Merge changes Id4441165,I14e0efe0,I0782c2f8 into audio-kernel.lnx.5.10

* changes:
  asoc: lpass-cdc: Add support for unified compander
  asoc: lpass-cdc: add lpass-cdc v2p5 register updates
  asoc: lpass-cdc: Enable compile lpass-cdc

asoc/codecs/lpass-cdc/Kbuild

@@ -30,6 +30,10 @@ ifeq ($(KERNEL_BUILD), 0)
 		include $(AUDIO_ROOT)/config/konaauto.conf
 		INCS    +=  -include $(AUDIO_ROOT)/config/konaautoconf.h
 	endif
+	ifeq ($(CONFIG_ARCH_WAIPIO), y)
+		include $(AUDIO_ROOT)/config/waipioauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/waipioautoconf.h
+	endif
 	ifeq ($(CONFIG_ARCH_LITO), y)
 		include $(AUDIO_ROOT)/config/litoauto.conf
 		export
@@ -76,6 +80,7 @@ COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
 # for LPASS_CDC Codec
 ifdef CONFIG_SND_SOC_LPASS_CDC
 	LPASS_CDC_OBJS += lpass-cdc.o
+	LPASS_CDC_OBJS += lpass-cdc-comp.o
 	LPASS_CDC_OBJS += lpass-cdc-utils.o
 	LPASS_CDC_OBJS += lpass-cdc-regmap.o
 	LPASS_CDC_OBJS += lpass-cdc-tables.o

asoc/codecs/lpass-cdc/Makefile

@@ -0,0 +1,6 @@
+modules:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

asoc/codecs/lpass-cdc/internal.h

@@ -102,10 +102,6 @@ int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg);
 
 extern const struct regmap_config lpass_cdc_regmap_config;
 extern u8 *lpass_cdc_reg_access[MAX_MACRO];
-extern u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX];
-extern u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX];
-extern u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX];
-extern u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX];
 extern const u16 macro_id_base_offset[MAX_MACRO];
 
 #endif

asoc/codecs/lpass-cdc/lpass-cdc-comp.c

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+#include "lpass-cdc-comp.h"
+
+int lpass_cdc_load_compander_coeff(struct snd_soc_component *component,
+				   u16 lsb_reg, u16 msb_reg,
+				   struct comp_coeff_val *comp_coeff_table,
+				   u16 arr_size)
+{
+	int i = 0;
+
+	/* Load Compander Coeff */
+	for (i = 0; i < arr_size; i++) {
+		snd_soc_component_write(component, lsb_reg,
+				comp_coeff_table[i].lsb);
+		snd_soc_component_write(component, msb_reg,
+				comp_coeff_table[i].msb);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(lpass_cdc_load_compander_coeff);
+
+int lpass_cdc_update_compander_setting(struct snd_soc_component *component,
+				       u16 start_addr, u8 *reg_val)
+{
+	u16 i = 0;
+
+	for (i = 0; i < COMP_MAX_SETTING; i++)
+		snd_soc_component_write(component,
+					start_addr + i * 4,
+					reg_val[i]);
+
+	return 0;
+}
+EXPORT_SYMBOL(lpass_cdc_update_compander_setting);

asoc/codecs/lpass-cdc/lpass-cdc-comp.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+#ifndef LPASS_CDC_COMP_H
+#define LPASS_CDC_COMP_H
+
+#include <sound/soc.h>
+
+#define COMP_MAX_SETTING 12
+
+struct comp_coeff_val {
+	u8 lsb;
+	u8 msb;
+};
+
+int lpass_cdc_load_compander_coeff(struct snd_soc_component *component,
+				   u16 lsb_reg, u16 msb_reg,
+				   struct comp_coeff_val *comp_coeff_table,
+				   u16 arr_size);
+int lpass_cdc_update_compander_setting(struct snd_soc_component *component,
+				       u16 start_addr, u8 *reg_val);
+
+#endif

asoc/codecs/lpass-cdc/lpass-cdc-registers.h

@@ -13,18 +13,11 @@
 #define LPASS_CDC_TX_TOP_CSR_TOP_CFG0		(TX_START_OFFSET + 0x0080)
 #define LPASS_CDC_TX_TOP_CSR_ANC_CFG		(TX_START_OFFSET + 0x0084)
 #define LPASS_CDC_TX_TOP_CSR_SWR_CTRL		(TX_START_OFFSET + 0x0088)
-#define LPASS_CDC_TX_TOP_CSR_FREQ_MCLK		(TX_START_OFFSET + 0x0090)
 #define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS		(TX_START_OFFSET + 0x0094)
 #define LPASS_CDC_TX_TOP_CSR_DEBUG_EN		(TX_START_OFFSET + 0x0098)
-#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL	(TX_START_OFFSET + 0x00A4)
+#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL		(TX_START_OFFSET + 0x00A4)
 #define LPASS_CDC_TX_TOP_CSR_I2S_CLK		(TX_START_OFFSET + 0x00A8)
 #define LPASS_CDC_TX_TOP_CSR_I2S_RESET		(TX_START_OFFSET + 0x00AC)
-#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL	(TX_START_OFFSET + 0x00C0)
-#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL	(TX_START_OFFSET + 0x00C4)
-#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL	(TX_START_OFFSET + 0x00C8)
-#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL	(TX_START_OFFSET + 0x00CC)
-#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL	(TX_START_OFFSET + 0x00D0)
-#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL	(TX_START_OFFSET + 0x00D4)
 #define LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL	(TX_START_OFFSET + 0x00C0)
 #define LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL	(TX_START_OFFSET + 0x00C4)
 #define LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL	(TX_START_OFFSET + 0x00C8)
@@ -47,22 +40,22 @@
 #define LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1	(TX_START_OFFSET + 0x0134)
 #define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0	(TX_START_OFFSET + 0x0138)
 #define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1	(TX_START_OFFSET + 0x013C)
-#define LPASS_CDC_TX_ANC0_CLK_RESET_CTL	(TX_START_OFFSET + 0x0200)
+#define LPASS_CDC_TX_ANC0_CLK_RESET_CTL		(TX_START_OFFSET + 0x0200)
 #define LPASS_CDC_TX_ANC0_MODE_1_CTL		(TX_START_OFFSET + 0x0204)
 #define LPASS_CDC_TX_ANC0_MODE_2_CTL		(TX_START_OFFSET + 0x0208)
 #define LPASS_CDC_TX_ANC0_FF_SHIFT		(TX_START_OFFSET + 0x020C)
 #define LPASS_CDC_TX_ANC0_FB_SHIFT		(TX_START_OFFSET + 0x0210)
-#define LPASS_CDC_TX_ANC0_LPF_FF_A_CTL	(TX_START_OFFSET + 0x0214)
-#define LPASS_CDC_TX_ANC0_LPF_FF_B_CTL	(TX_START_OFFSET + 0x0218)
-#define LPASS_CDC_TX_ANC0_LPF_FB_CTL	(TX_START_OFFSET + 0x021C)
-#define LPASS_CDC_TX_ANC0_SMLPF_CTL	(TX_START_OFFSET + 0x0220)
+#define LPASS_CDC_TX_ANC0_LPF_FF_A_CTL		(TX_START_OFFSET + 0x0214)
+#define LPASS_CDC_TX_ANC0_LPF_FF_B_CTL		(TX_START_OFFSET + 0x0218)
+#define LPASS_CDC_TX_ANC0_LPF_FB_CTL		(TX_START_OFFSET + 0x021C)
+#define LPASS_CDC_TX_ANC0_SMLPF_CTL		(TX_START_OFFSET + 0x0220)
 #define LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL	(TX_START_OFFSET + 0x0224)
-#define LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL	(TX_START_OFFSET + 0x0228)
+#define LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL		(TX_START_OFFSET + 0x0228)
 #define LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL	(TX_START_OFFSET + 0x022C)
 #define LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL	(TX_START_OFFSET + 0x0230)
-#define LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL	(TX_START_OFFSET + 0x0234)
-#define LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL	(TX_START_OFFSET + 0x0238)
-#define LPASS_CDC_TX_ANC0_FB_GAIN_CTL	(TX_START_OFFSET + 0x023C)
+#define LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL		(TX_START_OFFSET + 0x0234)
+#define LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL		(TX_START_OFFSET + 0x0238)
+#define LPASS_CDC_TX_ANC0_FB_GAIN_CTL		(TX_START_OFFSET + 0x023C)
 #define LPASS_CDC_TX0_TX_PATH_CTL	(TX_START_OFFSET + 0x0400)
 #define LPASS_CDC_TX0_TX_PATH_CFG0	(TX_START_OFFSET + 0x0404)
 #define LPASS_CDC_TX0_TX_PATH_CFG1	(TX_START_OFFSET + 0x0408)
@@ -158,6 +151,7 @@
 
 #define RX_START_OFFSET				0x1000
 #define LPASS_CDC_RX_TOP_TOP_CFG0		(RX_START_OFFSET + 0x0000)
+#define LPASS_CDC_RX_TOP_TOP_CFG1		(RX_START_OFFSET + 0x0004)
 #define LPASS_CDC_RX_TOP_SWR_CTRL		(RX_START_OFFSET + 0x0008)
 #define LPASS_CDC_RX_TOP_DEBUG			(RX_START_OFFSET + 0x000C)
 #define LPASS_CDC_RX_TOP_DEBUG_BUS		(RX_START_OFFSET + 0x0010)
@@ -260,13 +254,6 @@
 #define LPASS_CDC_RX_BCL_VBAT_ATTN1		(RX_START_OFFSET + 0x0300)
 #define LPASS_CDC_RX_BCL_VBAT_ATTN2		(RX_START_OFFSET + 0x0304)
 #define LPASS_CDC_RX_BCL_VBAT_ATTN3		(RX_START_OFFSET + 0x0308)
-#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1	(RX_START_OFFSET + 0x030C)
-#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2	(RX_START_OFFSET + 0x0310)
-#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1	(RX_START_OFFSET + 0x0314)
-#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2	(RX_START_OFFSET + 0x0318)
-#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3	(RX_START_OFFSET + 0x031C)
-#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4	(RX_START_OFFSET + 0x0320)
-#define LPASS_CDC_RX_BCL_VBAT_DECODE_ST	(RX_START_OFFSET + 0x0324)
 #define LPASS_CDC_RX_INTR_CTRL_CFG		(RX_START_OFFSET + 0x0340)
 #define LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT	(RX_START_OFFSET + 0x0344)
 #define LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0	(RX_START_OFFSET + 0x0360)
@@ -301,49 +288,137 @@
 #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4	(RX_START_OFFSET + 0x0450)
 #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5	(RX_START_OFFSET + 0x0454)
 #define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6	(RX_START_OFFSET + 0x0458)
-#define LPASS_CDC_RX_RX1_RX_PATH_CTL		(RX_START_OFFSET + 0x0480)
-#define LPASS_CDC_RX_RX1_RX_PATH_CFG0		(RX_START_OFFSET + 0x0484)
-#define LPASS_CDC_RX_RX1_RX_PATH_CFG1		(RX_START_OFFSET + 0x0488)
-#define LPASS_CDC_RX_RX1_RX_PATH_CFG2		(RX_START_OFFSET + 0x048C)
-#define LPASS_CDC_RX_RX1_RX_PATH_CFG3		(RX_START_OFFSET + 0x0490)
-#define LPASS_CDC_RX_RX1_RX_VOL_CTL		(RX_START_OFFSET + 0x0494)
-#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL	(RX_START_OFFSET + 0x0498)
-#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG	(RX_START_OFFSET + 0x049C)
-#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL	(RX_START_OFFSET + 0x04A0)
-#define LPASS_CDC_RX_RX1_RX_PATH_SEC1		(RX_START_OFFSET + 0x04A4)
-#define LPASS_CDC_RX_RX1_RX_PATH_SEC2		(RX_START_OFFSET + 0x04A8)
-#define LPASS_CDC_RX_RX1_RX_PATH_SEC3		(RX_START_OFFSET + 0x04AC)
-#define LPASS_CDC_RX_RX1_RX_PATH_SEC4		(RX_START_OFFSET + 0x04B0)
-#define LPASS_CDC_RX_RX1_RX_PATH_SEC7		(RX_START_OFFSET + 0x04B4)
-#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0	(RX_START_OFFSET + 0x04B8)
-#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1	(RX_START_OFFSET + 0x04BC)
-#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL	(RX_START_OFFSET + 0x04C0)
-#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1	(RX_START_OFFSET + 0x04C4)
-#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2	(RX_START_OFFSET + 0x04C8)
-#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3	(RX_START_OFFSET + 0x04CC)
-#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4	(RX_START_OFFSET + 0x04D0)
-#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5	(RX_START_OFFSET + 0x04D4)
-#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6	(RX_START_OFFSET + 0x04D8)
-#define LPASS_CDC_RX_RX2_RX_PATH_CTL		(RX_START_OFFSET + 0x0500)
-#define LPASS_CDC_RX_RX2_RX_PATH_CFG0		(RX_START_OFFSET + 0x0504)
-#define LPASS_CDC_RX_RX2_RX_PATH_CFG1		(RX_START_OFFSET + 0x0508)
-#define LPASS_CDC_RX_RX2_RX_PATH_CFG2		(RX_START_OFFSET + 0x050C)
-#define LPASS_CDC_RX_RX2_RX_PATH_CFG3		(RX_START_OFFSET + 0x0510)
-#define LPASS_CDC_RX_RX2_RX_VOL_CTL		(RX_START_OFFSET + 0x0514)
-#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL	(RX_START_OFFSET + 0x0518)
-#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG	(RX_START_OFFSET + 0x051C)
-#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL	(RX_START_OFFSET + 0x0520)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC0		(RX_START_OFFSET + 0x0524)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC1		(RX_START_OFFSET + 0x0528)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC2		(RX_START_OFFSET + 0x052C)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC3		(RX_START_OFFSET + 0x0530)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC4		(RX_START_OFFSET + 0x0534)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC5		(RX_START_OFFSET + 0x0538)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC6		(RX_START_OFFSET + 0x053C)
-#define LPASS_CDC_RX_RX2_RX_PATH_SEC7		(RX_START_OFFSET + 0x0540)
-#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0	(RX_START_OFFSET + 0x0544)
-#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1	(RX_START_OFFSET + 0x0548)
-#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL	(RX_START_OFFSET + 0x054C)
+#define LPASS_CDC_RX_RX0_RX_FIR_CTL		(RX_START_OFFSET + 0x045C)
+#define LPASS_CDC_RX_RX0_RX_FIR_CFG		(RX_START_OFFSET + 0x0460)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR	(RX_START_OFFSET + 0x0464)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0	(RX_START_OFFSET + 0x0468)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1	(RX_START_OFFSET + 0x046C)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2	(RX_START_OFFSET + 0x0470)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3	(RX_START_OFFSET + 0x0474)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4	(RX_START_OFFSET + 0x0478)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5	(RX_START_OFFSET + 0x047C)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6	(RX_START_OFFSET + 0x0480)
+#define LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7	(RX_START_OFFSET + 0x0484)
+#define LPASS_CDC_RX_RX1_RX_PATH_CTL		(RX_START_OFFSET + 0x04C0)
+#define LPASS_CDC_RX_RX1_RX_PATH_CFG0		(RX_START_OFFSET + 0x04C4)
+#define LPASS_CDC_RX_RX1_RX_PATH_CFG1		(RX_START_OFFSET + 0x04C8)
+#define LPASS_CDC_RX_RX1_RX_PATH_CFG2		(RX_START_OFFSET + 0x04CC)
+#define LPASS_CDC_RX_RX1_RX_PATH_CFG3		(RX_START_OFFSET + 0x04D0)
+#define LPASS_CDC_RX_RX1_RX_VOL_CTL		(RX_START_OFFSET + 0x04D4)
+#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL	(RX_START_OFFSET + 0x04D8)
+#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG	(RX_START_OFFSET + 0x04DC)
+#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL	(RX_START_OFFSET + 0x04E0)
+#define LPASS_CDC_RX_RX1_RX_PATH_SEC1		(RX_START_OFFSET + 0x04E4)
+#define LPASS_CDC_RX_RX1_RX_PATH_SEC2		(RX_START_OFFSET + 0x04E8)
+#define LPASS_CDC_RX_RX1_RX_PATH_SEC3		(RX_START_OFFSET + 0x04EC)
+#define LPASS_CDC_RX_RX1_RX_PATH_SEC4		(RX_START_OFFSET + 0x04F0)
+#define LPASS_CDC_RX_RX1_RX_PATH_SEC7		(RX_START_OFFSET + 0x04F4)
+#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0	(RX_START_OFFSET + 0x04F8)
+#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1	(RX_START_OFFSET + 0x04FC)
+#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL	(RX_START_OFFSET + 0x0500)
+#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1	(RX_START_OFFSET + 0x0504)
+#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2	(RX_START_OFFSET + 0x0508)
+#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3	(RX_START_OFFSET + 0x050C)
+#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4	(RX_START_OFFSET + 0x0510)
+#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5	(RX_START_OFFSET + 0x0514)
+#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6	(RX_START_OFFSET + 0x0518)
+#define LPASS_CDC_RX_RX1_RX_FIR_CTL		(RX_START_OFFSET + 0x051C)
+#define LPASS_CDC_RX_RX1_RX_FIR_CFG		(RX_START_OFFSET + 0x0520)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR	(RX_START_OFFSET + 0x0524)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0	(RX_START_OFFSET + 0x0528)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1	(RX_START_OFFSET + 0x052C)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2	(RX_START_OFFSET + 0x0530)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3	(RX_START_OFFSET + 0x0534)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4	(RX_START_OFFSET + 0x0538)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5	(RX_START_OFFSET + 0x053C)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6	(RX_START_OFFSET + 0x0540)
+#define LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7	(RX_START_OFFSET + 0x0544)
+#define LPASS_CDC_RX_RX2_RX_PATH_CTL		(RX_START_OFFSET + 0x0580)
+#define LPASS_CDC_RX_RX2_RX_PATH_CFG0		(RX_START_OFFSET + 0x0584)
+#define LPASS_CDC_RX_RX2_RX_PATH_CFG1		(RX_START_OFFSET + 0x0588)
+#define LPASS_CDC_RX_RX2_RX_PATH_CFG2		(RX_START_OFFSET + 0x058C)
+#define LPASS_CDC_RX_RX2_RX_PATH_CFG3		(RX_START_OFFSET + 0x0590)
+#define LPASS_CDC_RX_RX2_RX_VOL_CTL		(RX_START_OFFSET + 0x0594)
+#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL	(RX_START_OFFSET + 0x0598)
+#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG	(RX_START_OFFSET + 0x059C)
+#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL	(RX_START_OFFSET + 0x05A0)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC0		(RX_START_OFFSET + 0x05A4)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC1		(RX_START_OFFSET + 0x05A8)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC2		(RX_START_OFFSET + 0x05AC)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC3		(RX_START_OFFSET + 0x05B0)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC4		(RX_START_OFFSET + 0x05B4)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC5		(RX_START_OFFSET + 0x05B8)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC6		(RX_START_OFFSET + 0x05BC)
+#define LPASS_CDC_RX_RX2_RX_PATH_SEC7		(RX_START_OFFSET + 0x05C0)
+#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0	(RX_START_OFFSET + 0x05C4)
+#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1	(RX_START_OFFSET + 0x05C8)
+#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL	(RX_START_OFFSET + 0x05CC)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1	(RX_START_OFFSET + 0x0600)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2	(RX_START_OFFSET + 0x0604)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3	(RX_START_OFFSET + 0x0608)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1	(RX_START_OFFSET + 0x060C)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2	(RX_START_OFFSET + 0x0610)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3	(RX_START_OFFSET + 0x0614)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4	(RX_START_OFFSET + 0x0618)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5	(RX_START_OFFSET + 0x061C)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6	(RX_START_OFFSET + 0x0620)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7	(RX_START_OFFSET + 0x0624)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8	(RX_START_OFFSET + 0x0628)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1	(RX_START_OFFSET + 0x062C)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2	(RX_START_OFFSET + 0x0630)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3	(RX_START_OFFSET + 0x0634)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4	(RX_START_OFFSET + 0x0638)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1	(RX_START_OFFSET + 0x063C)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2	(RX_START_OFFSET + 0x0640)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3	(RX_START_OFFSET + 0x0644)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4	(RX_START_OFFSET + 0x0648)
+#define LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5	(RX_START_OFFSET + 0x064C)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL	(RX_START_OFFSET + 0x0680)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG		(RX_START_OFFSET + 0x0684)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1	(RX_START_OFFSET + 0x0688)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2	(RX_START_OFFSET + 0x068C)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3	(RX_START_OFFSET + 0x0690)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1	(RX_START_OFFSET + 0x0694)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2	(RX_START_OFFSET + 0x0698)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3	(RX_START_OFFSET + 0x069C)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1	(RX_START_OFFSET + 0x06A0)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2	(RX_START_OFFSET + 0x06A4)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1	(RX_START_OFFSET + 0x06A8)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2	(RX_START_OFFSET + 0x06AC)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3	(RX_START_OFFSET + 0x06B0)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4	(RX_START_OFFSET + 0x06B4)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1	(RX_START_OFFSET + 0x06B8)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2	(RX_START_OFFSET + 0x06BC)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3	(RX_START_OFFSET + 0x06C0)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4	(RX_START_OFFSET + 0x06C4)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5	(RX_START_OFFSET + 0x06C8)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1	(RX_START_OFFSET + 0x06CC)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON \
+						(RX_START_OFFSET + 0x06D0)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL \
+						(RX_START_OFFSET + 0x06D4)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN		(RX_START_OFFSET + 0x06D8)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
+						(RX_START_OFFSET + 0x06DC)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
+						(RX_START_OFFSET + 0x06E0)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
+						(RX_START_OFFSET + 0x06E4)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
+						(RX_START_OFFSET + 0x06E8)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
+						(RX_START_OFFSET + 0x06EC)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
+						(RX_START_OFFSET + 0x06F0)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
+						(RX_START_OFFSET + 0x06F4)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
+						(RX_START_OFFSET + 0x06F8)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
+						(RX_START_OFFSET + 0x06FC)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1	(RX_START_OFFSET + 0x0700)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2	(RX_START_OFFSET + 0x0704)
+#define LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3	(RX_START_OFFSET + 0x0708)
 #define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL	(RX_START_OFFSET + 0x0780)
 #define LPASS_CDC_RX_IDLE_DETECT_CFG0		(RX_START_OFFSET + 0x0784)
 #define LPASS_CDC_RX_IDLE_DETECT_CFG1		(RX_START_OFFSET + 0x0788)
@@ -357,14 +432,38 @@
 #define LPASS_CDC_RX_COMPANDER0_CTL5		(RX_START_OFFSET + 0x0814)
 #define LPASS_CDC_RX_COMPANDER0_CTL6		(RX_START_OFFSET + 0x0818)
 #define LPASS_CDC_RX_COMPANDER0_CTL7		(RX_START_OFFSET + 0x081C)
-#define LPASS_CDC_RX_COMPANDER1_CTL0		(RX_START_OFFSET + 0x0840)
-#define LPASS_CDC_RX_COMPANDER1_CTL1		(RX_START_OFFSET + 0x0844)
-#define LPASS_CDC_RX_COMPANDER1_CTL2		(RX_START_OFFSET + 0x0848)
-#define LPASS_CDC_RX_COMPANDER1_CTL3		(RX_START_OFFSET + 0x084C)
-#define LPASS_CDC_RX_COMPANDER1_CTL4		(RX_START_OFFSET + 0x0850)
-#define LPASS_CDC_RX_COMPANDER1_CTL5		(RX_START_OFFSET + 0x0854)
-#define LPASS_CDC_RX_COMPANDER1_CTL6		(RX_START_OFFSET + 0x0858)
-#define LPASS_CDC_RX_COMPANDER1_CTL7		(RX_START_OFFSET + 0x085C)
+#define LPASS_CDC_RX_COMPANDER0_CTL8		(RX_START_OFFSET + 0x0820)
+#define LPASS_CDC_RX_COMPANDER0_CTL9		(RX_START_OFFSET + 0x0820)
+#define LPASS_CDC_RX_COMPANDER0_CTL10		(RX_START_OFFSET + 0x0824)
+#define LPASS_CDC_RX_COMPANDER0_CTL11		(RX_START_OFFSET + 0x0828)
+#define LPASS_CDC_RX_COMPANDER0_CTL12		(RX_START_OFFSET + 0x082C)
+#define LPASS_CDC_RX_COMPANDER0_CTL13		(RX_START_OFFSET + 0x0830)
+#define LPASS_CDC_RX_COMPANDER0_CTL14		(RX_START_OFFSET + 0x0834)
+#define LPASS_CDC_RX_COMPANDER0_CTL15		(RX_START_OFFSET + 0x0838)
+#define LPASS_CDC_RX_COMPANDER0_CTL16		(RX_START_OFFSET + 0x083C)
+#define LPASS_CDC_RX_COMPANDER0_CTL17		(RX_START_OFFSET + 0x0840)
+#define LPASS_CDC_RX_COMPANDER0_CTL18		(RX_START_OFFSET + 0x0848)
+#define LPASS_CDC_RX_COMPANDER0_CTL19		(RX_START_OFFSET + 0x084C)
+#define LPASS_CDC_RX_COMPANDER1_CTL0		(RX_START_OFFSET + 0x0860)
+#define LPASS_CDC_RX_COMPANDER1_CTL1		(RX_START_OFFSET + 0x0864)
+#define LPASS_CDC_RX_COMPANDER1_CTL2		(RX_START_OFFSET + 0x0868)
+#define LPASS_CDC_RX_COMPANDER1_CTL3		(RX_START_OFFSET + 0x086C)
+#define LPASS_CDC_RX_COMPANDER1_CTL4		(RX_START_OFFSET + 0x0870)
+#define LPASS_CDC_RX_COMPANDER1_CTL5		(RX_START_OFFSET + 0x0874)
+#define LPASS_CDC_RX_COMPANDER1_CTL6		(RX_START_OFFSET + 0x0878)
+#define LPASS_CDC_RX_COMPANDER1_CTL7		(RX_START_OFFSET + 0x087C)
+#define LPASS_CDC_RX_COMPANDER1_CTL8		(RX_START_OFFSET + 0x0880)
+#define LPASS_CDC_RX_COMPANDER1_CTL9		(RX_START_OFFSET + 0x0884)
+#define LPASS_CDC_RX_COMPANDER1_CTL10		(RX_START_OFFSET + 0x0888)
+#define LPASS_CDC_RX_COMPANDER1_CTL11		(RX_START_OFFSET + 0x088C)
+#define LPASS_CDC_RX_COMPANDER1_CTL12		(RX_START_OFFSET + 0x0890)
+#define LPASS_CDC_RX_COMPANDER1_CTL13		(RX_START_OFFSET + 0x0894)
+#define LPASS_CDC_RX_COMPANDER1_CTL14		(RX_START_OFFSET + 0x0898)
+#define LPASS_CDC_RX_COMPANDER1_CTL15		(RX_START_OFFSET + 0x089C)
+#define LPASS_CDC_RX_COMPANDER1_CTL16		(RX_START_OFFSET + 0x08A0)
+#define LPASS_CDC_RX_COMPANDER1_CTL17		(RX_START_OFFSET + 0x08A4)
+#define LPASS_CDC_RX_COMPANDER1_CTL18		(RX_START_OFFSET + 0x08A8)
+#define LPASS_CDC_RX_COMPANDER1_CTL19		(RX_START_OFFSET + 0x08AC)
 #define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
 						(RX_START_OFFSET + 0x0A00)
 #define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
@@ -509,6 +608,19 @@
 #define LPASS_CDC_WSA_TOP_TX_I2S_CTL		(WSA_START_OFFSET + 0x00A0)
 #define LPASS_CDC_WSA_TOP_I2S_CLK		(WSA_START_OFFSET + 0x00A4)
 #define LPASS_CDC_WSA_TOP_I2S_RESET		(WSA_START_OFFSET + 0x00A8)
+#define LPASS_CDC_WSA_TOP_FS_UNGATE		(WSA_START_OFFSET + 0x00AC)
+#define LPASS_CDC_WSA_TOP_GRP_SEL		(WSA_START_OFFSET + 0x00B0)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB	(WSA_START_OFFSET + 0x00B4)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB	(WSA_START_OFFSET + 0x00B8)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT	(WSA_START_OFFSET + 0x00BC)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB	(WSA_START_OFFSET + 0x00C0)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB	(WSA_START_OFFSET + 0x00C4)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB	(WSA_START_OFFSET + 0x00C8)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB	(WSA_START_OFFSET + 0x00CC)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT	(WSA_START_OFFSET + 0x00D0)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB	(WSA_START_OFFSET + 0x00D4)
+#define LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB	(WSA_START_OFFSET + 0x00D8)
+#define LPASS_CDC_WSA_TOP_FS_UNGATE2		(WSA_START_OFFSET + 0x00DC)
 #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0	(WSA_START_OFFSET + 0x0100)
 #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1	(WSA_START_OFFSET + 0x0104)
 #define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0	(WSA_START_OFFSET + 0x0108)
@@ -563,19 +675,6 @@
 #define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1	(WSA_START_OFFSET + 0x0200)
 #define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2	(WSA_START_OFFSET + 0x0204)
 #define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3	(WSA_START_OFFSET + 0x0208)
-#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1 \
-						(WSA_START_OFFSET + 0x020C)
-#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2 \
-						(WSA_START_OFFSET + 0x0210)
-#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1 \
-						(WSA_START_OFFSET + 0x0214)
-#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2 \
-						(WSA_START_OFFSET + 0x0218)
-#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3 \
-						(WSA_START_OFFSET + 0x021C)
-#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4 \
-						(WSA_START_OFFSET + 0x0220)
-#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST	(WSA_START_OFFSET + 0x0224)
 #define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL	(WSA_START_OFFSET + 0x0244)
 #define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0	(WSA_START_OFFSET + 0x0248)
 #define LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL	(WSA_START_OFFSET + 0x0264)
@@ -649,53 +748,126 @@
 #define LPASS_CDC_WSA_COMPANDER0_CTL5		(WSA_START_OFFSET + 0x0594)
 #define LPASS_CDC_WSA_COMPANDER0_CTL6		(WSA_START_OFFSET + 0x0598)
 #define LPASS_CDC_WSA_COMPANDER0_CTL7		(WSA_START_OFFSET + 0x059C)
-#define LPASS_CDC_WSA_COMPANDER1_CTL0		(WSA_START_OFFSET + 0x05C0)
-#define LPASS_CDC_WSA_COMPANDER1_CTL1		(WSA_START_OFFSET + 0x05C4)
-#define LPASS_CDC_WSA_COMPANDER1_CTL2		(WSA_START_OFFSET + 0x05C8)
-#define LPASS_CDC_WSA_COMPANDER1_CTL3		(WSA_START_OFFSET + 0x05CC)
-#define LPASS_CDC_WSA_COMPANDER1_CTL4		(WSA_START_OFFSET + 0x05D0)
-#define LPASS_CDC_WSA_COMPANDER1_CTL5		(WSA_START_OFFSET + 0x05D4)
-#define LPASS_CDC_WSA_COMPANDER1_CTL6		(WSA_START_OFFSET + 0x05D8)
-#define LPASS_CDC_WSA_COMPANDER1_CTL7		(WSA_START_OFFSET + 0x05DC)
-#define LPASS_CDC_WSA_SOFTCLIP0_CRC		(WSA_START_OFFSET + 0x0600)
-#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL	(WSA_START_OFFSET + 0x0604)
-#define LPASS_CDC_WSA_SOFTCLIP1_CRC		(WSA_START_OFFSET + 0x0640)
-#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL	(WSA_START_OFFSET + 0x0644)
+#define LPASS_CDC_WSA_COMPANDER0_CTL8		(WSA_START_OFFSET + 0x05A0)
+#define LPASS_CDC_WSA_COMPANDER0_CTL9		(WSA_START_OFFSET + 0x05A4)
+#define LPASS_CDC_WSA_COMPANDER0_CTL10		(WSA_START_OFFSET + 0x05A8)
+#define LPASS_CDC_WSA_COMPANDER0_CTL11		(WSA_START_OFFSET + 0x05AC)
+#define LPASS_CDC_WSA_COMPANDER0_CTL12		(WSA_START_OFFSET + 0x05B0)
+#define LPASS_CDC_WSA_COMPANDER0_CTL13		(WSA_START_OFFSET + 0x05B4)
+#define LPASS_CDC_WSA_COMPANDER0_CTL14		(WSA_START_OFFSET + 0x05B8)
+#define LPASS_CDC_WSA_COMPANDER0_CTL15		(WSA_START_OFFSET + 0x05BC)
+#define LPASS_CDC_WSA_COMPANDER0_CTL16		(WSA_START_OFFSET + 0x05C0)
+#define LPASS_CDC_WSA_COMPANDER0_CTL17		(WSA_START_OFFSET + 0x05C4)
+#define LPASS_CDC_WSA_COMPANDER0_CTL18		(WSA_START_OFFSET + 0x05C8)
+#define LPASS_CDC_WSA_COMPANDER0_CTL19		(WSA_START_OFFSET + 0x05CC)
+#define LPASS_CDC_WSA_COMPANDER1_CTL0		(WSA_START_OFFSET + 0x05E0)
+#define LPASS_CDC_WSA_COMPANDER1_CTL1		(WSA_START_OFFSET + 0x05E4)
+#define LPASS_CDC_WSA_COMPANDER1_CTL2		(WSA_START_OFFSET + 0x05E8)
+#define LPASS_CDC_WSA_COMPANDER1_CTL3		(WSA_START_OFFSET + 0x05EC)
+#define LPASS_CDC_WSA_COMPANDER1_CTL4		(WSA_START_OFFSET + 0x05F0)
+#define LPASS_CDC_WSA_COMPANDER1_CTL5		(WSA_START_OFFSET + 0x05F4)
+#define LPASS_CDC_WSA_COMPANDER1_CTL6		(WSA_START_OFFSET + 0x05F8)
+#define LPASS_CDC_WSA_COMPANDER1_CTL7		(WSA_START_OFFSET + 0x05FC)
+#define LPASS_CDC_WSA_COMPANDER1_CTL8		(WSA_START_OFFSET + 0x0600)
+#define LPASS_CDC_WSA_COMPANDER1_CTL9		(WSA_START_OFFSET + 0x0604)
+#define LPASS_CDC_WSA_COMPANDER1_CTL10		(WSA_START_OFFSET + 0x0608)
+#define LPASS_CDC_WSA_COMPANDER1_CTL11		(WSA_START_OFFSET + 0x060C)
+#define LPASS_CDC_WSA_COMPANDER1_CTL12		(WSA_START_OFFSET + 0x0610)
+#define LPASS_CDC_WSA_COMPANDER1_CTL13		(WSA_START_OFFSET + 0x0614)
+#define LPASS_CDC_WSA_COMPANDER1_CTL14		(WSA_START_OFFSET + 0x0618)
+#define LPASS_CDC_WSA_COMPANDER1_CTL15		(WSA_START_OFFSET + 0x061C)
+#define LPASS_CDC_WSA_COMPANDER1_CTL16		(WSA_START_OFFSET + 0x0620)
+#define LPASS_CDC_WSA_COMPANDER1_CTL17		(WSA_START_OFFSET + 0x0624)
+#define LPASS_CDC_WSA_COMPANDER1_CTL18		(WSA_START_OFFSET + 0x0628)
+#define LPASS_CDC_WSA_COMPANDER1_CTL19		(WSA_START_OFFSET + 0x062C)
+#define LPASS_CDC_WSA_SOFTCLIP0_CRC		(WSA_START_OFFSET + 0x0640)
+#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL	(WSA_START_OFFSET + 0x0644)
+#define LPASS_CDC_WSA_SOFTCLIP1_CRC		(WSA_START_OFFSET + 0x0660)
+#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL	(WSA_START_OFFSET + 0x0664)
 #define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL \
 						(WSA_START_OFFSET + 0x0680)
 #define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0	(WSA_START_OFFSET + 0x0684)
 #define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL \
 						(WSA_START_OFFSET + 0x06C0)
 #define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0	(WSA_START_OFFSET + 0x06C4)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL	(WSA_START_OFFSET + 0x0700)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL0	(WSA_START_OFFSET + 0x0704)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL1	(WSA_START_OFFSET + 0x0708)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL	(WSA_START_OFFSET + 0x070C)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB \
-						(WSA_START_OFFSET + 0x0710)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB \
-						(WSA_START_OFFSET + 0x0714)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB \
-						(WSA_START_OFFSET + 0x0718)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB \
-						(WSA_START_OFFSET + 0x071C)
-#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO	(WSA_START_OFFSET + 0x0720)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL	(WSA_START_OFFSET + 0x0740)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL0	(WSA_START_OFFSET + 0x0744)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL1	(WSA_START_OFFSET + 0x0748)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL	(WSA_START_OFFSET + 0x074C)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB \
-						(WSA_START_OFFSET + 0x0750)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB \
-						(WSA_START_OFFSET + 0x0754)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB \
-						(WSA_START_OFFSET + 0x0758)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB \
-						(WSA_START_OFFSET + 0x075C)
-#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO	(WSA_START_OFFSET + 0x0760)
-#define WSA_MAX_OFFSET				(WSA_START_OFFSET + 0x0760)
+#define LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL	(WSA_START_OFFSET + 0x0780)
+#define LPASS_CDC_WSA_IDLE_DETECT_CFG0		(WSA_START_OFFSET + 0x0784)
+#define LPASS_CDC_WSA_IDLE_DETECT_CFG1		(WSA_START_OFFSET + 0x0788)
+#define LPASS_CDC_WSA_IDLE_DETECT_CFG2		(WSA_START_OFFSET + 0x078C)
+#define LPASS_CDC_WSA_IDLE_DETECT_CFG3		(WSA_START_OFFSET + 0x0790)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1	(WSA_START_OFFSET + 0x0900)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2	(WSA_START_OFFSET + 0x0904)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3	(WSA_START_OFFSET + 0x0908)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1	(WSA_START_OFFSET + 0x090C)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2	(WSA_START_OFFSET + 0x0910)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3	(WSA_START_OFFSET + 0x0914)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4	(WSA_START_OFFSET + 0x0918)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5	(WSA_START_OFFSET + 0x091C)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6	(WSA_START_OFFSET + 0x0920)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7	(WSA_START_OFFSET + 0x0924)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8	(WSA_START_OFFSET + 0x0928)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1 \
+						(WSA_START_OFFSET + 0x092C)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2 \
+						(WSA_START_OFFSET + 0x0930)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3 \
+						(WSA_START_OFFSET + 0x0934)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4 \
+						(WSA_START_OFFSET + 0x0938)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1	(WSA_START_OFFSET + 0x093C)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2	(WSA_START_OFFSET + 0x0940)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3	(WSA_START_OFFSET + 0x0944)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4	(WSA_START_OFFSET + 0x0948)
+#define LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5	(WSA_START_OFFSET + 0x094C)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL	(WSA_START_OFFSET + 0x0980)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG	(WSA_START_OFFSET + 0x0984)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1	(WSA_START_OFFSET + 0x0988)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2	(WSA_START_OFFSET + 0x098C)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3	(WSA_START_OFFSET + 0x0990)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1	(WSA_START_OFFSET + 0x0994)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2	(WSA_START_OFFSET + 0x0998)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3	(WSA_START_OFFSET + 0x099C)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1	(WSA_START_OFFSET + 0x09A0)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC2	(WSA_START_OFFSET + 0x09A4)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1	(WSA_START_OFFSET + 0x09A8)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2	(WSA_START_OFFSET + 0x09AC)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3	(WSA_START_OFFSET + 0x09B0)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4	(WSA_START_OFFSET + 0x09B4)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1	(WSA_START_OFFSET + 0x09B8)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2	(WSA_START_OFFSET + 0x09BC)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3	(WSA_START_OFFSET + 0x09C0)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4	(WSA_START_OFFSET + 0x09C4)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5	(WSA_START_OFFSET + 0x09C8)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1	(WSA_START_OFFSET + 0x09CC)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON \
+						(WSA_START_OFFSET + 0x09D0)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL \
+						(WSA_START_OFFSET + 0x09D4)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN	(WSA_START_OFFSET + 0x09D8)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
+						(WSA_START_OFFSET + 0x09DC)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
+						(WSA_START_OFFSET + 0x09E0)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
+						(WSA_START_OFFSET + 0x09E4)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
+						(WSA_START_OFFSET + 0x09E8)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
+						(WSA_START_OFFSET + 0x09EC)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
+						(WSA_START_OFFSET + 0x09F0)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
+						(WSA_START_OFFSET + 0x09F4)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
+						(WSA_START_OFFSET + 0x09F8)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
+						(WSA_START_OFFSET + 0x09FC)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1	(WSA_START_OFFSET + 0x0A00)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2	(WSA_START_OFFSET + 0x0A04)
+#define LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3	(WSA_START_OFFSET + 0x0A08)
+#define WSA_MAX_OFFSET				(WSA_START_OFFSET + 0x0A08)
 
-#define LPASS_CDC_WSA_MACRO_MAX 0x1D9 /* 0x760/4 = 0x1D8 + 1 registers */
+#define LPASS_CDC_WSA_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */
 
 /* VA macro registers */
 #define VA_START_OFFSET				0x3000
@@ -711,22 +883,18 @@
 #define LPASS_CDC_VA_TOP_CSR_DMIC_CFG		(VA_START_OFFSET + 0x0094)
 #define LPASS_CDC_VA_TOP_CSR_DEBUG_BUS		(VA_START_OFFSET + 0x009C)
 #define LPASS_CDC_VA_TOP_CSR_DEBUG_EN		(VA_START_OFFSET + 0x00A0)
-#define LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL	(VA_START_OFFSET + 0x00A4)
+#define LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL		(VA_START_OFFSET + 0x00A4)
 #define LPASS_CDC_VA_TOP_CSR_I2S_CLK		(VA_START_OFFSET + 0x00A8)
 #define LPASS_CDC_VA_TOP_CSR_I2S_RESET		(VA_START_OFFSET + 0x00AC)
+#define LPASS_CDC_VA_TOP_CSR_DEBUG_CLK		(VA_START_OFFSET + 0x00B0)
 #define LPASS_CDC_VA_TOP_CSR_CORE_ID_0		(VA_START_OFFSET + 0x00C0)
 #define LPASS_CDC_VA_TOP_CSR_CORE_ID_1		(VA_START_OFFSET + 0x00C4)
 #define LPASS_CDC_VA_TOP_CSR_CORE_ID_2		(VA_START_OFFSET + 0x00C8)
 #define LPASS_CDC_VA_TOP_CSR_CORE_ID_3		(VA_START_OFFSET + 0x00CC)
-#define VA_TOP_MAX_OFFSET			(VA_START_OFFSET + 0x00CC)
-
-#define LPASS_CDC_VA_MACRO_TOP_MAX 0x34 /* 0x0CC/4 = 0x33 + 1 = 0x34 */
-
 #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0	(VA_START_OFFSET + 0x00D0)
 #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1	(VA_START_OFFSET + 0x00D4)
 #define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2	(VA_START_OFFSET + 0x00D8)
 #define LPASS_CDC_VA_TOP_CSR_SWR_CTRL		(VA_START_OFFSET + 0x00DC)
-
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0	(VA_START_OFFSET + 0x0100)
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1	(VA_START_OFFSET + 0x0104)
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0	(VA_START_OFFSET + 0x0108)
@@ -735,15 +903,6 @@
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1	(VA_START_OFFSET + 0x0114)
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0	(VA_START_OFFSET + 0x0118)
 #define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1	(VA_START_OFFSET + 0x011C)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0	(VA_START_OFFSET + 0x0120)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1	(VA_START_OFFSET + 0x0124)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0	(VA_START_OFFSET + 0x0128)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1	(VA_START_OFFSET + 0x012C)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0	(VA_START_OFFSET + 0x0130)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1	(VA_START_OFFSET + 0x0134)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0	(VA_START_OFFSET + 0x0138)
-#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1	(VA_START_OFFSET + 0x013C)
-
 #define LPASS_CDC_VA_TX0_TX_PATH_CTL	(VA_START_OFFSET + 0x0400)
 #define LPASS_CDC_VA_TX0_TX_PATH_CFG0	(VA_START_OFFSET + 0x0404)
 #define LPASS_CDC_VA_TX0_TX_PATH_CFG1	(VA_START_OFFSET + 0x0408)
@@ -789,55 +948,290 @@
 #define LPASS_CDC_VA_TX3_TX_PATH_SEC4	(VA_START_OFFSET + 0x05A0)
 #define LPASS_CDC_VA_TX3_TX_PATH_SEC5	(VA_START_OFFSET + 0x05A4)
 #define LPASS_CDC_VA_TX3_TX_PATH_SEC6	(VA_START_OFFSET + 0x05A8)
-#define LPASS_CDC_VA_TX4_TX_PATH_CTL	(VA_START_OFFSET + 0x0600)
-#define LPASS_CDC_VA_TX4_TX_PATH_CFG0	(VA_START_OFFSET + 0x0604)
-#define LPASS_CDC_VA_TX4_TX_PATH_CFG1	(VA_START_OFFSET + 0x0608)
-#define LPASS_CDC_VA_TX4_TX_VOL_CTL	(VA_START_OFFSET + 0x060C)
-#define LPASS_CDC_VA_TX4_TX_PATH_SEC0	(VA_START_OFFSET + 0x0610)
-#define LPASS_CDC_VA_TX4_TX_PATH_SEC1	(VA_START_OFFSET + 0x0614)
-#define LPASS_CDC_VA_TX4_TX_PATH_SEC2	(VA_START_OFFSET + 0x0618)
-#define LPASS_CDC_VA_TX4_TX_PATH_SEC3	(VA_START_OFFSET + 0x061C)
-#define LPASS_CDC_VA_TX4_TX_PATH_SEC4	(VA_START_OFFSET + 0x0620)
-#define LPASS_CDC_VA_TX4_TX_PATH_SEC5	(VA_START_OFFSET + 0x0624)
-#define LPASS_CDC_VA_TX4_TX_PATH_SEC6	(VA_START_OFFSET + 0x0628)
-#define LPASS_CDC_VA_TX5_TX_PATH_CTL	(VA_START_OFFSET + 0x0680)
-#define LPASS_CDC_VA_TX5_TX_PATH_CFG0	(VA_START_OFFSET + 0x0684)
-#define LPASS_CDC_VA_TX5_TX_PATH_CFG1	(VA_START_OFFSET + 0x0688)
-#define LPASS_CDC_VA_TX5_TX_VOL_CTL	(VA_START_OFFSET + 0x068C)
-#define LPASS_CDC_VA_TX5_TX_PATH_SEC0	(VA_START_OFFSET + 0x0690)
-#define LPASS_CDC_VA_TX5_TX_PATH_SEC1	(VA_START_OFFSET + 0x0694)
-#define LPASS_CDC_VA_TX5_TX_PATH_SEC2	(VA_START_OFFSET + 0x0698)
-#define LPASS_CDC_VA_TX5_TX_PATH_SEC3	(VA_START_OFFSET + 0x069C)
-#define LPASS_CDC_VA_TX5_TX_PATH_SEC4	(VA_START_OFFSET + 0x06A0)
-#define LPASS_CDC_VA_TX5_TX_PATH_SEC5	(VA_START_OFFSET + 0x06A4)
-#define LPASS_CDC_VA_TX5_TX_PATH_SEC6	(VA_START_OFFSET + 0x06A8)
-#define LPASS_CDC_VA_TX6_TX_PATH_CTL	(VA_START_OFFSET + 0x0700)
-#define LPASS_CDC_VA_TX6_TX_PATH_CFG0	(VA_START_OFFSET + 0x0704)
-#define LPASS_CDC_VA_TX6_TX_PATH_CFG1	(VA_START_OFFSET + 0x0708)
-#define LPASS_CDC_VA_TX6_TX_VOL_CTL	(VA_START_OFFSET + 0x070C)
-#define LPASS_CDC_VA_TX6_TX_PATH_SEC0	(VA_START_OFFSET + 0x0710)
-#define LPASS_CDC_VA_TX6_TX_PATH_SEC1	(VA_START_OFFSET + 0x0714)
-#define LPASS_CDC_VA_TX6_TX_PATH_SEC2	(VA_START_OFFSET + 0x0718)
-#define LPASS_CDC_VA_TX6_TX_PATH_SEC3	(VA_START_OFFSET + 0x071C)
-#define LPASS_CDC_VA_TX6_TX_PATH_SEC4	(VA_START_OFFSET + 0x0720)
-#define LPASS_CDC_VA_TX6_TX_PATH_SEC5	(VA_START_OFFSET + 0x0724)
-#define LPASS_CDC_VA_TX6_TX_PATH_SEC6	(VA_START_OFFSET + 0x0728)
-#define LPASS_CDC_VA_TX7_TX_PATH_CTL	(VA_START_OFFSET + 0x0780)
-#define LPASS_CDC_VA_TX7_TX_PATH_CFG0	(VA_START_OFFSET + 0x0784)
-#define LPASS_CDC_VA_TX7_TX_PATH_CFG1	(VA_START_OFFSET + 0x0788)
-#define LPASS_CDC_VA_TX7_TX_VOL_CTL	(VA_START_OFFSET + 0x078C)
-#define LPASS_CDC_VA_TX7_TX_PATH_SEC0	(VA_START_OFFSET + 0x0790)
-#define LPASS_CDC_VA_TX7_TX_PATH_SEC1	(VA_START_OFFSET + 0x0794)
-#define LPASS_CDC_VA_TX7_TX_PATH_SEC2	(VA_START_OFFSET + 0x0798)
-#define LPASS_CDC_VA_TX7_TX_PATH_SEC3	(VA_START_OFFSET + 0x079C)
-#define LPASS_CDC_VA_TX7_TX_PATH_SEC4	(VA_START_OFFSET + 0x07A0)
-#define LPASS_CDC_VA_TX7_TX_PATH_SEC5	(VA_START_OFFSET + 0x07A4)
-#define LPASS_CDC_VA_TX7_TX_PATH_SEC6	(VA_START_OFFSET + 0x07A8)
-#define VA_MAX_OFFSET			(VA_START_OFFSET + 0x07A8)
+#define VA_MAX_OFFSET			(VA_START_OFFSET + 0x05A8)
+
+#define LPASS_CDC_VA_MACRO_MAX 0x16B /* 5A8/4 = 16A + 1 = 16B */
+
+/* WSA2 - macro#5 */
+#define WSA2_START_OFFSET			0x4000
+#define LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL \
+						(WSA2_START_OFFSET + 0x0000)
+#define LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL \
+						(WSA2_START_OFFSET + 0x0004)
+#define LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL	(WSA2_START_OFFSET + 0x0008)
+#define LPASS_CDC_WSA2_TOP_TOP_CFG0		(WSA2_START_OFFSET + 0x0080)
+#define LPASS_CDC_WSA2_TOP_TOP_CFG1		(WSA2_START_OFFSET + 0x0084)
+#define LPASS_CDC_WSA2_TOP_FREQ_MCLK		(WSA2_START_OFFSET + 0x0088)
+#define LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL	(WSA2_START_OFFSET + 0x008C)
+#define LPASS_CDC_WSA2_TOP_DEBUG_EN0		(WSA2_START_OFFSET + 0x0090)
+#define LPASS_CDC_WSA2_TOP_DEBUG_EN1		(WSA2_START_OFFSET + 0x0094)
+#define LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB		(WSA2_START_OFFSET + 0x0098)
+#define LPASS_CDC_WSA2_TOP_RX_I2S_CTL		(WSA2_START_OFFSET + 0x009C)
+#define LPASS_CDC_WSA2_TOP_TX_I2S_CTL		(WSA2_START_OFFSET + 0x00A0)
+#define LPASS_CDC_WSA2_TOP_I2S_CLK		(WSA2_START_OFFSET + 0x00A4)
+#define LPASS_CDC_WSA2_TOP_I2S_RESET		(WSA2_START_OFFSET + 0x00A8)
+#define LPASS_CDC_WSA2_TOP_FS_UNGATE		(WSA2_START_OFFSET + 0x00AC)
+#define LPASS_CDC_WSA2_TOP_GRP_SEL		(WSA2_START_OFFSET + 0x00B0)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB	(WSA2_START_OFFSET + 0x00B4)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB	(WSA2_START_OFFSET + 0x00B8)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT	(WSA2_START_OFFSET + 0x00BC)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB	(WSA2_START_OFFSET + 0x00C0)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB	(WSA2_START_OFFSET + 0x00C4)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB	(WSA2_START_OFFSET + 0x00C8)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB	(WSA2_START_OFFSET + 0x00CC)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT	(WSA2_START_OFFSET + 0x00D0)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB	(WSA2_START_OFFSET + 0x00D4)
+#define LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB	(WSA2_START_OFFSET + 0x00D8)
+#define LPASS_CDC_WSA2_TOP_FS_UNGATE2		(WSA2_START_OFFSET + 0x00DC)
+#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0	(WSA2_START_OFFSET + 0x0100)
+#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1	(WSA2_START_OFFSET + 0x0104)
+#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0	(WSA2_START_OFFSET + 0x0108)
+#define LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1	(WSA2_START_OFFSET + 0x010C)
+#define LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0	(WSA2_START_OFFSET + 0x0110)
+#define LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0	(WSA2_START_OFFSET + 0x0114)
+#define LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0	(WSA2_START_OFFSET + 0x0118)
+/* VBAT registers  */
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL	(WSA2_START_OFFSET + 0x0180)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG	(WSA2_START_OFFSET + 0x0184)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1	(WSA2_START_OFFSET + 0x0188)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2	(WSA2_START_OFFSET + 0x018C)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3	(WSA2_START_OFFSET + 0x0190)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1	(WSA2_START_OFFSET + 0x0194)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2	(WSA2_START_OFFSET + 0x0198)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3	(WSA2_START_OFFSET + 0x019C)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1	(WSA2_START_OFFSET + 0x01A0)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2	(WSA2_START_OFFSET + 0x01A4)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1	(WSA2_START_OFFSET + 0x01A8)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2	(WSA2_START_OFFSET + 0x01AC)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3	(WSA2_START_OFFSET + 0x01B0)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4	(WSA2_START_OFFSET + 0x01B4)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1	(WSA2_START_OFFSET + 0x01B8)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2	(WSA2_START_OFFSET + 0x01BC)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3	(WSA2_START_OFFSET + 0x01C0)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4	(WSA2_START_OFFSET + 0x01C4)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5	(WSA2_START_OFFSET + 0x01C8)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1	(WSA2_START_OFFSET + 0x01CC)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON \
+						(WSA2_START_OFFSET + 0x01D0)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL \
+						(WSA2_START_OFFSET + 0x01D4)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN	(WSA2_START_OFFSET + 0x01D8)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \
+						(WSA2_START_OFFSET + 0x01DC)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \
+						(WSA2_START_OFFSET + 0x01E0)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \
+						(WSA2_START_OFFSET + 0x01E4)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \
+						(WSA2_START_OFFSET + 0x01E8)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \
+						(WSA2_START_OFFSET + 0x01EC)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \
+						(WSA2_START_OFFSET + 0x01F0)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \
+						(WSA2_START_OFFSET + 0x01F4)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \
+						(WSA2_START_OFFSET + 0x01F8)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \
+						(WSA2_START_OFFSET + 0x01FC)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1	(WSA2_START_OFFSET + 0x0200)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2	(WSA2_START_OFFSET + 0x0204)
+#define LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3	(WSA2_START_OFFSET + 0x0208)
+#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL	(WSA2_START_OFFSET + 0x0244)
+#define LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0	(WSA2_START_OFFSET + 0x0248)
+#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL	(WSA2_START_OFFSET + 0x0264)
+#define LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0	(WSA2_START_OFFSET + 0x0268)
+#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL	(WSA2_START_OFFSET + 0x0284)
+#define LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0	(WSA2_START_OFFSET + 0x0288)
+#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL	(WSA2_START_OFFSET + 0x02A4)
+#define LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0	(WSA2_START_OFFSET + 0x02A8)
+#define LPASS_CDC_WSA2_INTR_CTRL_CFG		(WSA2_START_OFFSET + 0x0340)
+#define LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT	(WSA2_START_OFFSET + 0x0344)
+#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0	(WSA2_START_OFFSET + 0x0360)
+#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0	(WSA2_START_OFFSET + 0x0368)
+#define LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0	(WSA2_START_OFFSET + 0x0370)
+#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0	(WSA2_START_OFFSET + 0x0380)
+#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0	(WSA2_START_OFFSET + 0x0388)
+#define LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0	(WSA2_START_OFFSET + 0x0390)
+#define LPASS_CDC_WSA2_INTR_CTRL_LEVEL0		(WSA2_START_OFFSET + 0x03C0)
+#define LPASS_CDC_WSA2_INTR_CTRL_BYPASS0	(WSA2_START_OFFSET + 0x03C8)
+#define LPASS_CDC_WSA2_INTR_CTRL_SET0		(WSA2_START_OFFSET + 0x03D0)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_CTL		(WSA2_START_OFFSET + 0x0400)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG0		(WSA2_START_OFFSET + 0x0404)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG1		(WSA2_START_OFFSET + 0x0408)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG2		(WSA2_START_OFFSET + 0x040C)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_CFG3		(WSA2_START_OFFSET + 0x0410)
+#define LPASS_CDC_WSA2_RX0_RX_VOL_CTL		(WSA2_START_OFFSET + 0x0414)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL	(WSA2_START_OFFSET + 0x0418)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG	(WSA2_START_OFFSET + 0x041C)
+#define LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL	(WSA2_START_OFFSET + 0x0420)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC0		(WSA2_START_OFFSET + 0x0424)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC1		(WSA2_START_OFFSET + 0x0428)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC2		(WSA2_START_OFFSET + 0x042C)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC3		(WSA2_START_OFFSET + 0x0430)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC5		(WSA2_START_OFFSET + 0x0438)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC6		(WSA2_START_OFFSET + 0x043C)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_SEC7		(WSA2_START_OFFSET + 0x0440)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0	(WSA2_START_OFFSET + 0x0444)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1	(WSA2_START_OFFSET + 0x0448)
+#define LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL	(WSA2_START_OFFSET + 0x044C)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_CTL		(WSA2_START_OFFSET + 0x0480)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG0		(WSA2_START_OFFSET + 0x0484)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG1		(WSA2_START_OFFSET + 0x0488)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG2		(WSA2_START_OFFSET + 0x048C)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_CFG3		(WSA2_START_OFFSET + 0x0490)
+#define LPASS_CDC_WSA2_RX1_RX_VOL_CTL		(WSA2_START_OFFSET + 0x0494)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL	(WSA2_START_OFFSET + 0x0498)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG	(WSA2_START_OFFSET + 0x049C)
+#define LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL	(WSA2_START_OFFSET + 0x04A0)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC0		(WSA2_START_OFFSET + 0x04A4)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC1		(WSA2_START_OFFSET + 0x04A8)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC2		(WSA2_START_OFFSET + 0x04AC)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC3		(WSA2_START_OFFSET + 0x04B0)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC5		(WSA2_START_OFFSET + 0x04B8)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC6		(WSA2_START_OFFSET + 0x04BC)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_SEC7		(WSA2_START_OFFSET + 0x04C0)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0	(WSA2_START_OFFSET + 0x04C4)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1	(WSA2_START_OFFSET + 0x04C8)
+#define LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL	(WSA2_START_OFFSET + 0x04CC)
+#define LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL	(WSA2_START_OFFSET + 0x0500)
+#define LPASS_CDC_WSA2_BOOST0_BOOST_CTL		(WSA2_START_OFFSET + 0x0504)
+#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG1	(WSA2_START_OFFSET + 0x0508)
+#define LPASS_CDC_WSA2_BOOST0_BOOST_CFG2	(WSA2_START_OFFSET + 0x050C)
+#define LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL	(WSA2_START_OFFSET + 0x0540)
+#define LPASS_CDC_WSA2_BOOST1_BOOST_CTL		(WSA2_START_OFFSET + 0x0544)
+#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG1	(WSA2_START_OFFSET + 0x0548)
+#define LPASS_CDC_WSA2_BOOST1_BOOST_CFG2	(WSA2_START_OFFSET + 0x054C)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL0		(WSA2_START_OFFSET + 0x0580)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL1		(WSA2_START_OFFSET + 0x0584)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL2		(WSA2_START_OFFSET + 0x0588)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL3		(WSA2_START_OFFSET + 0x058C)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL4		(WSA2_START_OFFSET + 0x0590)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL5		(WSA2_START_OFFSET + 0x0594)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL6		(WSA2_START_OFFSET + 0x0598)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL7		(WSA2_START_OFFSET + 0x059C)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL8		(WSA2_START_OFFSET + 0x05A0)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL9		(WSA2_START_OFFSET + 0x05A4)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL10		(WSA2_START_OFFSET + 0x05A8)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL11		(WSA2_START_OFFSET + 0x05AC)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL12		(WSA2_START_OFFSET + 0x05B0)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL13		(WSA2_START_OFFSET + 0x05B4)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL14		(WSA2_START_OFFSET + 0x05B8)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL15		(WSA2_START_OFFSET + 0x05BC)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL16		(WSA2_START_OFFSET + 0x05C0)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL17		(WSA2_START_OFFSET + 0x05C4)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL18		(WSA2_START_OFFSET + 0x05C8)
+#define LPASS_CDC_WSA2_COMPANDER0_CTL19		(WSA2_START_OFFSET + 0x05CC)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL0		(WSA2_START_OFFSET + 0x05E0)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL1		(WSA2_START_OFFSET + 0x05E4)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL2		(WSA2_START_OFFSET + 0x05E8)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL3		(WSA2_START_OFFSET + 0x05EC)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL4		(WSA2_START_OFFSET + 0x05F0)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL5		(WSA2_START_OFFSET + 0x05F4)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL6		(WSA2_START_OFFSET + 0x05F8)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL7		(WSA2_START_OFFSET + 0x05FC)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL8		(WSA2_START_OFFSET + 0x0600)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL9		(WSA2_START_OFFSET + 0x0604)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL10		(WSA2_START_OFFSET + 0x0608)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL11		(WSA2_START_OFFSET + 0x060C)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL12		(WSA2_START_OFFSET + 0x0610)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL13		(WSA2_START_OFFSET + 0x0614)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL14		(WSA2_START_OFFSET + 0x0618)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL15		(WSA2_START_OFFSET + 0x061C)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL16		(WSA2_START_OFFSET + 0x0620)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL17		(WSA2_START_OFFSET + 0x0624)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL18		(WSA2_START_OFFSET + 0x0628)
+#define LPASS_CDC_WSA2_COMPANDER1_CTL19		(WSA2_START_OFFSET + 0x062C)
+#define LPASS_CDC_WSA2_SOFTCLIP0_CRC		(WSA2_START_OFFSET + 0x0640)
+#define LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL	(WSA2_START_OFFSET + 0x0644)
+#define LPASS_CDC_WSA2_SOFTCLIP1_CRC		(WSA2_START_OFFSET + 0x0660)
+#define LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL	(WSA2_START_OFFSET + 0x0664)
+#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL \
+						(WSA2_START_OFFSET + 0x0680)
+#define LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0	(WSA2_START_OFFSET + 0x0684)
+#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL \
+						(WSA2_START_OFFSET + 0x06C0)
+#define LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0	(WSA2_START_OFFSET + 0x06C4)
+#define LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL	(WSA2_START_OFFSET + 0x0780)
+#define LPASS_CDC_WSA2_IDLE_DETECT_CFG0		(WSA2_START_OFFSET + 0x0784)
+#define LPASS_CDC_WSA2_IDLE_DETECT_CFG1		(WSA2_START_OFFSET + 0x0788)
+#define LPASS_CDC_WSA2_IDLE_DETECT_CFG2		(WSA2_START_OFFSET + 0x078C)
+#define LPASS_CDC_WSA2_IDLE_DETECT_CFG3		(WSA2_START_OFFSET + 0x0790)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1	(WSA2_START_OFFSET + 0x0900)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2	(WSA2_START_OFFSET + 0x0904)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3	(WSA2_START_OFFSET + 0x0908)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1	(WSA2_START_OFFSET + 0x090C)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2	(WSA2_START_OFFSET + 0x0910)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3	(WSA2_START_OFFSET + 0x0914)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4	(WSA2_START_OFFSET + 0x0918)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5	(WSA2_START_OFFSET + 0x091C)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6	(WSA2_START_OFFSET + 0x0920)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7	(WSA2_START_OFFSET + 0x0924)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8	(WSA2_START_OFFSET + 0x0928)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1 \
+						(WSA2_START_OFFSET + 0x092C)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2 \
+						(WSA2_START_OFFSET + 0x0930)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3 \
+						(WSA2_START_OFFSET + 0x0934)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4 \
+						(WSA2_START_OFFSET + 0x0938)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1	(WSA2_START_OFFSET + 0x093C)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2	(WSA2_START_OFFSET + 0x0940)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3	(WSA2_START_OFFSET + 0x0944)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4	(WSA2_START_OFFSET + 0x0948)
+#define LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5	(WSA2_START_OFFSET + 0x094C)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL	(WSA2_START_OFFSET + 0x0980)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG	(WSA2_START_OFFSET + 0x0984)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1	(WSA2_START_OFFSET + 0x0988)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2	(WSA2_START_OFFSET + 0x098C)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3	(WSA2_START_OFFSET + 0x0990)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1	(WSA2_START_OFFSET + 0x0994)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2	(WSA2_START_OFFSET + 0x0998)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3	(WSA2_START_OFFSET + 0x099C)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1	(WSA2_START_OFFSET + 0x09A0)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC2	(WSA2_START_OFFSET + 0x09A4)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1	(WSA2_START_OFFSET + 0x09A8)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2	(WSA2_START_OFFSET + 0x09AC)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3	(WSA2_START_OFFSET + 0x09B0)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4	(WSA2_START_OFFSET + 0x09B4)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1	(WSA2_START_OFFSET + 0x09B8)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2	(WSA2_START_OFFSET + 0x09BC)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3	(WSA2_START_OFFSET + 0x09C0)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4	(WSA2_START_OFFSET + 0x09C4)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5	(WSA2_START_OFFSET + 0x09C8)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1	(WSA2_START_OFFSET + 0x09CC)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON \
+						(WSA2_START_OFFSET + 0x09D0)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL \
+						(WSA2_START_OFFSET + 0x09D4)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN	(WSA2_START_OFFSET + 0x09D8)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1 \
+						(WSA2_START_OFFSET + 0x09DC)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2 \
+						(WSA2_START_OFFSET + 0x09E0)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3 \
+						(WSA2_START_OFFSET + 0x09E4)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4 \
+						(WSA2_START_OFFSET + 0x09E8)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5 \
+						(WSA2_START_OFFSET + 0x09EC)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6 \
+						(WSA2_START_OFFSET + 0x09F0)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7 \
+						(WSA2_START_OFFSET + 0x09F4)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8 \
+						(WSA2_START_OFFSET + 0x09F8)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9 \
+						(WSA2_START_OFFSET + 0x09FC)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1	(WSA2_START_OFFSET + 0x0A00)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2	(WSA2_START_OFFSET + 0x0A04)
+#define LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3	(WSA2_START_OFFSET + 0x0A08)
+#define WSA2_MAX_OFFSET				(WSA2_START_OFFSET + 0x0A08)
 
-#define LPASS_CDC_VA_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 = 1EB */
+#define LPASS_CDC_WSA2_MACRO_MAX 0x283 /* 0xA08/4 = 0x282 + 1 registers */
 
-#define LPASS_CDC_MAX_REGISTER VA_MAX_OFFSET
+#define LPASS_CDC_MAX_REGISTER WSA2_MAX_OFFSET
 
 #define LPASS_CDC_REG(reg)  (((reg) & 0x0FFF)/4)
 

asoc/codecs/lpass-cdc/lpass-cdc-regmap.c

@@ -13,19 +13,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
 	{ LPASS_CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
 	{ LPASS_CDC_TX_TOP_CSR_ANC_CFG, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
+	{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x60},
 	{ LPASS_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
 	{ LPASS_CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
 	{ LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
 	{ LPASS_CDC_TX_TOP_CSR_I2S_CLK, 0x00},
 	{ LPASS_CDC_TX_TOP_CSR_I2S_RESET, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
-	{ LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
+	{ LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL, 0x0E},
+	{ LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL, 0x0E},
+	{ LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL, 0x0E},
+	{ LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL, 0x0E},
+	{ LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL, 0x0E},
+	{ LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL, 0x0E},
 	{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
 	{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
 	{ LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
@@ -150,6 +149,7 @@ static const struct reg_default lpass_cdc_defaults[] = {
 
 	/* RX Macro */
 	{ LPASS_CDC_RX_TOP_TOP_CFG0, 0x00},
+	{ LPASS_CDC_RX_TOP_TOP_CFG1, 0x00},
 	{ LPASS_CDC_RX_TOP_SWR_CTRL, 0x00},
 	{ LPASS_CDC_RX_TOP_DEBUG, 0x00},
 	{ LPASS_CDC_RX_TOP_DEBUG_BUS, 0x00},
@@ -169,11 +169,11 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11},
 	{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20},
 	{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00},
-	{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00},
+	{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x08},
 	{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11},
 	{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20},
 	{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00},
-	{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00},
+	{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x08},
 	{ LPASS_CDC_RX_TOP_RX_I2S_CTL, 0x0C},
 	{ LPASS_CDC_RX_TOP_TX_I2S2_CTL, 0x0C},
 	{ LPASS_CDC_RX_TOP_I2S_CLK, 0x0C},
@@ -250,13 +250,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_BCL_VBAT_ATTN1, 0x04},
 	{ LPASS_CDC_RX_BCL_VBAT_ATTN2, 0x08},
 	{ LPASS_CDC_RX_BCL_VBAT_ATTN3, 0x0C},
-	{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0},
-	{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00},
-	{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00},
-	{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00},
-	{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00},
-	{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00},
-	{ LPASS_CDC_RX_BCL_VBAT_DECODE_ST, 0x00},
 	{ LPASS_CDC_RX_INTR_CTRL_CFG, 0x00},
 	{ LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00},
 	{ LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF},
@@ -272,7 +265,7 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_RX0_RX_PATH_CFG0, 0x00},
 	{ LPASS_CDC_RX_RX0_RX_PATH_CFG1, 0x64},
 	{ LPASS_CDC_RX_RX0_RX_PATH_CFG2, 0x8F},
-	{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x03},
 	{ LPASS_CDC_RX_RX0_RX_VOL_CTL, 0x00},
 	{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04},
 	{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E},
@@ -291,11 +284,22 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55},
 	{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55},
 	{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55},
+	{ LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_CFG, 0x64},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6, 0x00},
+	{ LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7, 0x00},
 	{ LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x04},
 	{ LPASS_CDC_RX_RX1_RX_PATH_CFG0, 0x00},
 	{ LPASS_CDC_RX_RX1_RX_PATH_CFG1, 0x64},
 	{ LPASS_CDC_RX_RX1_RX_PATH_CFG2, 0x8F},
-	{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x03},
 	{ LPASS_CDC_RX_RX1_RX_VOL_CTL, 0x00},
 	{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04},
 	{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E},
@@ -314,11 +318,22 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55},
 	{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55},
 	{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55},
+	{ LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_CFG, 0x64},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6, 0x00},
+	{ LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7, 0x00},
 	{ LPASS_CDC_RX_RX2_RX_PATH_CTL, 0x04},
 	{ LPASS_CDC_RX_RX2_RX_PATH_CFG0, 0x00},
 	{ LPASS_CDC_RX_RX2_RX_PATH_CFG1, 0x64},
 	{ LPASS_CDC_RX_RX2_RX_PATH_CFG2, 0x8F},
-	{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x00},
+	{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x03},
 	{ LPASS_CDC_RX_RX2_RX_VOL_CTL, 0x00},
 	{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04},
 	{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E},
@@ -334,6 +349,61 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08},
 	{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00},
 	{ LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1, 0x85},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2, 0xDC},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3, 0x85},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4, 0xDC},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5, 0x85},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6, 0xDC},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7, 0x32},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4, 0x00},
+	{ LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG, 0x10},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2, 0x01},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3, 0x40},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2, 0x18},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3, 0x18},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4, 0x03},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN, 0x0C},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
+	{ LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
 	{ LPASS_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00},
 	{ LPASS_CDC_RX_IDLE_DETECT_CFG0, 0x07},
 	{ LPASS_CDC_RX_IDLE_DETECT_CFG1, 0x3C},
@@ -347,6 +417,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_COMPANDER0_CTL5, 0x00},
 	{ LPASS_CDC_RX_COMPANDER0_CTL6, 0x01},
 	{ LPASS_CDC_RX_COMPANDER0_CTL7, 0x28},
+	{ LPASS_CDC_RX_COMPANDER0_CTL8, 0x00},
+	{ LPASS_CDC_RX_COMPANDER0_CTL9, 0x00},
+	{ LPASS_CDC_RX_COMPANDER0_CTL10, 0x06},
+	{ LPASS_CDC_RX_COMPANDER0_CTL11, 0x12},
+	{ LPASS_CDC_RX_COMPANDER0_CTL12, 0x1E},
+	{ LPASS_CDC_RX_COMPANDER0_CTL13, 0x2A},
+	{ LPASS_CDC_RX_COMPANDER0_CTL14, 0x36},
+	{ LPASS_CDC_RX_COMPANDER0_CTL15, 0x3C},
+	{ LPASS_CDC_RX_COMPANDER0_CTL16, 0xC4},
+	{ LPASS_CDC_RX_COMPANDER0_CTL17, 0x00},
+	{ LPASS_CDC_RX_COMPANDER0_CTL18, 0x0C},
+	{ LPASS_CDC_RX_COMPANDER0_CTL19, 0x16},
 	{ LPASS_CDC_RX_COMPANDER1_CTL0, 0x60},
 	{ LPASS_CDC_RX_COMPANDER1_CTL1, 0xDB},
 	{ LPASS_CDC_RX_COMPANDER1_CTL2, 0xFF},
@@ -355,6 +437,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_RX_COMPANDER1_CTL5, 0x00},
 	{ LPASS_CDC_RX_COMPANDER1_CTL6, 0x01},
 	{ LPASS_CDC_RX_COMPANDER1_CTL7, 0x28},
+	{ LPASS_CDC_RX_COMPANDER1_CTL8, 0x00},
+	{ LPASS_CDC_RX_COMPANDER1_CTL9, 0x00},
+	{ LPASS_CDC_RX_COMPANDER1_CTL10, 0x06},
+	{ LPASS_CDC_RX_COMPANDER1_CTL11, 0x12},
+	{ LPASS_CDC_RX_COMPANDER1_CTL12, 0x1E},
+	{ LPASS_CDC_RX_COMPANDER1_CTL13, 0x2A},
+	{ LPASS_CDC_RX_COMPANDER1_CTL14, 0x36},
+	{ LPASS_CDC_RX_COMPANDER1_CTL15, 0x3C},
+	{ LPASS_CDC_RX_COMPANDER1_CTL16, 0xC4},
+	{ LPASS_CDC_RX_COMPANDER1_CTL17, 0x00},
+	{ LPASS_CDC_RX_COMPANDER1_CTL18, 0x0C},
+	{ LPASS_CDC_RX_COMPANDER1_CTL19, 0x16},
 	{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00},
 	{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00},
 	{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00},
@@ -450,6 +544,19 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
 	{ LPASS_CDC_WSA_TOP_I2S_CLK, 0x02},
 	{ LPASS_CDC_WSA_TOP_I2S_RESET, 0x00},
+	{ LPASS_CDC_WSA_TOP_FS_UNGATE, 0xFF},
+	{ LPASS_CDC_WSA_TOP_GRP_SEL, 0x08},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB, 0x00},
+	{ LPASS_CDC_WSA_TOP_FS_UNGATE2, 0x03},
 	{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
 	{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
 	{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
@@ -492,13 +599,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1, 0x04},
 	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2, 0x08},
 	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C},
-	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0xE0},
-	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2, 0x00},
-	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x00},
-	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0x00},
-	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x00},
-	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0x00},
-	{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST, 0x00},
 	{ LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
 	{ LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
 	{ LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
@@ -571,6 +671,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA_COMPANDER0_CTL5, 0x00},
 	{ LPASS_CDC_WSA_COMPANDER0_CTL6, 0x01},
 	{ LPASS_CDC_WSA_COMPANDER0_CTL7, 0x28},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL8, 0x00},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL9, 0x00},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL10, 0x06},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL11, 0x12},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL12, 0x1E},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL13, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL14, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL15, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL16, 0x00},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL17, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL18, 0x2A},
+	{ LPASS_CDC_WSA_COMPANDER0_CTL19, 0x16},
 	{ LPASS_CDC_WSA_COMPANDER1_CTL0, 0x60},
 	{ LPASS_CDC_WSA_COMPANDER1_CTL1, 0xDB},
 	{ LPASS_CDC_WSA_COMPANDER1_CTL2, 0xFF},
@@ -579,6 +691,18 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA_COMPANDER1_CTL5, 0x00},
 	{ LPASS_CDC_WSA_COMPANDER1_CTL6, 0x01},
 	{ LPASS_CDC_WSA_COMPANDER1_CTL7, 0x28},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL8, 0x00},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL9, 0x00},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL10, 0x06},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL11, 0x12},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL12, 0x1E},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL13, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL14, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL15, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL16, 0x00},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL17, 0x24},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL18, 0x2A},
+	{ LPASS_CDC_WSA_COMPANDER1_CTL19, 0x16},
 	{ LPASS_CDC_WSA_SOFTCLIP0_CRC, 0x00},
 	{ LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
 	{ LPASS_CDC_WSA_SOFTCLIP1_CRC, 0x00},
@@ -587,24 +711,66 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
 	{ LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
 	{ LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
-	{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
+	{ LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA_IDLE_DETECT_CFG0, 0x07},
+	{ LPASS_CDC_WSA_IDLE_DETECT_CFG1, 0x3C},
+	{ LPASS_CDC_WSA_IDLE_DETECT_CFG2, 0x00},
+	{ LPASS_CDC_WSA_IDLE_DETECT_CFG3, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1, 0x85},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2, 0xDC},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3, 0x85},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4, 0xDC},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5, 0x85},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6, 0xDC},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7, 0x32},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4, 0x00},
+	{ LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG, 0x10},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2, 0x01},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3, 0x40},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2, 0x18},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3, 0x18},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4, 0x03},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN, 0x0C},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
+	{ LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
 
 	/* VA macro */
 	{ LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
@@ -639,14 +805,6 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
 	{ LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
 	{ LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0, 0x00},
-	{ LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1, 0x00},
 	{ LPASS_CDC_VA_TX0_TX_PATH_CTL, 0x04},
 	{ LPASS_CDC_VA_TX0_TX_PATH_CFG0, 0x10},
 	{ LPASS_CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
@@ -692,50 +850,249 @@ static const struct reg_default lpass_cdc_defaults[] = {
 	{ LPASS_CDC_VA_TX3_TX_PATH_SEC4, 0x20},
 	{ LPASS_CDC_VA_TX3_TX_PATH_SEC5, 0x00},
 	{ LPASS_CDC_VA_TX3_TX_PATH_SEC6, 0x00},
-	{ LPASS_CDC_VA_TX4_TX_PATH_CTL, 0x04},
-	{ LPASS_CDC_VA_TX4_TX_PATH_CFG0, 0x10},
-	{ LPASS_CDC_VA_TX4_TX_PATH_CFG1, 0x0B},
-	{ LPASS_CDC_VA_TX4_TX_VOL_CTL, 0x00},
-	{ LPASS_CDC_VA_TX4_TX_PATH_SEC0, 0x00},
-	{ LPASS_CDC_VA_TX4_TX_PATH_SEC1, 0x00},
-	{ LPASS_CDC_VA_TX4_TX_PATH_SEC2, 0x01},
-	{ LPASS_CDC_VA_TX4_TX_PATH_SEC3, 0x3C},
-	{ LPASS_CDC_VA_TX4_TX_PATH_SEC4, 0x20},
-	{ LPASS_CDC_VA_TX4_TX_PATH_SEC5, 0x00},
-	{ LPASS_CDC_VA_TX4_TX_PATH_SEC6, 0x00},
-	{ LPASS_CDC_VA_TX5_TX_PATH_CTL, 0x04},
-	{ LPASS_CDC_VA_TX5_TX_PATH_CFG0, 0x10},
-	{ LPASS_CDC_VA_TX5_TX_PATH_CFG1, 0x0B},
-	{ LPASS_CDC_VA_TX5_TX_VOL_CTL, 0x00},
-	{ LPASS_CDC_VA_TX5_TX_PATH_SEC0, 0x00},
-	{ LPASS_CDC_VA_TX5_TX_PATH_SEC1, 0x00},
-	{ LPASS_CDC_VA_TX5_TX_PATH_SEC2, 0x01},
-	{ LPASS_CDC_VA_TX5_TX_PATH_SEC3, 0x3C},
-	{ LPASS_CDC_VA_TX5_TX_PATH_SEC4, 0x20},
-	{ LPASS_CDC_VA_TX5_TX_PATH_SEC5, 0x00},
-	{ LPASS_CDC_VA_TX5_TX_PATH_SEC6, 0x00},
-	{ LPASS_CDC_VA_TX6_TX_PATH_CTL, 0x04},
-	{ LPASS_CDC_VA_TX6_TX_PATH_CFG0, 0x10},
-	{ LPASS_CDC_VA_TX6_TX_PATH_CFG1, 0x0B},
-	{ LPASS_CDC_VA_TX6_TX_VOL_CTL, 0x00},
-	{ LPASS_CDC_VA_TX6_TX_PATH_SEC0, 0x00},
-	{ LPASS_CDC_VA_TX6_TX_PATH_SEC1, 0x00},
-	{ LPASS_CDC_VA_TX6_TX_PATH_SEC2, 0x01},
-	{ LPASS_CDC_VA_TX6_TX_PATH_SEC3, 0x3C},
-	{ LPASS_CDC_VA_TX6_TX_PATH_SEC4, 0x20},
-	{ LPASS_CDC_VA_TX6_TX_PATH_SEC5, 0x00},
-	{ LPASS_CDC_VA_TX6_TX_PATH_SEC6, 0x00},
-	{ LPASS_CDC_VA_TX7_TX_PATH_CTL, 0x04},
-	{ LPASS_CDC_VA_TX7_TX_PATH_CFG0, 0x10},
-	{ LPASS_CDC_VA_TX7_TX_PATH_CFG1, 0x0B},
-	{ LPASS_CDC_VA_TX7_TX_VOL_CTL, 0x00},
-	{ LPASS_CDC_VA_TX7_TX_PATH_SEC0, 0x00},
-	{ LPASS_CDC_VA_TX7_TX_PATH_SEC1, 0x00},
-	{ LPASS_CDC_VA_TX7_TX_PATH_SEC2, 0x01},
-	{ LPASS_CDC_VA_TX7_TX_PATH_SEC3, 0x3C},
-	{ LPASS_CDC_VA_TX7_TX_PATH_SEC4, 0x20},
-	{ LPASS_CDC_VA_TX7_TX_PATH_SEC5, 0x00},
-	{ LPASS_CDC_VA_TX7_TX_PATH_SEC6, 0x00},
+
+	/* WSA2 Macro */
+	{ LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
+	{ LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
+	{ LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL, 0x00},
+	{ LPASS_CDC_WSA2_TOP_TOP_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_TOP_TOP_CFG1, 0x00},
+	{ LPASS_CDC_WSA2_TOP_FREQ_MCLK, 0x00},
+	{ LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL, 0x00},
+	{ LPASS_CDC_WSA2_TOP_DEBUG_EN0, 0x00},
+	{ LPASS_CDC_WSA2_TOP_DEBUG_EN1, 0x00},
+	{ LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB, 0x88},
+	{ LPASS_CDC_WSA2_TOP_RX_I2S_CTL, 0x0C},
+	{ LPASS_CDC_WSA2_TOP_TX_I2S_CTL, 0x0C},
+	{ LPASS_CDC_WSA2_TOP_I2S_CLK, 0x02},
+	{ LPASS_CDC_WSA2_TOP_I2S_RESET, 0x00},
+	{ LPASS_CDC_WSA2_TOP_FS_UNGATE, 0xFF},
+	{ LPASS_CDC_WSA2_TOP_GRP_SEL, 0x08},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB, 0x00},
+	{ LPASS_CDC_WSA2_TOP_FS_UNGATE2, 0x03},
+	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1, 0x00},
+	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1, 0x00},
+	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG, 0x10},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3, 0x04},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1, 0xE0},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3, 0x40},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1, 0x2A},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2, 0x18},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3, 0x18},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4, 0x03},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4, 0x64},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN, 0x0C},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2, 0x77},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5, 0x4B},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1, 0x04},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2, 0x08},
+	{ LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C},
+	{ LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL, 0x02},
+	{ LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL, 0x02},
+	{ LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL, 0x02},
+	{ LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL, 0x02},
+	{ LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_CFG, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0, 0xFF},
+	{ LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0, 0xFF},
+	{ LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_LEVEL0, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_BYPASS0, 0x00},
+	{ LPASS_CDC_WSA2_INTR_CTRL_SET0, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_CTL, 0x04},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 0x64},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG2, 0x8F},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_CFG3, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_VOL_CTL, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL, 0x04},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG, 0x7E},
+	{ LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC0, 0x04},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC1, 0x08},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC2, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC3, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC5, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC6, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_SEC7, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0, 0x08},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1, 0x00},
+	{ LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG0, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG1, 0x64},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG2, 0x8F},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_CFG3, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_VOL_CTL, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL, 0x04},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG, 0x7E},
+	{ LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC0, 0x04},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC1, 0x08},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC2, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC3, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC5, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC6, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_SEC7, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0, 0x08},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1, 0x00},
+	{ LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL, 0x00},
+	{ LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_BOOST0_BOOST_CTL, 0xD0},
+	{ LPASS_CDC_WSA2_BOOST0_BOOST_CFG1, 0x89},
+	{ LPASS_CDC_WSA2_BOOST0_BOOST_CFG2, 0x04},
+	{ LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_BOOST1_BOOST_CTL, 0xD0},
+	{ LPASS_CDC_WSA2_BOOST1_BOOST_CFG1, 0x89},
+	{ LPASS_CDC_WSA2_BOOST1_BOOST_CFG2, 0x04},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL0, 0x60},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL1, 0xDB},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL2, 0xFF},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL3, 0x35},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL4, 0xFF},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL5, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL6, 0x01},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL7, 0x28},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL8, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL9, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL10, 0x06},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL11, 0x12},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL12, 0x1E},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL13, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL14, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL15, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL16, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL17, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL18, 0x2A},
+	{ LPASS_CDC_WSA2_COMPANDER0_CTL19, 0x16},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL0, 0x60},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL1, 0xDB},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL2, 0xFF},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL3, 0x35},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL4, 0xFF},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL5, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL6, 0x01},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL7, 0x28},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL8, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL9, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL10, 0x06},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL11, 0x12},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL12, 0x1E},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL13, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL14, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL15, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL16, 0x00},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL17, 0x24},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL18, 0x2A},
+	{ LPASS_CDC_WSA2_COMPANDER1_CTL19, 0x16},
+	{ LPASS_CDC_WSA2_SOFTCLIP0_CRC, 0x00},
+	{ LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
+	{ LPASS_CDC_WSA2_SOFTCLIP1_CRC, 0x00},
+	{ LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
+	{ LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
+	{ LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
+	{ LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_IDLE_DETECT_CFG0, 0x07},
+	{ LPASS_CDC_WSA2_IDLE_DETECT_CFG1, 0x3C},
+	{ LPASS_CDC_WSA2_IDLE_DETECT_CFG2, 0x00},
+	{ LPASS_CDC_WSA2_IDLE_DETECT_CFG3, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1, 0x85},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2, 0xDC},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3, 0x85},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4, 0xDC},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5, 0x85},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6, 0xDC},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7, 0x32},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4, 0x00},
+	{ LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG, 0x10},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3, 0x04},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1, 0xE0},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3, 0x40},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1, 0x2A},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2, 0x18},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3, 0x18},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4, 0x03},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4, 0x64},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN, 0x0C},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2, 0x77},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5, 0x4B},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7, 0x01},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9, 0x00},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1, 0x04},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2, 0x08},
+	{ LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3, 0x0C},
 };
 
 static bool lpass_cdc_is_readable_register(struct device *dev,
@@ -801,28 +1158,22 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
 	case LPASS_CDC_VA_TOP_CSR_DMIC1_CTL:
 	case LPASS_CDC_VA_TOP_CSR_DMIC2_CTL:
 	case LPASS_CDC_VA_TOP_CSR_DMIC3_CTL:
-	case LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
-	case LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
-	case LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
-	case LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
+	case LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL:
+	case LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL:
+	case LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL:
+	case LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL:
 	case LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL:
 	case LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL:
 	case LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL:
-	case LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST:
 	case LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0:
 	case LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0:
 	case LPASS_CDC_WSA_COMPANDER0_CTL6:
 	case LPASS_CDC_WSA_COMPANDER1_CTL6:
-	case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
-	case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
-	case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
+	case LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL:
+	case LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0:
+	case LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0:
+	case LPASS_CDC_WSA2_COMPANDER0_CTL6:
+	case LPASS_CDC_WSA2_COMPANDER1_CTL6:
 	case LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB:
 	case LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB:
 	case LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB:
@@ -834,7 +1185,6 @@ static bool lpass_cdc_is_volatile_register(struct device *dev,
 	case LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2:
 	case LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2:
 	case LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL:
-	case LPASS_CDC_RX_BCL_VBAT_DECODE_ST:
 	case LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0:
 	case LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0:
 	case LPASS_CDC_RX_COMPANDER0_CTL6:

asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c

@@ -18,6 +18,7 @@
 
 #include <asoc/msm-cdc-pinctrl.h>
 #include "lpass-cdc.h"
+#include "lpass-cdc-comp.h"
 #include "lpass-cdc-registers.h"
 #include "lpass-cdc-clk-rsc.h"
 
@@ -102,19 +103,14 @@ static const struct wcd_imped_val imped_index[] = {
 	{13, 9},
 };
 
-struct comp_coeff_val {
-	u8 lsb;
-	u8 msb;
-};
-
 enum {
 	HPH_ULP,
 	HPH_LOHIFI,
 	HPH_MODE_MAX,
 };
 
-static const struct comp_coeff_val
-			comp_coeff_table [HPH_MODE_MAX][COMP_MAX_COEFF] = {
+static struct comp_coeff_val
+		comp_coeff_table [HPH_MODE_MAX][COMP_MAX_COEFF] = {
 	{
 		{0x40, 0x00},
 		{0x4C, 0x00},
@@ -171,6 +167,20 @@ static const struct comp_coeff_val
 	},
 };
 
+enum {
+	RX_MODE_ULP,
+	RX_MODE_LOHIFI,
+	RX_MODE_EAR,
+	RX_MODE_MAX
+};
+
+static u8 comp_setting_table[RX_MODE_MAX][COMP_MAX_SETTING] =
+{
+	{0x00, 0x10, 0x06, 0x12, 0x21, 0x30, 0x3F, 0x48, 0xC4, 0xC, 0xC, 0xB0}, /* ULP */
+	{0x00, 0x00, 0x06, 0x12, 0x1E, 0x2A, 0x36, 0x3C, 0xC4, 0x0, 0xC, 0xB0}, /* LOHIFI */
+	{0x00, 0x10, 0x06, 0x12, 0x1E, 0x2A, 0x30, 0x30, 0xDC, 0xC, 0xC, 0xB0}, /* EAR -36 max_attn */
+};
+
 struct lpass_cdc_rx_macro_reg_mask_val {
 	u16 reg;
 	u8 mask;
@@ -356,7 +366,7 @@ static int lpass_cdc_rx_macro_hw_params(struct snd_pcm_substream *substream,
 static int lpass_cdc_rx_macro_get_channel_map(struct snd_soc_dai *dai,
 				unsigned int *tx_num, unsigned int *tx_slot,
 				unsigned int *rx_num, unsigned int *rx_slot);
-static int lpass_cdc_rx_macro_digital_mute(struct snd_soc_dai *dai, int mute);
+static int lpass_cdc_rx_macro_mute_stream(struct snd_soc_dai *dai, int mute, int stream);
 static int lpass_cdc_rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
 				     struct snd_ctl_elem_value *ucontrol);
 static int lpass_cdc_rx_macro_mux_get(struct snd_kcontrol *kcontrol,
@@ -653,7 +663,7 @@ static const struct snd_kcontrol_new rx_mix_tx0_mux =
 static struct snd_soc_dai_ops lpass_cdc_rx_macro_dai_ops = {
 	.hw_params = lpass_cdc_rx_macro_hw_params,
 	.get_channel_map = lpass_cdc_rx_macro_get_channel_map,
-	.digital_mute = lpass_cdc_rx_macro_digital_mute,
+	.mute_stream = lpass_cdc_rx_macro_mute_stream,
 };
 
 static struct snd_soc_dai_driver lpass_cdc_rx_macro_dai[] = {
@@ -952,9 +962,9 @@ static int lpass_cdc_rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai
 		for (j = 0; j < INTERP_MAX; j++) {
 			int_mux_cfg1 = int_mux_cfg0 + 4;
 
-			int_mux_cfg0_val = snd_soc_component_read32(
+			int_mux_cfg0_val = snd_soc_component_read(
 						component, int_mux_cfg0);
-			int_mux_cfg1_val = snd_soc_component_read32(
+			int_mux_cfg1_val = snd_soc_component_read(
 						component, int_mux_cfg1);
 			inp0_sel = int_mux_cfg0_val & 0x0F;
 			inp1_sel = (int_mux_cfg0_val >> 4) & 0x0F;
@@ -1007,7 +1017,7 @@ static int lpass_cdc_rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
 
 		int_mux_cfg1 = LPASS_CDC_RX_INP_MUX_RX_INT0_CFG1;
 		for (j = 0; j < INTERP_MAX; j++) {
-			int_mux_cfg1_val = snd_soc_component_read32(
+			int_mux_cfg1_val = snd_soc_component_read(
 						component, int_mux_cfg1) &
 						0x0F;
 			if (int_mux_cfg1_val == int_2_inp +
@@ -1175,7 +1185,7 @@ static int lpass_cdc_rx_macro_get_channel_map(struct snd_soc_dai *dai,
 			__func__, dai->id, *rx_slot, *rx_num);
 		break;
 	case RX_MACRO_AIF_ECHO:
-		val = snd_soc_component_read32(component,
+		val = snd_soc_component_read(component,
 			LPASS_CDC_RX_INP_MUX_RX_MIX_CFG4);
 		if (val & LPASS_CDC_RX_MACRO_EC_MIX_TX0_MASK) {
 			mask |= 0x1;
@@ -1185,7 +1195,7 @@ static int lpass_cdc_rx_macro_get_channel_map(struct snd_soc_dai *dai,
 			mask |= 0x2;
 			cnt++;
 		}
-		val = snd_soc_component_read32(component,
+		val = snd_soc_component_read(component,
 			LPASS_CDC_RX_INP_MUX_RX_MIX_CFG5);
 		if (val & LPASS_CDC_RX_MACRO_EC_MIX_TX2_MASK) {
 			mask |= 0x4;
@@ -1201,7 +1211,7 @@ static int lpass_cdc_rx_macro_get_channel_map(struct snd_soc_dai *dai,
 	return 0;
 }
 
-static int lpass_cdc_rx_macro_digital_mute(struct snd_soc_dai *dai, int mute)
+static int lpass_cdc_rx_macro_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 {
 	struct snd_soc_component *component = dai->component;
 	struct device *rx_dev = NULL;
@@ -1232,11 +1242,11 @@ static int lpass_cdc_rx_macro_digital_mute(struct snd_soc_dai *dai, int mute)
 			dsm_reg = LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL;
 		int_mux_cfg0 = LPASS_CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
 		int_mux_cfg1 = int_mux_cfg0 + 4;
-		int_mux_cfg0_val = snd_soc_component_read32(component,
+		int_mux_cfg0_val = snd_soc_component_read(component,
 							int_mux_cfg0);
-		int_mux_cfg1_val = snd_soc_component_read32(component,
+		int_mux_cfg1_val = snd_soc_component_read(component,
 							int_mux_cfg1);
-		if (snd_soc_component_read32(component, dsm_reg) & 0x01) {
+		if (snd_soc_component_read(component, dsm_reg) & 0x01) {
 			if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0))
 				snd_soc_component_update_bits(component,
 							reg, 0x20, 0x20);
@@ -1414,7 +1424,7 @@ static int lpass_cdc_rx_macro_event_handler(struct snd_soc_component *component,
 		reg = LPASS_CDC_RX_COMPANDER0_CTL0 +
 				(rx_idx * LPASS_CDC_RX_MACRO_COMP_OFFSET);
 		snd_soc_component_write(component, reg,
-				snd_soc_component_read32(component, reg));
+				snd_soc_component_read(component, reg));
 		break;
 	case LPASS_CDC_MACRO_EVT_IMPED_TRUE:
 		lpass_cdc_rx_macro_wcd_clsh_imped_config(component, data, true);
@@ -1469,9 +1479,9 @@ static int lpass_cdc_rx_macro_event_handler(struct snd_soc_component *component,
 		lpass_cdc_rsc_clk_reset(rx_dev, RX_CORE_CLK);
 		break;
 	case LPASS_CDC_MACRO_EVT_RX_PA_GAIN_UPDATE:
-		rx_priv->rx0_gain_val = snd_soc_component_read32(component,
+		rx_priv->rx0_gain_val = snd_soc_component_read(component,
 					LPASS_CDC_RX_RX0_RX_VOL_CTL);
-		rx_priv->rx1_gain_val = snd_soc_component_read32(component,
+		rx_priv->rx1_gain_val = snd_soc_component_read(component,
 					LPASS_CDC_RX_RX1_RX_VOL_CTL);
 		if (data) {
 			/* Reduce gain by half only if its greater than -6DB */
@@ -1564,7 +1574,7 @@ static int lpass_cdc_rx_macro_set_idle_detect_thr(struct snd_soc_component *comp
 	if (path_type == INTERP_MIX_PATH) {
 		mux_reg = LPASS_CDC_RX_INP_MUX_RX_INT0_CFG1 +
 						2 * interp;
-		mux_reg_val = snd_soc_component_read32(component, mux_reg) &
+		mux_reg_val = snd_soc_component_read(component, mux_reg) &
 				0x0f;
 
 		if ((mux_reg_val >= INTn_2_INP_SEL_RX0) &&
@@ -1577,7 +1587,7 @@ static int lpass_cdc_rx_macro_set_idle_detect_thr(struct snd_soc_component *comp
 	if (path_type == INTERP_MAIN_PATH) {
 		mux_reg = LPASS_CDC_RX_INP_MUX_RX_INT1_CFG0 +
 			  2 * (interp - 1);
-		mux_reg_val = snd_soc_component_read32(component, mux_reg) &
+		mux_reg_val = snd_soc_component_read(component, mux_reg) &
 				0x0f;
 		i = LPASS_CDC_RX_MACRO_INTERP_MUX_NUM_INPUTS;
 
@@ -1589,7 +1599,7 @@ static int lpass_cdc_rx_macro_set_idle_detect_thr(struct snd_soc_component *comp
 				num_ports++;
 			}
 			mux_reg_val =
-				(snd_soc_component_read32(component, mux_reg) &
+				(snd_soc_component_read(component, mux_reg) &
 					0xf0) >> 4;
 			mux_reg += 1;
 			i--;
@@ -1675,7 +1685,7 @@ static int lpass_cdc_rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
 		break;
 	case SND_SOC_DAPM_POST_PMU:
 		snd_soc_component_write(component, gain_reg,
-			snd_soc_component_read32(component, gain_reg));
+			snd_soc_component_read(component, gain_reg));
 		break;
 	case SND_SOC_DAPM_POST_PMD:
 		/* Clk Disable */
@@ -1699,8 +1709,8 @@ static bool lpass_cdc_rx_macro_adie_lb(struct snd_soc_component *component,
 
 	int_mux_cfg0 = LPASS_CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
 	int_mux_cfg1 = int_mux_cfg0 + 4;
-	int_mux_cfg0_val = snd_soc_component_read32(component, int_mux_cfg0);
-	int_mux_cfg1_val = snd_soc_component_read32(component, int_mux_cfg1);
+	int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
+	int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
 
 	int_n_inp0 = int_mux_cfg0_val & 0x0F;
 	if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
@@ -1764,7 +1774,7 @@ static int lpass_cdc_rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
 		break;
 	case SND_SOC_DAPM_POST_PMU:
 		snd_soc_component_write(component, gain_reg,
-			snd_soc_component_read32(component, gain_reg));
+			snd_soc_component_read(component, gain_reg));
 		break;
 	case SND_SOC_DAPM_POST_PMD:
 		lpass_cdc_rx_macro_enable_interp_clk(component, event, w->shift);
@@ -1774,28 +1784,17 @@ static int lpass_cdc_rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
 	return 0;
 }
 
-static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *component,
-				struct lpass_cdc_rx_macro_priv *rx_priv,
-				int interp_n, int event)
+static void lpass_cdc_rx_macro_droop_setting(struct snd_soc_component *component,
+					    int interp_n, int event)
 {
-	int comp = 0;
-	u16 comp_ctl0_reg = 0, rx_path_cfg0_reg = 0, rx_path_cfg3_reg = 0;
-	u16 rx0_path_ctl_reg = 0;
 	u8 pcm_rate = 0, val = 0;
-
-	/* AUX does not have compander */
-	if (interp_n == INTERP_AUX)
-		return 0;
-
-	comp = interp_n;
-	dev_dbg(component->dev, "%s: event %d compander %d, enabled %d\n",
-		__func__, event, comp + 1, rx_priv->comp_enabled[comp]);
+	u16 rx0_path_ctl_reg = 0, rx_path_cfg3_reg = 0;
 
 	rx_path_cfg3_reg = LPASS_CDC_RX_RX0_RX_PATH_CFG3 +
-					(comp * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET);
+					(interp_n * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET);
 	rx0_path_ctl_reg = LPASS_CDC_RX_RX0_RX_PATH_CTL +
-					(comp * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET);
-	pcm_rate = (snd_soc_component_read32(component, rx0_path_ctl_reg)
+					(interp_n * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET);
+	pcm_rate = (snd_soc_component_read(component, rx0_path_ctl_reg)
 						& 0x0F);
 	if (pcm_rate < 0x06)
 		val = 0x03;
@@ -1812,14 +1811,50 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
 	if (SND_SOC_DAPM_EVENT_OFF(event))
 		snd_soc_component_update_bits(component, rx_path_cfg3_reg,
 					0x03, 0x03);
+}
+
+static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *component,
+				struct lpass_cdc_rx_macro_priv *rx_priv,
+				int interp_n, int event)
+{
+	int comp = 0;
+	u16 comp_ctl0_reg = 0, comp_ctl8_reg = 0, rx_path_cfg0_reg = 0;
+	u16 comp_coeff_lsb_reg = 0, comp_coeff_msb_reg = 0;
+	u16 mode = rx_priv->hph_pwr_mode;
+
+	comp = interp_n;
 	if (!rx_priv->comp_enabled[comp])
 		return 0;
 
+	if (rx_priv->is_ear_mode_on && interp_n == INTERP_HPHL)
+		mode = RX_MODE_EAR;
+
+	if (interp_n == INTERP_HPHL) {
+		comp_coeff_lsb_reg = LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB;
+		comp_coeff_msb_reg = LPASS_CDC_RX_TOP_HPHL_COMP_WR_MSB;
+	} else if (interp_n == INTERP_HPHR) {
+		comp_coeff_lsb_reg = LPASS_CDC_RX_TOP_HPHR_COMP_WR_LSB;
+		comp_coeff_msb_reg = LPASS_CDC_RX_TOP_HPHR_COMP_WR_MSB;
+	} else {
+		/* compander coefficients are loaded only for hph path */
+		return 0;
+	}
 	comp_ctl0_reg = LPASS_CDC_RX_COMPANDER0_CTL0 +
 					(comp * LPASS_CDC_RX_MACRO_COMP_OFFSET);
+	comp_ctl8_reg = LPASS_CDC_RX_COMPANDER0_CTL8 +
+					(comp * LPASS_CDC_RX_MACRO_COMP_OFFSET);
 	rx_path_cfg0_reg = LPASS_CDC_RX_RX0_RX_PATH_CFG0 +
 					(comp * LPASS_CDC_RX_MACRO_RX_PATH_OFFSET);
 	if (SND_SOC_DAPM_EVENT_ON(event)) {
+		lpass_cdc_load_compander_coeff(component,
+				comp_coeff_lsb_reg, comp_coeff_msb_reg,
+				comp_coeff_table[rx_priv->hph_pwr_mode],
+				COMP_MAX_COEFF);
+
+		lpass_cdc_update_compander_setting(component,
+					comp_ctl8_reg,
+					comp_setting_table[mode]);
+
 		/* Enable Compander Clock */
 		snd_soc_component_update_bits(component, comp_ctl0_reg,
 					0x01, 0x01);
@@ -1845,47 +1880,6 @@ static int lpass_cdc_rx_macro_config_compander(struct snd_soc_component *compone
 	return 0;
 }
 
-static int lpass_cdc_rx_macro_load_compander_coeff(struct snd_soc_component *component,
-					 struct lpass_cdc_rx_macro_priv *rx_priv,
-					 int interp_n, int event)
-{
-	int comp = 0;
-	u16 comp_coeff_lsb_reg = 0, comp_coeff_msb_reg = 0;
-	int i = 0;
-	int hph_pwr_mode = HPH_LOHIFI;
-
-	if (!rx_priv->comp_enabled[comp])
-		return 0;
-
-	if (interp_n == INTERP_HPHL) {
-		comp_coeff_lsb_reg = LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB;
-		comp_coeff_msb_reg = LPASS_CDC_RX_TOP_HPHL_COMP_WR_MSB;
-	} else if (interp_n == INTERP_HPHR) {
-		comp_coeff_lsb_reg = LPASS_CDC_RX_TOP_HPHR_COMP_WR_LSB;
-		comp_coeff_msb_reg = LPASS_CDC_RX_TOP_HPHR_COMP_WR_MSB;
-	} else {
-		/* compander coefficients are loaded only for hph path */
-		return 0;
-	}
-
-	comp = interp_n;
-	hph_pwr_mode = rx_priv->hph_pwr_mode;
-	dev_dbg(component->dev, "%s: event %d compander %d, enabled %d\n",
-		__func__, event, comp + 1, rx_priv->comp_enabled[comp]);
-
-	if (SND_SOC_DAPM_EVENT_ON(event)) {
-		/* Load Compander Coeff */
-		for (i = 0; i < COMP_MAX_COEFF; i++) {
-			snd_soc_component_write(component, comp_coeff_lsb_reg,
-					comp_coeff_table[hph_pwr_mode][i].lsb);
-			snd_soc_component_write(component, comp_coeff_msb_reg,
-					comp_coeff_table[hph_pwr_mode][i].msb);
-		}
-	}
-
-	return 0;
-}
-
 static void lpass_cdc_rx_macro_enable_softclip_clk(struct snd_soc_component *component,
 					 struct lpass_cdc_rx_macro_priv *rx_priv,
 					 bool enable)
@@ -2325,7 +2319,7 @@ static int lpass_cdc_rx_macro_vbat_bcl_gsm_mode_func_get(struct snd_kcontrol *kc
 			snd_soc_kcontrol_component(kcontrol);
 
 	ucontrol->value.integer.value[0] =
-		((snd_soc_component_read32(
+		((snd_soc_component_read(
 			component, LPASS_CDC_RX_BCL_VBAT_CFG) & 0x04) ?
 		  1 : 0);
 
@@ -2670,8 +2664,6 @@ static int lpass_cdc_rx_macro_enable_interp_clk(struct snd_soc_component *compon
 					0x01, 0x01);
 			snd_soc_component_update_bits(component, rx_cfg2_reg,
 					0x03, 0x03);
-			lpass_cdc_rx_macro_load_compander_coeff(component, rx_priv,
-						      interp_idx, event);
 			lpass_cdc_rx_macro_idle_detect_control(component, rx_priv,
 					interp_idx, event);
 			if (rx_priv->hph_hd2_mode)
@@ -2679,6 +2671,8 @@ static int lpass_cdc_rx_macro_enable_interp_clk(struct snd_soc_component *compon
 					component, interp_idx, event);
 			lpass_cdc_rx_macro_hphdelay_lutbypass(component, rx_priv,
 						    interp_idx, event);
+			lpass_cdc_rx_macro_droop_setting(component,
+						interp_idx, event);
 			lpass_cdc_rx_macro_config_compander(component, rx_priv,
 						interp_idx, event);
 			if (interp_idx == INTERP_AUX) {
@@ -2818,7 +2812,7 @@ static int lpass_cdc_rx_macro_iir_enable_audio_mixer_get(struct snd_kcontrol *kc
 	u16 iir_reg = LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL + 0x80 * iir_idx;
 
 	ucontrol->value.integer.value[0] = (
-				snd_soc_component_read32(component, iir_reg) &
+				snd_soc_component_read(component, iir_reg) &
 				(1 << band_idx)) != 0;
 
 	dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__,
@@ -2851,7 +2845,7 @@ static int lpass_cdc_rx_macro_iir_enable_audio_mixer_put(struct snd_kcontrol *kc
 	snd_soc_component_update_bits(component, iir_reg, (1 << band_idx),
 			    (value << band_idx));
 
-	iir_band_en_status = ((snd_soc_component_read32(component, iir_reg) &
+	iir_band_en_status = ((snd_soc_component_read(component, iir_reg) &
 			      (1 << band_idx)) != 0);
 	dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__,
 		iir_idx, band_idx, iir_band_en_status);
@@ -2870,7 +2864,7 @@ static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
 		((band_idx * BAND_MAX + coeff_idx)
 		* sizeof(uint32_t)) & 0x7F);
 
-	value |= snd_soc_component_read32(component,
+	value |= snd_soc_component_read(component,
 		(LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx));
 
 	snd_soc_component_write(component,
@@ -2878,7 +2872,7 @@ static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
 		((band_idx * BAND_MAX + coeff_idx)
 		* sizeof(uint32_t) + 1) & 0x7F);
 
-	value |= (snd_soc_component_read32(component,
+	value |= (snd_soc_component_read(component,
 			       (LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL +
 				0x80 * iir_idx)) << 8);
 
@@ -2887,7 +2881,7 @@ static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
 		((band_idx * BAND_MAX + coeff_idx)
 		* sizeof(uint32_t) + 2) & 0x7F);
 
-	value |= (snd_soc_component_read32(component,
+	value |= (snd_soc_component_read(component,
 			       (LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL +
 				0x80 * iir_idx)) << 16);
 
@@ -2897,7 +2891,7 @@ static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
 		* sizeof(uint32_t) + 3) & 0x7F);
 
 	/* Mask bits top 2 bits since they are reserved */
-	value |= ((snd_soc_component_read32(component,
+	value |= ((snd_soc_component_read(component,
 				(LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL +
 				 16 * iir_idx)) & 0x3F) << 24);
 
@@ -3039,36 +3033,36 @@ static int lpass_cdc_rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
 		if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
 		} else {
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
 			snd_soc_component_write(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
-			snd_soc_component_read32(component,
+			snd_soc_component_read(component,
 				LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
 		}
 		break;
@@ -3227,14 +3221,14 @@ static int lpass_cdc_rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
 
 	dev_dbg(rx_dev, "%s %d %s\n", __func__, event, w->name);
 
-	val = snd_soc_component_read32(component,
+	val = snd_soc_component_read(component,
 			LPASS_CDC_RX_INP_MUX_RX_MIX_CFG4);
 	if (!(strcmp(w->name, "RX MIX TX0 MUX")))
 		ec_tx = ((val & 0xf0) >> 0x4) - 1;
 	else if (!(strcmp(w->name, "RX MIX TX1 MUX")))
 		ec_tx = (val & 0x0f) - 1;
 
-	val = snd_soc_component_read32(component,
+	val = snd_soc_component_read(component,
 			LPASS_CDC_RX_INP_MUX_RX_MIX_CFG5);
 	if (!(strcmp(w->name, "RX MIX TX2 MUX")))
 		ec_tx = (val & 0x0f) - 1;
@@ -3863,30 +3857,8 @@ static void lpass_cdc_rx_macro_init_bcl_pmic_reg(struct snd_soc_component *compo
 
 	switch (rx_priv->bcl_pmic_params.id) {
 	case 0:
-		/* Enable ID0 to listen to respective PMIC group interrupts */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x02, 0x02);
-		/* Update MC_SID0 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x0F,
-			rx_priv->bcl_pmic_params.sid);
-		/* Update MC_PPID0 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0xFF,
-			rx_priv->bcl_pmic_params.ppid);
 		break;
 	case 1:
-		/* Enable ID1 to listen to respective PMIC group interrupts */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x01, 0x01);
-		/* Update MC_SID1 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x0F,
-			rx_priv->bcl_pmic_params.sid);
-		/* Update MC_PPID1 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0xFF,
-			rx_priv->bcl_pmic_params.ppid);
 		break;
 	default:
 		dev_err(rx_dev, "%s: PMIC ID is invalid %d\n",

asoc/codecs/lpass-cdc/lpass-cdc-tables.c

@@ -14,34 +14,17 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
@@ -58,6 +41,22 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
@@ -149,98 +148,9 @@ u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC6)] = RD_WR_REG,
 };
 
-u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX] = {
-	[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC7)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC6)] = RD_WR_REG,
-};
-
 u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_RX_TOP_TOP_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_TOP_TOP_CFG1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_TOP_SWR_CTRL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG_BUS)] = RD_WR_REG,
@@ -341,13 +251,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN2)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_ST)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CFG)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT)] = WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
@@ -382,6 +285,17 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG,
@@ -405,6 +319,17 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA7)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG,
@@ -425,6 +350,61 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG,
@@ -438,6 +418,18 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL6)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL17)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL18)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL19)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG,
@@ -446,6 +438,18 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL6)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL17)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL18)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL19)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG,
@@ -530,200 +534,6 @@ u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
 };
 
 u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = {
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC6)] = RD_WR_REG,
-};
-
-u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX] = {
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
-};
-
-u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX] = {
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
-};
-
-u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
@@ -816,6 +626,19 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_TX_I2S_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_CLK)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_RESET)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FS_UNGATE)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_GRP_SEL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_LSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_WR_MSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_LUT)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_LSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP7_RD_MSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_LSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_WR_MSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_LUT)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_LSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_SPKR_COMP8_RD_MSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FS_UNGATE2)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
@@ -858,13 +681,6 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
@@ -938,6 +754,18 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL5)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL6)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL17)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL18)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL19)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL1)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL2)] = RD_WR_REG,
@@ -946,6 +774,18 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL5)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL6)] = RD_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL17)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL18)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL19)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_CRC)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP1_CRC)] = RD_WR_REG,
@@ -954,24 +794,311 @@ u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
 	[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
 	[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL0)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL1)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL)] = RD_WR_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB)] = RD_REG,
-	[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_IDLE_DETECT_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
+};
+
+u8 lpass_cdc_wsa2_reg_access[LPASS_CDC_WSA2_MACRO_MAX] = {
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TOP_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TOP_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FREQ_MCLK)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_BUS_SEL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_EN0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_EN1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_DEBUG_DSM_LB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_RX_I2S_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_TX_I2S_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_I2S_CLK)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_I2S_RESET)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FS_UNGATE)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_GRP_SEL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_LSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_WR_MSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_LUT)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_LSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP7_RD_MSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_LSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_WR_MSB)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_LUT)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_LSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_SPKR_COMP8_RD_MSB)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TOP_FS_UNGATE2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_INT1_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_MIX_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_RX_EC_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX_INP_MUX_SOFTCLIP_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_ADC_CAL3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_PK_EST3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_RF_PROC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_TAC4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_DEBUG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_UPD_MON)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_GAIN_MON_VAL)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BAN)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX1_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX2_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_TX3_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_CLR_COMMIT)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_STATUS0)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN1_CLEAR0)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_MASK0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_STATUS0)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_PIN2_CLEAR0)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_LEVEL0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_BYPASS0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_INTR_CTRL_SET0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_VOL_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_VOL_MIX_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_SEC7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_MIX_SEC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX0_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_VOL_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_VOL_MIX_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_SEC7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_MIX_SEC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_RX1_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST0_BOOST_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_BOOST1_BOOST_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL6)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL17)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL18)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER0_CTL19)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL6)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL10)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL11)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL12)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL13)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL14)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL15)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL16)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL17)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL18)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_COMPANDER1_CTL19)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP0_CRC)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP1_CRC)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_SOFTCLIP1_SOFTCLIP_CTRL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG0)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_IDLE_DETECT_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CTL3)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_CFG8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_TEST4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST1)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST2)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST3)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST4)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_CB_DECODE_CB_DECODE_ST5)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PATH_CTL)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_CFG)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_ADC_CAL3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_PK_EST3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_RF_PROC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_TAC4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_DEBUG1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_UPD_MON)] = WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_GAIN_MON_VAL)] = RD_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BAN)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN1)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN2)] = RD_WR_REG,
+	[LPASS_CDC_REG(LPASS_CDC_WSA2_VBAT_TEMP_VBAT_BCL_ATTN3)] = RD_WR_REG,
 };
 
 u8 *lpass_cdc_reg_access[MAX_MACRO] = {
@@ -979,4 +1106,5 @@ u8 *lpass_cdc_reg_access[MAX_MACRO] = {
 	[RX_MACRO] = lpass_cdc_rx_reg_access,
 	[WSA_MACRO] = lpass_cdc_wsa_reg_access,
 	[VA_MACRO] = lpass_cdc_va_reg_access,
+	[WSA2_MACRO] = lpass_cdc_wsa2_reg_access,
 };

asoc/codecs/lpass-cdc/lpass-cdc-utils.c

@@ -15,6 +15,7 @@ const u16 macro_id_base_offset[MAX_MACRO] = {
 	RX_START_OFFSET,
 	WSA_START_OFFSET,
 	VA_START_OFFSET,
+	WSA2_START_OFFSET,
 };
 
 int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg)
@@ -28,13 +29,11 @@ int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg)
 	if (reg >= WSA_START_OFFSET
 		&& reg <= WSA_MAX_OFFSET)
 		return WSA_MACRO;
-	if (!va_no_dec_flag &&
-		(reg >= VA_START_OFFSET &&
-		reg <= VA_MAX_OFFSET))
-		return VA_MACRO;
-	if (va_no_dec_flag &&
-		(reg >= VA_START_OFFSET &&
-		reg <= VA_TOP_MAX_OFFSET))
+	if (reg >= WSA2_START_OFFSET
+		&& reg <= WSA2_MAX_OFFSET)
+		return WSA2_MACRO;
+	if (reg >= VA_START_OFFSET &&
+		reg <= VA_MAX_OFFSET)
 		return VA_MACRO;
 
 	return -EINVAL;

asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c

@@ -16,6 +16,7 @@
 
 #include <asoc/msm-cdc-pinctrl.h>
 #include "lpass-cdc.h"
+#include "lpass-cdc-comp.h"
 #include "lpass-cdc-registers.h"
 #include "lpass-cdc-wsa-macro.h"
 #include "lpass-cdc-clk-rsc.h"
@@ -107,6 +108,32 @@ enum {
 	INTn_2_INP_SEL_RX3,
 };
 
+enum {
+	WSA_MODE_21DB,
+	WSA_MODE_19P5DB,
+	WSA_MODE_18DB,
+	WSA_MODE_16P5DB,
+	WSA_MODE_15DB,
+	WSA_MODE_13P5DB,
+	WSA_MODE_12DB,
+	WSA_MODE_10P5DB,
+	WSA_MODE_9DB,
+	WSA_MODE_MAX
+};
+
+static u8 comp_setting_table[WSA_MODE_MAX][COMP_MAX_SETTING] =
+{
+	{0x00, 0x10, 0x06, 0x18, 0x24, 0x2A, 0x2A, 0x2A, 0x00, 0x2A, 0x2A, 0xB0}, /* WSA_MODE_21DB */
+	{0x00, 0x10, 0x06, 0x18, 0x24, 0x2A, 0x2A, 0x2A, 0xFD, 0x2A, 0x2A, 0xB0}, /* WSA_MODE_19PDB -1.5DB*/
+	{0x00, 0x10, 0x06, 0x12, 0x1E, 0x24, 0x24, 0x24, 0xFA, 0x24, 0x2A, 0xB0}, /* WSA_MODE_18DB -3DB*/
+	{0x00, 0x10, 0x06, 0x0C, 0x18, 0x21, 0x21, 0x21, 0xFA, 0x21, 0x2A, 0xB0}, /* WSA_MODE_16P5DB -3DB*/
+	{0x00, 0x10, 0x06, 0x0C, 0x18, 0x21, 0x21, 0x21, 0xFA, 0x21, 0x2A, 0xB0}, /* WSA_MODE_15DB -3DB -->TODO: NEED UPDATE ENTRIES */
+	{0x00, 0x10, 0x06, 0x12, 0x1B, 0x1B, 0x1B, 0x1B, 0xFA, 0x1B, 0x2A, 0xB0}, /* WSA_MODE_13P5DB -3DB */
+	{0x00, 0x10, 0x06, 0x12, 0x18, 0x18, 0x18, 0x18, 0xFA, 0x18, 0x2A, 0xB0}, /* WSA_MODE_12DB -3DB */
+	{0x00, 0x10, 0x06, 0x12, 0x18, 0x18, 0x18, 0x18, 0xFA, 0x18, 0x2A, 0xB0}, /* WSA_MODE_10P5DB -3DB --> NEED Update entries */
+	{0x00, 0x10, 0x06, 0x12, 0x18, 0x18, 0x18, 0x18, 0xFA, 0x18, 0x2A, 0xB0}, /* WSA_MODE_9DB -3DB --> NEED Update entries */
+};
+
 struct interp_sample_rate {
 	int sample_rate;
 	int rate_val;
@@ -148,7 +175,7 @@ static int lpass_cdc_wsa_macro_hw_params(struct snd_pcm_substream *substream,
 static int lpass_cdc_wsa_macro_get_channel_map(struct snd_soc_dai *dai,
 				unsigned int *tx_num, unsigned int *tx_slot,
 				unsigned int *rx_num, unsigned int *rx_slot);
-static int lpass_cdc_wsa_macro_digital_mute(struct snd_soc_dai *dai, int mute);
+static int lpass_cdc_wsa_macro_mute_stream(struct snd_soc_dai *dai, int mute, int stream);
 /* Hold instance to soundwire platform device */
 struct lpass_cdc_wsa_macro_swr_ctrl_data {
 	struct platform_device *wsa_swr_pdev;
@@ -210,6 +237,7 @@ enum {
 struct lpass_cdc_wsa_macro_priv {
 	struct device *dev;
 	int comp_enabled[LPASS_CDC_WSA_MACRO_COMP_MAX];
+	int comp_mode[LPASS_CDC_WSA_MACRO_COMP_MAX];
 	int ec_hq[LPASS_CDC_WSA_MACRO_RX1 + 1];
 	u16 prim_int_users[LPASS_CDC_WSA_MACRO_RX1 + 1];
 	u16 wsa_mclk_users;
@@ -284,6 +312,11 @@ static const char * const lpass_cdc_wsa_macro_vbat_bcl_gsm_mode_text[] = {
 	"OFF", "ON"
 };
 
+static const char * const lpass_cdc_wsa_macro_comp_mode_text[] = {
+	"G_21_DB", "G_19P5_DB", "G_18_DB", "G_16P5_DB", "G_15_DB",
+	"G_13P5_DB", "G_12_DB", "G_10P5_DB", "G_9_DB"
+};
+
 static const struct snd_kcontrol_new wsa_int0_vbat_mix_switch[] = {
 	SOC_DAPM_SINGLE("WSA RX0 VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
 };
@@ -298,6 +331,8 @@ static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa_macro_spkr_boost_stage_enum,
 			lpass_cdc_wsa_macro_speaker_boost_stage_text);
 static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa_macro_vbat_bcl_gsm_mode_enum,
 			lpass_cdc_wsa_macro_vbat_bcl_gsm_mode_text);
+static SOC_ENUM_SINGLE_EXT_DECL(lpass_cdc_wsa_macro_comp_mode_enum,
+			lpass_cdc_wsa_macro_comp_mode_text);
 
 /* RX INT0 */
 static const struct soc_enum rx0_prim_inp0_chain_enum =
@@ -380,7 +415,7 @@ static const struct snd_kcontrol_new rx_mix_ec1_mux =
 static struct snd_soc_dai_ops lpass_cdc_wsa_macro_dai_ops = {
 	.hw_params = lpass_cdc_wsa_macro_hw_params,
 	.get_channel_map = lpass_cdc_wsa_macro_get_channel_map,
-	.digital_mute = lpass_cdc_wsa_macro_digital_mute,
+	.mute_stream = lpass_cdc_wsa_macro_mute_stream,
 };
 
 static struct snd_soc_dai_driver lpass_cdc_wsa_macro_dai[] = {
@@ -617,9 +652,9 @@ static int lpass_cdc_wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *da
 		for (j = 0; j < NUM_INTERPOLATORS; j++) {
 			int_mux_cfg1 = int_mux_cfg0 + LPASS_CDC_WSA_MACRO_MUX_CFG1_OFFSET;
 
-			int_mux_cfg0_val = snd_soc_component_read32(component,
+			int_mux_cfg0_val = snd_soc_component_read(component,
 							int_mux_cfg0);
-			int_mux_cfg1_val = snd_soc_component_read32(component,
+			int_mux_cfg1_val = snd_soc_component_read(component,
 							int_mux_cfg1);
 			inp0_sel = int_mux_cfg0_val & LPASS_CDC_WSA_MACRO_MUX_INP_MASK1;
 			inp1_sel = (int_mux_cfg0_val >>
@@ -681,7 +716,7 @@ static int lpass_cdc_wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai
 
 		int_mux_cfg1 = LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;
 		for (j = 0; j < NUM_INTERPOLATORS; j++) {
-			int_mux_cfg1_val = snd_soc_component_read32(component,
+			int_mux_cfg1_val = snd_soc_component_read(component,
 							int_mux_cfg1) &
 							LPASS_CDC_WSA_MACRO_MUX_INP_MASK1;
 			if (int_mux_cfg1_val == int_2_inp +
@@ -820,7 +855,7 @@ static int lpass_cdc_wsa_macro_get_channel_map(struct snd_soc_dai *dai,
 		*rx_num = cnt;
 		break;
 	case LPASS_CDC_WSA_MACRO_AIF_ECHO:
-		val = snd_soc_component_read32(component,
+		val = snd_soc_component_read(component,
 			LPASS_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
 		if (val & LPASS_CDC_WSA_MACRO_EC_MIX_TX1_MASK) {
 			mask |= 0x2;
@@ -840,7 +875,7 @@ static int lpass_cdc_wsa_macro_get_channel_map(struct snd_soc_dai *dai,
 	return 0;
 }
 
-static int lpass_cdc_wsa_macro_digital_mute(struct snd_soc_dai *dai, int mute)
+static int lpass_cdc_wsa_macro_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 {
 	struct snd_soc_component *component = dai->component;
 	struct device *wsa_dev = NULL;
@@ -869,11 +904,11 @@ static int lpass_cdc_wsa_macro_digital_mute(struct snd_soc_dai *dai, int mute)
 				LPASS_CDC_WSA_MACRO_RX_PATH_DSMDEM_OFFSET;
 		int_mux_cfg0 = LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
 		int_mux_cfg1 = int_mux_cfg0 + 4;
-		int_mux_cfg0_val = snd_soc_component_read32(component,
+		int_mux_cfg0_val = snd_soc_component_read(component,
 							int_mux_cfg0);
-		int_mux_cfg1_val = snd_soc_component_read32(component,
+		int_mux_cfg1_val = snd_soc_component_read(component,
 							int_mux_cfg1);
-		if (snd_soc_component_read32(component, dsm_reg) & 0x01) {
+		if (snd_soc_component_read(component, dsm_reg) & 0x01) {
 			if (int_mux_cfg0_val || (int_mux_cfg1_val & 0x38))
 				snd_soc_component_update_bits(component, reg,
 							0x20, 0x20);
@@ -1295,7 +1330,7 @@ static int lpass_cdc_wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
 		lpass_cdc_wsa_macro_enable_swr(w, kcontrol, event);
-		val = snd_soc_component_read32(component, gain_reg);
+		val = snd_soc_component_read(component, gain_reg);
 		val += offset_val;
 		snd_soc_component_write(component, gain_reg, val);
 		break;
@@ -1312,9 +1347,10 @@ static int lpass_cdc_wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
 static int lpass_cdc_wsa_macro_config_compander(struct snd_soc_component *component,
 				int comp, int event)
 {
-	u16 comp_ctl0_reg, rx_path_cfg0_reg;
+	u16 comp_ctl0_reg, comp_ctl8_reg, rx_path_cfg0_reg;
 	struct device *wsa_dev = NULL;
 	struct lpass_cdc_wsa_macro_priv *wsa_priv = NULL;
+	u16 mode = 0;
 
 	if (!lpass_cdc_wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__))
 		return -EINVAL;
@@ -1325,12 +1361,18 @@ static int lpass_cdc_wsa_macro_config_compander(struct snd_soc_component *compon
 	if (!wsa_priv->comp_enabled[comp])
 		return 0;
 
+	mode = wsa_priv->comp_mode[comp];
 	comp_ctl0_reg = LPASS_CDC_WSA_COMPANDER0_CTL0 +
 					(comp * LPASS_CDC_WSA_MACRO_RX_COMP_OFFSET);
+	comp_ctl8_reg = LPASS_CDC_WSA_COMPANDER0_CTL8 +
+					(comp * LPASS_CDC_WSA_MACRO_RX_COMP_OFFSET);
 	rx_path_cfg0_reg = LPASS_CDC_WSA_RX0_RX_PATH_CFG0 +
 					(comp * LPASS_CDC_WSA_MACRO_RX_PATH_OFFSET);
 
 	if (SND_SOC_DAPM_EVENT_ON(event)) {
+		lpass_cdc_update_compander_setting(component,
+					comp_ctl8_reg,
+					comp_setting_table[mode]);
 		/* Enable Compander Clock */
 		snd_soc_component_update_bits(component, comp_ctl0_reg,
 						0x01, 0x01);
@@ -1447,8 +1489,8 @@ static bool lpass_cdc_wsa_macro_adie_lb(struct snd_soc_component *component,
 
 	int_mux_cfg0 = LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
 	int_mux_cfg1 = int_mux_cfg0 + 4;
-	int_mux_cfg0_val = snd_soc_component_read32(component, int_mux_cfg0);
-	int_mux_cfg1_val = snd_soc_component_read32(component, int_mux_cfg1);
+	int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
+	int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
 
 	int_n_inp0 = int_mux_cfg0_val & 0x0F;
 	if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
@@ -1549,7 +1591,7 @@ static int lpass_cdc_wsa_macro_enable_prim_interpolator(
 				0x1, 0x1);
 		}
 		if ((reg != prim_int_reg) &&
-		    ((snd_soc_component_read32(
+		    ((snd_soc_component_read(
 				component, prim_int_reg)) & 0x10))
 			snd_soc_component_update_bits(component, reg,
 					0x10, 0x10);
@@ -1635,7 +1677,7 @@ static int lpass_cdc_wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w
 					0x01, 0x01);
 			offset_val = -2;
 		}
-		val = snd_soc_component_read32(component, gain_reg);
+		val = snd_soc_component_read(component, gain_reg);
 		val += offset_val;
 		snd_soc_component_write(component, gain_reg, val);
 		lpass_cdc_wsa_macro_config_ear_spkr_gain(component, wsa_priv,
@@ -1664,7 +1706,7 @@ static int lpass_cdc_wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w
 					LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC0,
 					0x01, 0x00);
 			offset_val = 2;
-			val = snd_soc_component_read32(component, gain_reg);
+			val = snd_soc_component_read(component, gain_reg);
 			val += offset_val;
 			snd_soc_component_write(component, gain_reg, val);
 		}
@@ -1759,7 +1801,7 @@ static int lpass_cdc_wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
 						0x01, 0x01);
 		snd_soc_component_update_bits(component, boost_path_ctl,
 						0x10, 0x10);
-		if ((snd_soc_component_read32(component, reg_mix)) & 0x10)
+		if ((snd_soc_component_read(component, reg_mix)) & 0x10)
 			snd_soc_component_update_bits(component, reg_mix,
 						0x10, 0x00);
 		break;
@@ -1919,7 +1961,7 @@ static int lpass_cdc_wsa_macro_enable_echo(struct snd_soc_dapm_widget *w,
 
 	dev_dbg(wsa_dev, "%s %d %s\n", __func__, event, w->name);
 
-	val = snd_soc_component_read32(component,
+	val = snd_soc_component_read(component,
 				LPASS_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
 	if (!(strcmp(w->name, "WSA RX_MIX EC0_MUX")))
 		ec_tx = (val & 0x07) - 1;
@@ -2134,6 +2176,54 @@ static int lpass_cdc_wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontro
 	return 0;
 }
 
+static int lpass_cdc_wsa_macro_comp_mode_get(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct device *wsa_dev = NULL;
+	struct lpass_cdc_wsa_macro_priv *wsa_priv = NULL;
+	u16 idx = 0;
+
+	if (!lpass_cdc_wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__))
+		return -EINVAL;
+
+	if (strnstr(kcontrol->id.name, "RX0", sizeof("WSA_RX0")))
+		idx = LPASS_CDC_WSA_MACRO_COMP1;
+	if (strnstr(kcontrol->id.name, "RX1", sizeof("WSA_RX1")))
+		idx = LPASS_CDC_WSA_MACRO_COMP2;
+	ucontrol->value.integer.value[0] = wsa_priv->comp_mode[idx];
+
+	dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
+		__func__, ucontrol->value.integer.value[0]);
+
+	return 0;
+}
+
+static int lpass_cdc_wsa_macro_comp_mode_put(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct device *wsa_dev = NULL;
+	struct lpass_cdc_wsa_macro_priv *wsa_priv = NULL;
+	u16 idx = 0;
+
+	if (!lpass_cdc_wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__))
+		return -EINVAL;
+
+	if (strnstr(kcontrol->id.name, "RX0", sizeof("WSA_RX0")))
+		idx = LPASS_CDC_WSA_MACRO_COMP1;
+	if (strnstr(kcontrol->id.name, "RX1", sizeof("WSA_RX1")))
+		idx = LPASS_CDC_WSA_MACRO_COMP2;
+	wsa_priv->comp_mode[idx] =  ucontrol->value.integer.value[0];
+
+	dev_dbg(component->dev, "%s: comp_mode = %d\n", __func__,
+		wsa_priv->comp_mode[idx]);
+
+	return 0;
+}
+
 static int lpass_cdc_wsa_macro_spkr_left_boost_stage_get(struct snd_kcontrol *kcontrol,
 			struct snd_ctl_elem_value *ucontrol)
 {
@@ -2141,7 +2231,7 @@ static int lpass_cdc_wsa_macro_spkr_left_boost_stage_get(struct snd_kcontrol *kc
 	struct snd_soc_component *component =
 				snd_soc_kcontrol_component(kcontrol);
 
-	bst_state_max = snd_soc_component_read32(component,
+	bst_state_max = snd_soc_component_read(component,
 				LPASS_CDC_WSA_BOOST0_BOOST_CTL);
 	bst_state_max = (bst_state_max & 0x0c) >> 2;
 	ucontrol->value.integer.value[0] = bst_state_max;
@@ -2173,7 +2263,7 @@ static int lpass_cdc_wsa_macro_spkr_right_boost_stage_get(struct snd_kcontrol *k
 	struct snd_soc_component *component =
 				snd_soc_kcontrol_component(kcontrol);
 
-	bst_state_max = snd_soc_component_read32(component,
+	bst_state_max = snd_soc_component_read(component,
 				LPASS_CDC_WSA_BOOST1_BOOST_CTL);
 	bst_state_max = (bst_state_max & 0x0c) >> 2;
 	ucontrol->value.integer.value[0] = bst_state_max;
@@ -2286,7 +2376,7 @@ static int lpass_cdc_wsa_macro_vbat_bcl_gsm_mode_func_get(struct snd_kcontrol *k
 			snd_soc_kcontrol_component(kcontrol);
 
 	ucontrol->value.integer.value[0] =
-	    ((snd_soc_component_read32(
+	    ((snd_soc_component_read(
 		component, LPASS_CDC_WSA_VBAT_BCL_VBAT_CFG) & 0x04) ?
 	    1 : 0);
 
@@ -2375,6 +2465,12 @@ static const struct snd_kcontrol_new lpass_cdc_wsa_macro_snd_controls[] = {
 	SOC_ENUM_EXT("GSM mode Enable", lpass_cdc_wsa_macro_vbat_bcl_gsm_mode_enum,
 		     lpass_cdc_wsa_macro_vbat_bcl_gsm_mode_func_get,
 		     lpass_cdc_wsa_macro_vbat_bcl_gsm_mode_func_put),
+	SOC_ENUM_EXT("WSA_RX0 comp_mode", lpass_cdc_wsa_macro_comp_mode_enum,
+		     lpass_cdc_wsa_macro_comp_mode_get,
+		     lpass_cdc_wsa_macro_comp_mode_put),
+	SOC_ENUM_EXT("WSA_RX1 comp_mode", lpass_cdc_wsa_macro_comp_mode_enum,
+		     lpass_cdc_wsa_macro_comp_mode_get,
+		     lpass_cdc_wsa_macro_comp_mode_put),
 	SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM,
 			LPASS_CDC_WSA_MACRO_SOFTCLIP0, 1, 0,
 			lpass_cdc_wsa_macro_soft_clip_enable_get,
@@ -2791,30 +2887,8 @@ static void lpass_cdc_wsa_macro_init_bcl_pmic_reg(struct snd_soc_component *comp
 
 	switch (wsa_priv->bcl_pmic_params.id) {
 	case 0:
-		/* Enable ID0 to listen to respective PMIC group interrupts */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x02, 0x02);
-		/* Update MC_SID0 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x0F,
-			wsa_priv->bcl_pmic_params.sid);
-		/* Update MC_PPID0 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0xFF,
-			wsa_priv->bcl_pmic_params.ppid);
 		break;
 	case 1:
-		/* Enable ID1 to listen to respective PMIC group interrupts */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x01, 0x01);
-		/* Update MC_SID1 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x0F,
-			wsa_priv->bcl_pmic_params.sid);
-		/* Update MC_PPID1 */
-		snd_soc_component_update_bits(component,
-			LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0xFF,
-			wsa_priv->bcl_pmic_params.ppid);
 		break;
 	default:
 		dev_err(wsa_dev, "%s: PMIC ID is invalid %d\n",

asoc/codecs/lpass-cdc/lpass-cdc.c

@@ -108,30 +108,9 @@ static int __lpass_cdc_reg_read(struct lpass_cdc_priv *priv,
 			goto ssr_err;
 	}
 
-	if (priv->version < LPASS_CDC_VERSION_2_0) {
-		/* Request Clk before register access */
-		ret = lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
-				priv->macro_params[macro_id].default_clk_id,
-				priv->macro_params[macro_id].clk_id_req,
-				true);
-		if (ret < 0) {
-			dev_err_ratelimited(priv->dev,
-				"%s: Failed to enable clock, ret:%d\n",
-				__func__, ret);
-			goto err;
-		}
-	}
-
 	lpass_cdc_ahb_read_device(
 		priv->macro_params[macro_id].io_base, reg, val);
 
-	if (priv->version < LPASS_CDC_VERSION_2_0)
-		lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
-				priv->macro_params[macro_id].default_clk_id,
-				priv->macro_params[macro_id].clk_id_req,
-				false);
-
-err:
 	if (priv->macro_params[VA_MACRO].dev) {
 		pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev);
 		pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev);
@@ -159,30 +138,9 @@ static int __lpass_cdc_reg_write(struct lpass_cdc_priv *priv,
 			goto ssr_err;
 	}
 
-	if (priv->version < LPASS_CDC_VERSION_2_0) {
-		/* Request Clk before register access */
-		ret = lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
-				priv->macro_params[macro_id].default_clk_id,
-				priv->macro_params[macro_id].clk_id_req,
-				true);
-		if (ret < 0) {
-			dev_err_ratelimited(priv->dev,
-				"%s: Failed to enable clock, ret:%d\n",
-				__func__, ret);
-			goto err;
-		}
-	}
-
 	lpass_cdc_ahb_write_device(
 			priv->macro_params[macro_id].io_base, reg, val);
 
-	if (priv->version < LPASS_CDC_VERSION_2_0)
-		lpass_cdc_clk_rsc_request_clock(priv->macro_params[macro_id].dev,
-				priv->macro_params[macro_id].default_clk_id,
-				priv->macro_params[macro_id].clk_id_req,
-				false);
-
-err:
 	if (priv->macro_params[VA_MACRO].dev) {
 		pm_runtime_mark_last_busy(priv->macro_params[VA_MACRO].dev);
 		pm_runtime_put_autosuspend(priv->macro_params[VA_MACRO].dev);
@@ -694,11 +652,9 @@ int lpass_cdc_register_macro(struct device *dev, u16 macro_id,
 	if (macro_id == TX_MACRO || macro_id == VA_MACRO)
 		priv->macro_params[macro_id].clk_div_get = ops->clk_div_get;
 
-	if (priv->version == LPASS_CDC_VERSION_2_1) {
-		if (macro_id == VA_MACRO)
-			priv->macro_params[macro_id].reg_wake_irq =
+	if (macro_id == VA_MACRO)
+		priv->macro_params[macro_id].reg_wake_irq =
 						ops->reg_wake_irq;
-	}
 	priv->num_dais += ops->num_dais;
 	priv->num_macros_registered++;
 	priv->macros_supported[macro_id] = true;
@@ -1047,15 +1003,9 @@ int lpass_cdc_register_wake_irq(struct snd_soc_component *component,
 		return -EINVAL;
 	}
 
-	if (priv->version == LPASS_CDC_VERSION_2_1) {
-		if (priv->macro_params[VA_MACRO].reg_wake_irq)
-			priv->macro_params[VA_MACRO].reg_wake_irq(
-					component, ipc_wakeup);
-	} else {
-		if (priv->macro_params[TX_MACRO].reg_wake_irq)
-			priv->macro_params[TX_MACRO].reg_wake_irq(
-					component, ipc_wakeup);
-	}
+	if (priv->macro_params[VA_MACRO].reg_wake_irq)
+		priv->macro_params[VA_MACRO].reg_wake_irq(
+				component, ipc_wakeup);
 
 	return 0;
 }
@@ -1155,9 +1105,9 @@ static int lpass_cdc_soc_codec_probe(struct snd_soc_component *component)
 	}
 
 	/* Assign lpass_cdc version */
-	core_id_0 = snd_soc_component_read32(component,
+	core_id_0 = snd_soc_component_read(component,
 					LPASS_CDC_VA_TOP_CSR_CORE_ID_0);
-	core_id_1 = snd_soc_component_read32(component,
+	core_id_1 = snd_soc_component_read(component,
 					LPASS_CDC_VA_TOP_CSR_CORE_ID_1);
 	if ((core_id_0 == 0x01) && (core_id_1 == 0x0F))
 		priv->version = LPASS_CDC_VERSION_2_0;
@@ -1314,10 +1264,6 @@ static int lpass_cdc_probe(struct platform_device *pdev)
 			__func__, priv->num_macros, MAX_MACRO);
 		return -EINVAL;
 	}
-	priv->va_without_decimation = of_property_read_bool(pdev->dev.of_node,
-						"qcom,va-without-decimation");
-	if (priv->va_without_decimation)
-		lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_top_reg_access;
 
 	ret = of_property_read_u32(pdev->dev.of_node,
 				"qcom,lpass-cdc-version", &priv->version);
@@ -1326,12 +1272,6 @@ static int lpass_cdc_probe(struct platform_device *pdev)
 			__func__);
 		ret = 0;
 	}
-	if (priv->version == LPASS_CDC_VERSION_2_1) {
-		lpass_cdc_reg_access[TX_MACRO] = lpass_cdc_tx_reg_access_v2;
-		lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_reg_access_v2;
-	} else if (priv->version == LPASS_CDC_VERSION_2_0) {
-		lpass_cdc_reg_access[VA_MACRO] = lpass_cdc_va_reg_access_v3;
-	}
 
 	priv->dev = &pdev->dev;
 	priv->dev_up = true;

asoc/codecs/lpass-cdc/lpass-cdc.h

@@ -20,6 +20,7 @@ enum {
 	RX_MACRO,
 	WSA_MACRO,
 	VA_MACRO,
+	WSA2_MACRO,
 	MAX_MACRO
 };