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disp: msm: sde: avoid double clearing of INTR registers

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When there is CPU processing delay between first INTR clear and
second INTR clear there is a chance that the second register
write might clear the next frames interrupts which will avoid
triggering the irq callbacks causing software hung. This
patch avoids such a scenario by removing such double clearing
of INTR registers.

Change-Id: I8407991769c69d2d2c691763240671d5f3c0416d
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This commit is contained in:
Mahadevan
2023-11-02 23:09:22 +05:30
parent e16b13269d
commit 859ee56480
3 changed files with 3 additions and 27 deletions
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10
msm/sde/sde_hw_interrupts.c
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@@ -478,16 +478,11 @@ static void sde_hw_intr_dispatch_irq(struct sde_hw_intr *intr,
reg_idx)) {
/*
* Once a match on irq mask, perform a callback
* to the given cbfunc. cbfunc will take care
* the interrupt status clearing. If cbfunc is
* not provided, then the interrupt clearing
* is here.
* to the given cbfunc. This callback is done
* after clearing the interrupt registers.
*/
if (cbfunc)
cbfunc(arg, irq_idx);
else
intr->ops.clear_intr_status_nolock(
intr, irq_idx);
/*
* When callback finish, clear the irq_status
@@ -851,7 +846,6 @@ static void __setup_intr_ops(struct sde_hw_intr_ops *ops)
ops->disable_all_irqs = sde_hw_intr_disable_irqs;
ops->get_interrupt_sources = sde_hw_intr_get_interrupt_sources;
ops->clear_interrupt_status = sde_hw_intr_clear_interrupt_status;
ops->clear_intr_status_nolock = sde_hw_intr_clear_intr_status_nolock;
ops->get_interrupt_status = sde_hw_intr_get_interrupt_status;
ops->get_intr_status_nolock = sde_hw_intr_get_intr_status_nolock;
}