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qcacmn: Unify io memory access

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Snoc and pci should use the same memory access semantics.

Change-Id: I0f9eb8d0517853426897acd712c343b7ac7a5a1f
CRs-Fixed: 986480
This commit is contained in:
Houston Hoffman
2016-03-14 21:11:54 -07:00
committed by Vishwajith Upendra
parent dd50043a6e
commit 858f723a62
4 changed files with 24 additions and 56 deletions
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24
hif/src/hif_io32.h
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@@ -31,6 +31,11 @@
#include <linux/io.h>
#include "ol_if_athvar.h"
#include "hif.h"
#define hif_read32_mb(addr) ioread32((void __iomem *)addr)
#define hif_write32_mb(addr, value) \
iowrite32((u32)(value), (void __iomem *)(addr))
#ifdef HIF_PCI
#include "hif_io32_pci.h"
#endif
@@ -38,4 +43,23 @@
#ifdef HIF_SNOC
#include "hif_io32_snoc.h"
#endif /* HIF_PCI */
#ifdef CONFIG_IO_MEM_ACCESS_DEBUG
uint32_t hif_target_read_checked(struct hif_softc *scn,
uint32_t offset);
void hif_target_write_checked(struct hif_softc *scn, uint32_t offset,
uint32_t value);
#define A_TARGET_READ(scn, offset) \
hif_target_read_checked(scn, (offset))
#define A_TARGET_WRITE(scn, offset, value) \
hif_target_write_checked(scn, (offset), (value))
#else /* CONFIG_ATH_PCIE_ACCESS_DEBUG */
#define A_TARGET_READ(scn, offset) \
hif_read32_mb(scn->mem + (offset))
#define A_TARGET_WRITE(scn, offset, value) \
hif_write32_mb((scn->mem) + (offset), value)
#endif
#endif /* __HIF_IO32_H__ */

21
hif/src/pcie/hif_io32_pci.h
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@@ -84,10 +84,6 @@
/* AXI gating when L1, L2 to reduce power consumption */
#define CONFIG_PCIE_ENABLE_AXI_CLK_GATE 0
#define hif_read32_mb(addr) ioread32((void __iomem *)addr)
#define hif_write32_mb(addr, value) \
iowrite32((u32)(value), (void __iomem *)(addr))
#if CONFIG_ATH_PCIE_MAX_PERF
#define A_TARGET_ACCESS_BEGIN(scn) \
do {struct hif_softc *unused = scn; \
@@ -211,23 +207,6 @@ do { \
#endif /* CONFIG_ATH_PCIE_ACCESS_LIKELY */
#endif /* CONFIG_ATH_PCIE_MAX_PERF */
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
extern uint32_t hif_target_read_checked(struct hif_softc *scn,
uint32_t offset);
extern void hif_target_write_checked(struct hif_softc *scn, uint32_t offset,
uint32_t value);
#define A_TARGET_READ(scn, offset) \
hif_target_read_checked(scn, (offset))
#define A_TARGET_WRITE(scn, offset, value) \
hif_target_write_checked(scn, (offset), (value))
#else /* CONFIG_ATH_PCIE_ACCESS_DEBUG */
#define A_TARGET_READ(scn, offset) \
hif_read32_mb(scn->mem + (offset))
#define A_TARGET_WRITE(scn, offset, value) \
hif_write32_mb((scn->mem) + (offset), value);
#endif
irqreturn_t hif_fw_interrupt_handler(int irq, void *arg);
/**

34
hif/src/snoc/hif_io32_snoc.h
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@@ -61,40 +61,6 @@
#define Q_TARGET_ACCESS_BEGIN(scn) 0
#define Q_TARGET_ACCESS_END(scn) 0
/**
* hif_write32_mb - SNOC write 32
* @addr: physical address
* @value: value
*
* Return: N/A
*/
static inline void hif_write32_mb(void __iomem *addr, uint32_t value)
{
wmb(); /* write memory barrier */
writel_relaxed((value), (addr));
wmb(); /* write memory barrier */
}
/**
* hif_read32_mb - SNOC read 32
* @addr: physical address
*
* Return: N/A
*/
static inline uint32_t hif_read32_mb(void __iomem *addr)
{
uint32_t tmp;
rmb(); /* read memory barrier */
tmp = readl_relaxed(addr);
rmb(); /* read memory barrier */
return tmp;
}
#define A_TARGET_READ(scn, offset) \
hif_read32_mb(scn->mem + (offset))
#define A_TARGET_WRITE(scn, offset, value) \
hif_write32_mb((scn->mem + offset), (value))
#define ADRASTEA_CE_INTR_ENABLES 0x002F00A8
#define ADRASTEA_CE_INTR_ENABLES_SET "COMING IN REGISTER SET36"
#define ADRASTEA_CE_INTR_ENABLES_CLEAR "COMING IN REGISTER SET36"

1
htc/htc.c
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@@ -32,7 +32,6 @@
#include <qdf_types.h> /* qdf_print */
#include <hif.h>
#include "epping_main.h"
#include "hif_io32.h"
#include "cds_concurrency.h"
#include <cds_api.h>