qcacmn: enable MEC support for Beryllium

The multicast echo check feature is moved to hardware in
Beryllium. Enable this hardware feature and also disable
the MEC handing code for Beryllium in the host.

Change-Id: I86d319963191f3ed77aba16dcccbc659906edd9f
This commit is contained in:
Pavankumar Nandeshwar
2021-08-23 13:33:46 -07:00
committed by Madan Koyyalamudi
parent ebc826e655
commit 851b1f68c0
7 changed files with 38 additions and 8 deletions

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@@ -1127,6 +1127,9 @@ struct ol_if_ops {
uint8_t (*freq_to_band)(struct cdp_ctrl_objmgr_psoc *psoc, uint8_t (*freq_to_band)(struct cdp_ctrl_objmgr_psoc *psoc,
uint8_t pdev_id, uint16_t freq); uint8_t pdev_id, uint16_t freq);
QDF_STATUS(*set_mec_timer)(struct cdp_ctrl_objmgr_psoc *psoc,
uint8_t vdev_id, uint16_t mec_timer_val);
#ifdef ATH_SUPPORT_NAC_RSSI #ifdef ATH_SUPPORT_NAC_RSSI
int (*config_fw_for_nac_rssi)(struct cdp_ctrl_objmgr_psoc *psoc, int (*config_fw_for_nac_rssi)(struct cdp_ctrl_objmgr_psoc *psoc,
uint8_t pdev_id, uint8_t pdev_id,

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@@ -24,6 +24,9 @@
#include "dp_be_rx.h" #include "dp_be_rx.h"
#include <hal_be_api.h> #include <hal_be_api.h>
/* Generic AST entry aging timer value */
#define DP_AST_AGING_TIMER_DEFAULT_MS 5000
#if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = { static struct wlan_cfg_tcl_wbm_ring_num_map g_tcl_wbm_map_array[MAX_TCL_DATA_RINGS] = {
{.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0}, {.tcl_ring_num = 0, .wbm_ring_num = 0, .wbm_rbm_id = HAL_BE_WBM_SW0_BM_ID, .for_ipa = 0},
@@ -470,9 +473,16 @@ static QDF_STATUS dp_vdev_attach_be(struct dp_soc *soc, struct dp_vdev *vdev)
return QDF_STATUS_E_FAULT; return QDF_STATUS_E_FAULT;
} }
if (vdev->opmode == wlan_op_mode_sta) if (vdev->opmode == wlan_op_mode_sta) {
if (soc->cdp_soc.ol_ops->set_mec_timer)
soc->cdp_soc.ol_ops->set_mec_timer(
soc->ctrl_psoc,
vdev->vdev_id,
DP_AST_AGING_TIMER_DEFAULT_MS);
hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id, hal_tx_vdev_mcast_ctrl_set(soc->hal_soc, vdev->vdev_id,
HAL_TX_MCAST_CTRL_MEC_NOTIFY); HAL_TX_MCAST_CTRL_MEC_NOTIFY);
}
return QDF_STATUS_SUCCESS; return QDF_STATUS_SUCCESS;
} }

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@@ -242,8 +242,6 @@ static uint8_t dp_soc_ring_if_nss_offloaded(struct dp_soc *soc,
#define MON_VDEV_TIMER_INIT 0x1 #define MON_VDEV_TIMER_INIT 0x1
#define MON_VDEV_TIMER_RUNNING 0x2 #define MON_VDEV_TIMER_RUNNING 0x2
/* Generic AST entry aging timer value */
#define DP_AST_AGING_TIMER_DEFAULT_MS 1000
#define DP_MCS_LENGTH (6*MAX_MCS) #define DP_MCS_LENGTH (6*MAX_MCS)
#define DP_CURR_FW_STATS_AVAIL 19 #define DP_CURR_FW_STATS_AVAIL 19
@@ -13124,7 +13122,7 @@ static void dp_soc_cfg_init(struct dp_soc *soc)
soc->wbm_release_desc_rx_sg_support = 1; soc->wbm_release_desc_rx_sg_support = 1;
soc->rxdma2sw_rings_not_supported = 1; soc->rxdma2sw_rings_not_supported = 1;
soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS; soc->ast_offload_support = AST_OFFLOAD_ENABLE_STATUS;
soc->mec_fw_offload = FW_MEC_FW_OFFLOAD_ENABLED;
break; break;
default: default:
qdf_print("%s: Unknown tgt type %d\n", __func__, target_type); qdf_print("%s: Unknown tgt type %d\n", __func__, target_type);

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@@ -1342,9 +1342,11 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
} }
} }
if (dp_rx_mcast_echo_check(soc, peer, rx_tlv_hdr, nbuf)) { if ((!soc->mec_fw_offload) &&
dp_rx_mcast_echo_check(soc, peer, rx_tlv_hdr, nbuf)) {
/* this is a looped back MCBC pkt, drop it */ /* this is a looped back MCBC pkt, drop it */
DP_STATS_INC_PKT(peer, rx.mec_drop, 1, qdf_nbuf_len(nbuf)); DP_STATS_INC_PKT(peer, rx.mec_drop, 1,
qdf_nbuf_len(nbuf));
goto drop_nbuf; goto drop_nbuf;
} }
@@ -2847,7 +2849,11 @@ done:
err_code, err_code,
pool_id); pool_id);
break; break;
case HAL_RXDMA_MULTICAST_ECHO:
DP_STATS_INC_PKT(peer, rx.mec_drop, 1,
qdf_nbuf_len(nbuf));
qdf_nbuf_free(nbuf);
break;
default: default:
qdf_nbuf_free(nbuf); qdf_nbuf_free(nbuf);
dp_err_rl("RXDMA error %d", dp_err_rl("RXDMA error %d",

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@@ -4381,6 +4381,7 @@ void dp_tx_process_htt_completion(struct dp_soc *soc,
* descriptor in case of MEC notify. * descriptor in case of MEC notify.
*/ */
if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) { if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
qdf_assert_always(!soc->mec_fw_offload);
/* /*
* Get vdev id from HTT status word in case of MEC * Get vdev id from HTT status word in case of MEC
* notification * notification

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@@ -126,6 +126,12 @@
#define AST_OFFLOAD_ENABLE_STATUS 0 #define AST_OFFLOAD_ENABLE_STATUS 0
#endif #endif
#ifdef FEATURE_MEC_OFFLOAD
#define FW_MEC_FW_OFFLOAD_ENABLED 1
#else
#define FW_MEC_FW_OFFLOAD_ENABLED 0
#endif
#define PCP_TID_MAP_MAX 8 #define PCP_TID_MAP_MAX 8
#define MAX_MU_USERS 37 #define MAX_MU_USERS 37
@@ -2124,7 +2130,8 @@ struct dp_soc {
#ifdef WIFI_MONITOR_SUPPORT #ifdef WIFI_MONITOR_SUPPORT
struct dp_mon_soc *monitor_soc; struct dp_mon_soc *monitor_soc;
#endif #endif
bool rxdma2sw_rings_not_supported; uint8_t rxdma2sw_rings_not_supported:1,
mec_fw_offload:1;
}; };
#ifdef IPA_OFFLOAD #ifdef IPA_OFFLOAD

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@@ -574,6 +574,9 @@ enum hal_reo_error_code {
* @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout
* @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout
* @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request
* @ HAL_RXDMA_AMSDU_FRAGMENT : Rx PCU reported A-MSDU
* present as well as a fragmented MPDU
* @ HAL_RXDMA_MULTICAST_ECHO : RX OLE reported a multicast echo
* @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors
*/ */
enum hal_rxdma_error_code { enum hal_rxdma_error_code {
@@ -591,6 +594,8 @@ enum hal_rxdma_error_code {
HAL_RXDMA_ERR_DA_TIMEOUT, HAL_RXDMA_ERR_DA_TIMEOUT,
HAL_RXDMA_ERR_FLOW_TIMEOUT, HAL_RXDMA_ERR_FLOW_TIMEOUT,
HAL_RXDMA_ERR_FLUSH_REQUEST, HAL_RXDMA_ERR_FLUSH_REQUEST,
HAL_RXDMA_AMSDU_FRAGMENT,
HAL_RXDMA_MULTICAST_ECHO,
HAL_RXDMA_ERR_WAR = 31, HAL_RXDMA_ERR_WAR = 31,
HAL_RXDMA_ERR_MAX HAL_RXDMA_ERR_MAX
}; };