From 85191774b52d8a014e7b1023feec98ef9c87661c Mon Sep 17 00:00:00 2001 From: c_priys Date: Thu, 31 May 2018 12:46:53 +0530 Subject: [PATCH] qcacmn: Re-configure interrupt bits once again after FW resets Issue: Customer sees a lot of NOC errors after wifi comes up as FW resets the interrupt bits that host configured and then checks whether interrupt bits are enabled. FW then enters into MSI mode without filling the necessary MSI address and MSI data registers with proper values and this leads to lot of NOC errors on the platform. Fix description: Configure the interrupt bits one more time after FW resets the registers and then mark the host ready bit in FW indicator address CRs-Fixed: 2056198 Change-Id: I7a8871a9878b415ec90c4938df669c6225e79586 --- hif/src/snoc/if_ahb.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hif/src/snoc/if_ahb.c b/hif/src/snoc/if_ahb.c index 4ff662e59a..9d493f196d 100644 --- a/hif/src/snoc/if_ahb.c +++ b/hif/src/snoc/if_ahb.c @@ -363,6 +363,23 @@ irqreturn_t hif_ahb_interrupt_handler(int irq, void *context) */ int hif_target_sync_ahb(struct hif_softc *scn) { + int val = 0; + int limit = 0; + + while (limit < 50) { + hif_write32_mb(scn->mem + + (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), + PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); + qdf_mdelay(10); + val = hif_read32_mb(scn->mem + + (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)); + if (val == 0) + break; + limit++; + } + hif_write32_mb(scn->mem + + (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS), + PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); hif_write32_mb(scn->mem + FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); if (HAS_FW_INDICATOR) { int wait_limit = 500;