qcacmn: Add hal_rx_tid_get API
Implement hal_rx_tid_get API based on the chipset as the macro to retrieve tid value is chipset dependent. Change-Id: I37eab3f3c1c2bbba6094b9ddb24d72712b819f73 CRs-Fixed: 2522133
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nshrivas

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5ddc518b2e
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8513048ac9
@@ -569,6 +569,31 @@ static bool hal_rx_is_unicast_9000(uint8_t *buf)
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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/**
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* hal_rx_tid_get_9000: get tid based on qos control valid.
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* @hal_soc_hdl: hal soc handle
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* @buf: pointer to rx pkt TLV.
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*
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* Return: tid
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*/
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static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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uint8_t qos_control_valid =
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),
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RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,
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RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
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if (qos_control_valid)
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return hal_rx_mpdu_start_tid_get_8074v2(buf);
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return HAL_RX_NON_QOS_TID;
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}
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struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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/* init and setup */
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@@ -633,6 +658,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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hal_rx_mpdu_get_addr4_9000,
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hal_rx_get_mpdu_sequence_control_valid_9000,
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hal_rx_is_unicast_9000,
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hal_rx_tid_get_9000,
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};
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struct hal_hw_srng_config hw_srng_table_9000[] = {
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