Merge "qcedev: vote at lowsvs by default in hlos"

crypto-qti/qce.h

@@ -56,8 +56,8 @@
 #define QCE_BW_REQUEST_RESET_FIRST	4
 
 /* default average and peak bw for crypto device */
-#define CRYPTO_AVG_BW			100100
-#define CRYPTO_PEAK_BW			100100
+#define CRYPTO_AVG_BW			384
+#define CRYPTO_PEAK_BW			384
 
 typedef void (*qce_comp_func_ptr_t)(void *areq,
 		unsigned char *icv, unsigned char *iv, int ret);

crypto-qti/qce50.c

@@ -269,6 +269,13 @@ static int qce_crypto_config(struct qce_device *pce_dev,
 	return 0;
 }
 
+static void qce_enable_clock_gating(struct qce_device *pce_dev)
+{
+	writel_relaxed(0x1, pce_dev->iobase + CRYPTO_PWR_CTRL);
+	//Write memory barrier
+	wmb();
+}
+
 /*
  * IV counter mask is be set based on the values sent through the offload ioctl
  * calls. Currently for offload operations, it is 64 bytes of mask for AES CTR,
@@ -2359,6 +2366,8 @@ int qce_manage_timeout(void *handle, int req_info)
 	if (qce_sps_pipe_reset(pce_dev, op))
 		pr_err("%s: pipe reset failed\n", __func__);
 
+	qce_enable_clock_gating(pce_dev);
+
 	if (_qce_unlock_other_pipes(pce_dev, req_info))
 		pr_err("%s: fail unlock other pipes\n", __func__);
 
@@ -5330,6 +5339,7 @@ static int _qce_resume(void *handle)
 			pr_err("Producer cb registration failed rc = %d\n",
 								rc);
 	}
+	qce_enable_clock_gating(pce_dev);
 
 	return rc;
 }
@@ -6591,6 +6601,7 @@ void *qce_open(struct platform_device *pdev, int *rc)
 	pce_dev->dev_no = pcedev_no;
 	pcedev_no++;
 	pce_dev->owner = QCE_OWNER_NONE;
+	qce_enable_clock_gating(pce_dev);
 	mutex_unlock(&qce_iomap_mutex);
 	return pce_dev;
 err:

crypto-qti/qcryptohw_50.h

@@ -281,6 +281,7 @@
 #define CRYPTO_AUTH_EXP_MAC7_REG		0x1A3BC
 
 #define CRYPTO_CONFIG_REG			0x1A400
+#define CRYPTO_PWR_CTRL				0x1A408
 #define CRYPTO_DEBUG_ENABLE_REG			0x1AF00
 #define CRYPTO_DEBUG_REG			0x1AF04