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@@ -0,0 +1,102 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef CAM_JPEG_ENC_780_HW_INFO_TITAN170_H
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+#define CAM_JPEG_ENC_780_HW_INFO_TITAN170_H
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+
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+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK 0x00000001
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+#define CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_SHIFT 0x00000000
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+
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+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK 0x10000000
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+#define CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_SHIFT 0x0000000a
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+
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+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK 0x8000000
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+#define CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_SHIFT 0x0000001b
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+
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+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_MASK 0x00000800
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+#define CAM_JPEG_HW_IRQ_STATUS_BUS_ERROR_SHIFT 0x0000000b
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+
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+#define CAM_JPEG_HW_MASK_SCALE_ENABLE 0x1
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+
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF (0x1<<19)
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR (0x1<<20)
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR (0x1<<21)
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF (0x1<<22)
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW (0x1<<23)
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM (0x1<<24)
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ (0x1<<25)
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+#define CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM (0x1<<26)
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+#define CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK (0x1<<29)
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+
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+#define CAM_JPEG_HW_MASK_COMP_FRAMEDONE \
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+ CAM_JPEG_HW_IRQ_STATUS_FRAMEDONE_MASK
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+#define CAM_JPEG_HW_MASK_COMP_RESET_ACK \
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+ CAM_JPEG_HW_IRQ_STATUS_RESET_ACK_MASK
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+#define CAM_JPEG_HW_MASK_COMP_ERR \
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+ (CAM_JPEG_HW_IRQ_STATUS_DCD_UNESCAPED_FF | \
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+ CAM_JPEG_HW_IRQ_STATUS_DCD_HUFFMAN_ERROR | \
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+ CAM_JPEG_HW_IRQ_STATUS_DCD_COEFFICIENT_ERR | \
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+ CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_BIT_STUFF | \
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+ CAM_JPEG_HW_IRQ_STATUS_DCD_SCAN_UNDERFLOW | \
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+ CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM | \
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+ CAM_JPEG_HW_IRQ_STATUS_DCD_INVALID_RSM_SEQ | \
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+ CAM_JPEG_HW_IRQ_STATUS_DCD_MISSING_RSM | \
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+ CAM_JPEG_HW_IRQ_STATUS_VIOLATION_MASK)
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+
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+static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_780_hw_info = {
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+ .reg_offset = {
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+ .hw_version = 0x0,
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+ .int_clr = 0x1c,
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+ .int_status = 0x20,
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+ .int_mask = 0x18,
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+ .hw_cmd = 0x10,
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+ .reset_cmd = 0x8,
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+ .encode_size = 0x180,
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+ .core_cfg = 0xc,
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+ .misr_cfg = 0x2B4,
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+ .misr_rd0 = 0x2B8,
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+ },
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+ .reg_val = {
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+ .int_clr_clearall = 0xFFFFFFFF,
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+ .int_mask_disable_all = 0x00000000,
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+ .int_mask_enable_all = 0xFFFFFFFF,
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+ .hw_cmd_start = 0x00000001,
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+ .reset_cmd = 0x200320D3,
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+ .hw_cmd_stop = 0x00000002,
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+ .misr_cfg = 0x7,
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+ },
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+ .int_status = {
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+ .framedone = CAM_JPEG_HW_MASK_COMP_FRAMEDONE,
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+ .resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK,
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+ .iserror = CAM_JPEG_HW_MASK_COMP_ERR,
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+ .stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK,
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+ .scale_enable = CAM_JPEG_HW_MASK_SCALE_ENABLE,
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+ .scale_enable_shift = 0x7,
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+ },
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+ .reg_dump = {
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+ .start_offset = 0x0,
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+ .end_offset = 0x33C,
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+ },
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+ .camnoc_misr_reg_offset = {
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+ .main_ctl = 0x2C88,
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+ .id_mask_low = 0x2CA0,
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+ .id_value_low = 0x2C98,
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+ .misc_ctl = 0x2C90,
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+ },
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+ .camnoc_misr_reg_val = {
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+ .main_ctl = 0x3,
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+ .id_mask_low = 0xFC0,
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+ .id_value_low_rd = 0xD80,
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+ .id_value_low_wr = 0xDC2,
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+ .misc_ctl_start = 0x1,
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+ .misc_ctl_stop = 0x2,
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+ },
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+ .max_misr = 3,
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+ .max_misr_rd = 4,
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+ .camnoc_misr_sigdata = 0,
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+ .camnoc_misr_support = 0,
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+};
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+
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+#endif /* CAM_JPEG_ENC_780_HW_INFO_TITAN170_H */
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