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asoc: codecs: Add current_limit updates to WSA884x

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Boost current limit is now dependent on PBR and bat_cfg.
Add BOP2 VTH/HST initial settings.
Add OCP LOW VBAT ITH sel settings dependent on bat_cfg.

Change-Id: I235f4b75ee12e5f24d46fa0ebca67547997934e2
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
This commit is contained in:
Matthew Rice
2022-01-19 16:52:19 -08:00
committed by Gerrit - the friendly Code Review server
parent 233a0dcb1b
commit 823dd9bab9
3 changed files with 56 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
asoc/codecs/wsa884x/wsa884x-reg-masks.h
View File

@@ -17,6 +17,9 @@
#define FIELD_MASK(register_name, field_name) \
WSA884X_##register_name##_##field_name##_MASK
/* WSA884X_BOP2_PROG Fields: */
#define WSA884X_BOP2_PROG_BOP2_VTH_MASK 0xf0
#define WSA884X_BOP2_PROG_BOP2_HYST_MASK 0x0f
/* WSA884X_VSENSE1 Fields: */
#define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK 0xe0
#define WSA884X_VSENSE1_VSENSE_AMP_IQ_CTL_1_MASK 0x10
@@ -40,6 +43,14 @@
#define WSA884X_ADC_7_EN_AZ_REG_MASK 0x04
#define WSA884X_ADC_7_EN_SAR_REG_MASK 0x02
#define WSA884X_ADC_7_EN_SW_CURRENT_REG_MASK 0x01
/* WSA884X_TOP_CTRL1 Fields: */
#define WSA884X_TOP_CTRL1_IDLE_PWRSAV_OVERRIDE_MASK 0x80
#define WSA884X_TOP_CTRL1_DAC_LDO_PROG_MASK 0x60
#define WSA884X_TOP_CTRL1_DATA_INV_MASK 0x10
#define WSA884X_TOP_CTRL1_DATA_RESET_MASK 0x08
#define WSA884X_TOP_CTRL1_CLK_DIV2_MASK 0x04
#define WSA884X_TOP_CTRL1_CLK_INV_MASK 0x02
#define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_SEL_EN_MASK 0x01
/* WSA884X_BOP_DEGLITCH_CTL Fields: */
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK 0x1e
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK 0x01

11
asoc/codecs/wsa884x/wsa884x-reg-shifts.h
View File

@@ -17,6 +17,9 @@
#define FIELD_SHIFT(register_name, field_name) \
WSA884X_##register_name##_##field_name##_SHIFT
/* WSA884X_BOP2_PROG Fields: */
#define WSA884X_BOP2_PROG_BOP2_VTH_SHIFT 0x04
#define WSA884X_BOP2_PROG_BOP2_HYST_SHIFT 0x00
/* WSA884X_VSENSE1 Fields: */
#define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 0x05
#define WSA884X_VSENSE1_VSENSE_AMP_IQ_CTL_1_SHIFT 0x04
@@ -40,6 +43,14 @@
#define WSA884X_ADC_7_EN_AZ_REG_SHIFT 0x02
#define WSA884X_ADC_7_EN_SAR_REG_SHIFT 0x01
#define WSA884X_ADC_7_EN_SW_CURRENT_REG_SHIFT 0x00
/* WSA884X_TOP_CTRL1 Fields: */
#define WSA884X_TOP_CTRL1_IDLE_PWRSAV_OVERRIDE_SHIFT 0x07
#define WSA884X_TOP_CTRL1_DAC_LDO_PROG_SHIFT 0x05
#define WSA884X_TOP_CTRL1_DATA_INV_SHIFT 0x04
#define WSA884X_TOP_CTRL1_DATA_RESET_SHIFT 0x03
#define WSA884X_TOP_CTRL1_CLK_DIV2_SHIFT 0x02
#define WSA884X_TOP_CTRL1_CLK_INV_SHIFT 0x01
#define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_SEL_EN_SHIFT 0x00
/* WSA884X_BOP_DEGLITCH_CTL Fields: */
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 0x01
#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0x00

36
asoc/codecs/wsa884x/wsa884x.c
View File

@@ -115,6 +115,8 @@ static const struct wsa_reg_mask_val reg_init[] = {
{REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
{REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
{REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
{REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
{REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
};
static int wsa884x_handle_post_irq(void *data);
@@ -1379,14 +1381,40 @@ static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
REG_FIELD_VALUE(PWM_CLK_CTL,
PWM_CLK_FREQ_SEL, 0x01));
}
if (wsa884x->pbr_enable)
if (wsa884x->pbr_enable) {
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(CURRENT_LIMIT,
CURRENT_LIMIT_OVRD_EN, 0x00));
else
switch (wsa884x->bat_cfg) {
case CONFIG_1S:
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(CURRENT_LIMIT,
CURRENT_LIMIT, 0x15));
break;
case CONFIG_2S:
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(CURRENT_LIMIT,
CURRENT_LIMIT, 0x11));
break;
case CONFIG_3S:
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(CURRENT_LIMIT,
CURRENT_LIMIT, 0x0D));
break;
}
} else {
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(CURRENT_LIMIT,
CURRENT_LIMIT_OVRD_EN, 0x01));
if (wsa884x->system_gain >= G_12_DB)
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(CURRENT_LIMIT,
CURRENT_LIMIT, 0x15));
else
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(CURRENT_LIMIT,
CURRENT_LIMIT, 0x09));
}
/* Force remove group */
swr_remove_from_group(wsa884x->swr_slave,
wsa884x->swr_slave->dev_num);
@@ -2124,6 +2152,10 @@ static int wsa884x_swr_probe(struct swr_device *pdev)
REG_FIELD_VALUE(PWM_CLK_CTL,
PWM_CLK_FREQ_SEL, 0x01));
}
if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
snd_soc_component_update_bits(component,
REG_FIELD_VALUE(TOP_CTRL1,
OCP_LOWVBAT_ITH_SEL_EN, 0x00));
mutex_init(&wsa884x->res_lock);