qcacmn: Fix for BMI transaction timed out

Root Cause : We are observing BMI transaction issue beacuase the
             Fw signal is getting timed out as FW independent bit
             is not getting set.
Solution : Read the register value for flushing the PCIe write

Change-Id: I1c877449104dc9e23eaaa18ef848730c81dd5c02
CRs-Fixed: 2266242

hif/src/pcie/if_pci.c

@@ -3735,8 +3735,11 @@ end:
 static void hif_target_sync(struct hif_softc *scn)
 {
 	hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS |
-				PCIE_INTR_ENABLE_ADDRESS),
-				PCIE_INTR_FIRMWARE_MASK);
+			    PCIE_INTR_ENABLE_ADDRESS),
+			    PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
+	/* read to flush pcie write */
+	(void)hif_read32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS |
+			PCIE_INTR_ENABLE_ADDRESS));
 
 	hif_write32_mb(scn, scn->mem + PCIE_LOCAL_BASE_ADDRESS +
 			PCIE_SOC_WAKE_ADDRESS,
@@ -3757,8 +3760,11 @@ static void hif_target_sync(struct hif_softc *scn)
 			if (wait_limit-- < 0)
 				break;
 			hif_write32_mb(scn, scn->mem + (SOC_CORE_BASE_ADDRESS |
-				PCIE_INTR_ENABLE_ADDRESS),
-				PCIE_INTR_FIRMWARE_MASK);
+			    PCIE_INTR_ENABLE_ADDRESS),
+			    PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
+			    /* read to flush pcie write */
+			(void)hif_read32_mb(scn, scn->mem +
+			    (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS));
 
 			qdf_mdelay(10);
 		}