qcacmn: Add HAL macros in dp_rx_defrag.c
Add the following HAL macros: 1. HAL_RX_MSDU0_BUFFER_ADDR_LSB 2. HAL_RX_MSDU_DESC_INFO_PTR_GET 3. HAL_ENT_MPDU_DESC_INFO 4. HAL_DST_MPDU_DESC_INFO Add relevant function pointers to retrieve descriptor info from the macros based on chipsets. Change-Id: I99ce7566a668180c7849eedea915b6f23a8dbf35 CRs-Fixed: 2522133
This commit is contained in:

committed by
nshrivas

parent
38e84d2722
commit
8227240793
@@ -1038,9 +1038,7 @@ dp_rx_defrag_nwifi_to_8023(struct dp_soc *soc,
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qdf_assert(link_desc_va);
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qdf_assert(link_desc_va);
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msdu0 = (uint8_t *)link_desc_va +
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msdu0 = hal_rx_msdu0_buffer_addr_lsb(soc->hal_soc, link_desc_va);
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RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET;
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nbuf_len = qdf_nbuf_len(head) - RX_PKT_TLVS_LEN;
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nbuf_len = qdf_nbuf_len(head) - RX_PKT_TLVS_LEN;
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HAL_RX_UNIFORM_HDR_SET(link_desc_va, OWNER, UNI_DESC_OWNER_SW);
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HAL_RX_UNIFORM_HDR_SET(link_desc_va, OWNER, UNI_DESC_OWNER_SW);
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@@ -1048,8 +1046,7 @@ dp_rx_defrag_nwifi_to_8023(struct dp_soc *soc,
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UNI_DESC_BUF_TYPE_RX_MSDU_LINK);
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UNI_DESC_BUF_TYPE_RX_MSDU_LINK);
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/* msdu reconfig */
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/* msdu reconfig */
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msdu_desc_info = (uint8_t *)msdu0 +
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msdu_desc_info = hal_rx_msdu_desc_info_ptr_get(soc->hal_soc, msdu0);
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RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET;
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dst_ind = hal_rx_msdu_reo_dst_ind_get(soc->hal_soc, link_desc_va);
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dst_ind = hal_rx_msdu_reo_dst_ind_get(soc->hal_soc, link_desc_va);
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@@ -1121,11 +1118,10 @@ dp_rx_defrag_nwifi_to_8023(struct dp_soc *soc,
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buf_info.sw_cookie,
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buf_info.sw_cookie,
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HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
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HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
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/* mpdu desc info */
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/* mpdu desc info */
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ent_mpdu_desc_info = (uint8_t *)ent_ring_desc +
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ent_mpdu_desc_info = hal_ent_mpdu_desc_info(soc->hal_soc,
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RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET;
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ent_ring_desc);
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dst_mpdu_desc_info = hal_dst_mpdu_desc_info(soc->hal_soc,
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dst_mpdu_desc_info = (uint8_t *)dst_ring_desc +
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dst_ring_desc);
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REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET;
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qdf_mem_copy(ent_mpdu_desc_info, dst_mpdu_desc_info,
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qdf_mem_copy(ent_mpdu_desc_info, dst_mpdu_desc_info,
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sizeof(struct rx_mpdu_desc_info));
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sizeof(struct rx_mpdu_desc_info));
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@@ -411,6 +411,10 @@ struct hal_hw_txrx_ops {
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uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *hw_desc_addr);
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uint32_t (*hal_rx_hw_desc_get_ppduid_get)(void *hw_desc_addr);
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uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
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uint32_t (*hal_rx_mpdu_start_mpdu_qos_control_valid_get)(uint8_t *buf);
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uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
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uint32_t (*hal_rx_msdu_end_sa_sw_peer_id_get)(uint8_t *buf);
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void * (*hal_rx_msdu0_buffer_addr_lsb)(void *link_desc_addr);
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void * (*hal_rx_msdu_desc_info_ptr_get)(void *msdu0);
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void * (*hal_ent_mpdu_desc_info)(void *hw_addr);
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void * (*hal_dst_mpdu_desc_info)(void *hw_addr);
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};
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};
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/**
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/**
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@@ -3334,4 +3334,40 @@ uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
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return QDF_STATUS_E_INVAL;
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return QDF_STATUS_E_INVAL;
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}
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}
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static inline
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void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl,
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void *link_desc_addr)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr);
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}
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static inline
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void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl,
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void *msdu_addr)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr);
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}
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static inline
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void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
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void *hw_addr)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr);
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}
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static inline
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void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
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void *hw_addr)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr);
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}
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#endif /* _HAL_RX_H */
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#endif /* _HAL_RX_H */
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@@ -758,6 +758,30 @@ void hal_tx_desc_set_mesh_en_6290(void *desc, uint8_t en)
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HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
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HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
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HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
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HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
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}
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}
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static
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void *hal_rx_msdu0_buffer_addr_lsb_6290(void *link_desc_va)
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{
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return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
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}
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static
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void *hal_rx_msdu_desc_info_ptr_get_6290(void *msdu0)
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{
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return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
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}
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static
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void *hal_ent_mpdu_desc_info_6290(void *ent_ring_desc)
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{
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return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
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}
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static
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void *hal_dst_mpdu_desc_info_6290(void *dst_ring_desc)
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{
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return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
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}
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struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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hal_srng_dst_hw_init_generic,
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@@ -825,6 +849,10 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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hal_rx_hw_desc_get_ppduid_get_6290,
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hal_rx_hw_desc_get_ppduid_get_6290,
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hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290,
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hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290,
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hal_rx_msdu_end_sa_sw_peer_id_get_6290,
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hal_rx_msdu_end_sa_sw_peer_id_get_6290,
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hal_rx_msdu0_buffer_addr_lsb_6290,
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hal_rx_msdu_desc_info_ptr_get_6290,
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hal_ent_mpdu_desc_info_6290,
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hal_dst_mpdu_desc_info_6290,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6290[] = {
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struct hal_hw_srng_config hw_srng_table_6290[] = {
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@@ -233,6 +233,22 @@
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RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
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RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
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RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
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RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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(uint8_t *)(link_desc_va) + \
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RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
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#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
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(uint8_t *)(msdu0) + \
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RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
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#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
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(uint8_t *)(ent_ring_desc) + \
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RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
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#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
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(uint8_t *)(dst_ring_desc) + \
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REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
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#if defined(QCA_WIFI_QCA6290_11AX)
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#if defined(QCA_WIFI_QCA6290_11AX)
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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@@ -757,6 +757,30 @@ void hal_tx_desc_set_mesh_en_6390(void *desc, uint8_t en)
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HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
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HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
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}
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}
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static
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void *hal_rx_msdu0_buffer_addr_lsb_6390(void *link_desc_va)
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{
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return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
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}
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static
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void *hal_rx_msdu_desc_info_ptr_get_6390(void *msdu0)
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{
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return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
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}
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static
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void *hal_ent_mpdu_desc_info_6390(void *ent_ring_desc)
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{
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return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
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}
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static
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void *hal_dst_mpdu_desc_info_6390(void *dst_ring_desc)
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{
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return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
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}
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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hal_srng_dst_hw_init_generic,
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@@ -824,6 +848,10 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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hal_rx_hw_desc_get_ppduid_get_6390,
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hal_rx_hw_desc_get_ppduid_get_6390,
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hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390,
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hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390,
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hal_rx_msdu_end_sa_sw_peer_id_get_6390,
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hal_rx_msdu_end_sa_sw_peer_id_get_6390,
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hal_rx_msdu0_buffer_addr_lsb_6390,
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hal_rx_msdu_desc_info_ptr_get_6390,
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hal_ent_mpdu_desc_info_6390,
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hal_dst_mpdu_desc_info_6390,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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@@ -239,6 +239,22 @@
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RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
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RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
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RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
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RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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(uint8_t *)(link_desc_va) + \
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RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
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#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
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(uint8_t *)(msdu0) + \
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RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
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#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
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(uint8_t *)(ent_ring_desc) + \
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RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
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#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
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(uint8_t *)(dst_ring_desc) + \
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REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
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/*
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/*
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* hal_rx_msdu_start_nss_get_6390(): API to get the NSS
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* hal_rx_msdu_start_nss_get_6390(): API to get the NSS
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* Interval from rx_msdu_start
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* Interval from rx_msdu_start
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@@ -629,6 +629,30 @@ void hal_tx_desc_set_mesh_en_6490(void *desc, uint8_t en)
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HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
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HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
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}
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}
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static
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void *hal_rx_msdu0_buffer_addr_lsb_6490(void *link_desc_va)
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{
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return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
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}
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static
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void *hal_rx_msdu_desc_info_ptr_get_6490(void *msdu0)
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{
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return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
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}
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static
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void *hal_ent_mpdu_desc_info_6490(void *ent_ring_desc)
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{
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return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
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}
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static
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void *hal_dst_mpdu_desc_info_6490(void *dst_ring_desc)
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{
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return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
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}
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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/* tx */
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/* tx */
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hal_tx_desc_set_mesh_en_6490,
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hal_tx_desc_set_mesh_en_6490,
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@@ -658,4 +682,8 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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hal_rx_hw_desc_get_ppduid_get_6490,
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hal_rx_hw_desc_get_ppduid_get_6490,
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NULL,
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NULL,
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NULL,
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NULL,
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hal_rx_msdu0_buffer_addr_lsb_6490,
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hal_rx_msdu_desc_info_ptr_get_6490,
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hal_ent_mpdu_desc_info_6490,
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hal_dst_mpdu_desc_info_6490,
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};
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};
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@@ -213,3 +213,19 @@
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RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \
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RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \
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RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \
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RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \
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RX_MSDU_END_14_SA_SW_PEER_ID_LSB))
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RX_MSDU_END_14_SA_SW_PEER_ID_LSB))
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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(uint8_t *)(link_desc_va) + \
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RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
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||||||
|
#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
|
||||||
|
(uint8_t *)(msdu0) + \
|
||||||
|
RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
|
||||||
|
|
||||||
|
#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
|
||||||
|
(uint8_t *)(ent_ring_desc) + \
|
||||||
|
RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET
|
||||||
|
|
||||||
|
#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
|
||||||
|
(uint8_t *)(dst_ring_desc) + \
|
||||||
|
REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
|
||||||
|
@@ -755,6 +755,30 @@ void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en)
|
|||||||
HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
|
HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va)
|
||||||
|
{
|
||||||
|
return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0)
|
||||||
|
{
|
||||||
|
return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc)
|
||||||
|
{
|
||||||
|
return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc)
|
||||||
|
{
|
||||||
|
return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
|
||||||
|
}
|
||||||
|
|
||||||
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
|
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
|
||||||
|
|
||||||
/* init and setup */
|
/* init and setup */
|
||||||
@@ -823,6 +847,10 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
|
|||||||
hal_rx_hw_desc_get_ppduid_get_8074v1,
|
hal_rx_hw_desc_get_ppduid_get_8074v1,
|
||||||
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1,
|
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1,
|
||||||
hal_rx_msdu_end_sa_sw_peer_id_get_8074v1,
|
hal_rx_msdu_end_sa_sw_peer_id_get_8074v1,
|
||||||
|
hal_rx_msdu0_buffer_addr_lsb_8074v1,
|
||||||
|
hal_rx_msdu_desc_info_ptr_get_8074v1,
|
||||||
|
hal_ent_mpdu_desc_info_8074v1,
|
||||||
|
hal_dst_mpdu_desc_info_8074v1,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_hw_srng_config hw_srng_table_8074[] = {
|
struct hal_hw_srng_config hw_srng_table_8074[] = {
|
||||||
|
@@ -221,6 +221,23 @@
|
|||||||
RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \
|
RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \
|
||||||
RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
|
RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
|
||||||
RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
|
RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
|
||||||
|
|
||||||
|
#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
|
||||||
|
(uint8_t *)(link_desc_va) + \
|
||||||
|
RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
|
||||||
|
|
||||||
|
#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
|
||||||
|
(uint8_t *)(msdu0) + \
|
||||||
|
RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
|
||||||
|
|
||||||
|
#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
|
||||||
|
(uint8_t *)(ent_ring_desc) + \
|
||||||
|
RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
|
||||||
|
|
||||||
|
#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
|
||||||
|
(uint8_t *)(dst_ring_desc) + \
|
||||||
|
REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* hal_rx_msdu_start_nss_get_8074(): API to get the NSS
|
* hal_rx_msdu_start_nss_get_8074(): API to get the NSS
|
||||||
* Interval from rx_msdu_start
|
* Interval from rx_msdu_start
|
||||||
|
@@ -752,6 +752,30 @@ void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en)
|
|||||||
HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
|
HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va)
|
||||||
|
{
|
||||||
|
return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0)
|
||||||
|
{
|
||||||
|
return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc)
|
||||||
|
{
|
||||||
|
return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc)
|
||||||
|
{
|
||||||
|
return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
|
||||||
|
}
|
||||||
|
|
||||||
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
|
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
|
||||||
|
|
||||||
/* init and setup */
|
/* init and setup */
|
||||||
@@ -821,6 +845,10 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
|
|||||||
hal_rx_hw_desc_get_ppduid_get_8074v2,
|
hal_rx_hw_desc_get_ppduid_get_8074v2,
|
||||||
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2,
|
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2,
|
||||||
hal_rx_msdu_end_sa_sw_peer_id_get_8074v2,
|
hal_rx_msdu_end_sa_sw_peer_id_get_8074v2,
|
||||||
|
hal_rx_msdu0_buffer_addr_lsb_8074v2,
|
||||||
|
hal_rx_msdu_desc_info_ptr_get_8074v2,
|
||||||
|
hal_ent_mpdu_desc_info_8074v2,
|
||||||
|
hal_dst_mpdu_desc_info_8074v2,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_hw_srng_config hw_srng_table_8074v2[] = {
|
struct hal_hw_srng_config hw_srng_table_8074v2[] = {
|
||||||
|
@@ -231,6 +231,22 @@
|
|||||||
RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
|
RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
|
||||||
RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
|
RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
|
||||||
|
|
||||||
|
#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
|
||||||
|
(uint8_t *)(link_desc_va) + \
|
||||||
|
RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
|
||||||
|
|
||||||
|
#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
|
||||||
|
(uint8_t *)(msdu0) + \
|
||||||
|
RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
|
||||||
|
|
||||||
|
#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
|
||||||
|
(uint8_t *)(ent_ring_desc) + \
|
||||||
|
RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
|
||||||
|
|
||||||
|
#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
|
||||||
|
(uint8_t *)(dst_ring_desc) + \
|
||||||
|
REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS
|
* hal_rx_msdu_start_nss_get_8074v2(): API to get the NSS
|
||||||
* Interval from rx_msdu_start
|
* Interval from rx_msdu_start
|
||||||
|
@@ -761,6 +761,30 @@ void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en)
|
|||||||
HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
|
HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va)
|
||||||
|
{
|
||||||
|
return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0)
|
||||||
|
{
|
||||||
|
return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc)
|
||||||
|
{
|
||||||
|
return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static
|
||||||
|
void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc)
|
||||||
|
{
|
||||||
|
return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
|
||||||
|
}
|
||||||
|
|
||||||
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
|
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
|
||||||
|
|
||||||
/* init and setup */
|
/* init and setup */
|
||||||
@@ -830,6 +854,10 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
|
|||||||
hal_rx_hw_desc_get_ppduid_get_9000,
|
hal_rx_hw_desc_get_ppduid_get_9000,
|
||||||
hal_rx_mpdu_start_mpdu_qos_control_valid_9000,
|
hal_rx_mpdu_start_mpdu_qos_control_valid_9000,
|
||||||
hal_rx_msdu_end_sa_sw_peer_id_get_9000,
|
hal_rx_msdu_end_sa_sw_peer_id_get_9000,
|
||||||
|
hal_rx_msdu0_buffer_addr_lsb_9000,
|
||||||
|
hal_rx_msdu_desc_info_ptr_get_9000,
|
||||||
|
hal_ent_mpdu_desc_info_9000,
|
||||||
|
hal_dst_mpdu_desc_info_9000,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_hw_srng_config hw_srng_table_9000[] = {
|
struct hal_hw_srng_config hw_srng_table_9000[] = {
|
||||||
|
Reference in New Issue
Block a user