qcacmn: Add qca8074v2 register structures
Add separate register structures for qca8074v2 chip. Change-Id: Idf2ee0559c48edfb2c1835a6244578143b47f0fa CRs-Fixed: 2292210
Этот коммит содержится в:
Venkateswara Swamy Bandaru
коммит произвёл
nshrivas
nshrivas
родитель
452feb46d4
Коммит
8223158f81
239
hif/src/qca8074v2def.c
Обычный файл
239
hif/src/qca8074v2def.c
Обычный файл
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/*
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* Copyright (c) 2018 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "qdf_module.h"
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#if defined(QCA8074V2_HEADERS_DEF)
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#undef UMAC
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#define WLAN_HEADERS 1
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#include "wcss_version.h"
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#include "wcss_seq_hwiobase.h"
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#include "wfss_ce_reg_seq_hwioreg.h"
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#define MISSING 0
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#define SOC_RESET_CONTROL_OFFSET MISSING
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#define GPIO_PIN0_OFFSET MISSING
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#define GPIO_PIN1_OFFSET MISSING
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#define GPIO_PIN0_CONFIG_MASK MISSING
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#define GPIO_PIN1_CONFIG_MASK MISSING
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#define LOCAL_SCRATCH_OFFSET 0x18
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#define GPIO_PIN10_OFFSET MISSING
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#define GPIO_PIN11_OFFSET MISSING
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#define GPIO_PIN12_OFFSET MISSING
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#define GPIO_PIN13_OFFSET MISSING
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#define MBOX_BASE_ADDRESS MISSING
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#define INT_STATUS_ENABLE_ERROR_LSB MISSING
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#define INT_STATUS_ENABLE_ERROR_MASK MISSING
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#define INT_STATUS_ENABLE_CPU_LSB MISSING
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#define INT_STATUS_ENABLE_CPU_MASK MISSING
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#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
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#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
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#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
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#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
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#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
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#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
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#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
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#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
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#define INT_STATUS_ENABLE_ADDRESS MISSING
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#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
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#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
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#define HOST_INT_STATUS_ADDRESS MISSING
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#define CPU_INT_STATUS_ADDRESS MISSING
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#define ERROR_INT_STATUS_ADDRESS MISSING
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#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
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#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
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#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
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#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
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#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
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#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
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#define COUNT_DEC_ADDRESS MISSING
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#define HOST_INT_STATUS_CPU_MASK MISSING
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#define HOST_INT_STATUS_CPU_LSB MISSING
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#define HOST_INT_STATUS_ERROR_MASK MISSING
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#define HOST_INT_STATUS_ERROR_LSB MISSING
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#define HOST_INT_STATUS_COUNTER_MASK MISSING
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#define HOST_INT_STATUS_COUNTER_LSB MISSING
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#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
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#define WINDOW_DATA_ADDRESS MISSING
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#define WINDOW_READ_ADDR_ADDRESS MISSING
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#define WINDOW_WRITE_ADDR_ADDRESS MISSING
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/* GPIO Register */
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#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
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#define GPIO_PIN0_CONFIG_LSB MISSING
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#define GPIO_PIN0_PAD_PULL_LSB MISSING
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#define GPIO_PIN0_PAD_PULL_MASK MISSING
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/* SI reg */
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#define SI_CONFIG_ERR_INT_MASK MISSING
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#define SI_CONFIG_ERR_INT_LSB MISSING
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#define RTC_SOC_BASE_ADDRESS MISSING
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#define RTC_WMAC_BASE_ADDRESS MISSING
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#define SOC_CORE_BASE_ADDRESS MISSING
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#define WLAN_MAC_BASE_ADDRESS MISSING
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#define GPIO_BASE_ADDRESS MISSING
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#define ANALOG_INTF_BASE_ADDRESS MISSING
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#define CE0_BASE_ADDRESS MISSING
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#define CE1_BASE_ADDRESS MISSING
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#define CE_COUNT 12
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#define CE_WRAPPER_BASE_ADDRESS MISSING
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#define SI_BASE_ADDRESS MISSING
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#define DRAM_BASE_ADDRESS MISSING
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#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
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#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
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#define CLOCK_CONTROL_OFFSET MISSING
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#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
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#define RESET_CONTROL_SI0_RST_MASK MISSING
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#define WLAN_RESET_CONTROL_OFFSET MISSING
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#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
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#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
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#define CPU_CLOCK_OFFSET MISSING
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#define CPU_CLOCK_STANDARD_LSB MISSING
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#define CPU_CLOCK_STANDARD_MASK MISSING
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#define LPO_CAL_ENABLE_LSB MISSING
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#define LPO_CAL_ENABLE_MASK MISSING
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#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
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#define SOC_CHIP_ID_ADDRESS MISSING
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#define SOC_CHIP_ID_REVISION_MASK MISSING
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#define SOC_CHIP_ID_REVISION_LSB MISSING
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#define SOC_CHIP_ID_REVISION_MSB MISSING
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#define FW_IND_EVENT_PENDING MISSING
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#define FW_IND_INITIALIZED MISSING
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
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#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
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#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
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#define SR_WR_INDEX_ADDRESS MISSING
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#define DST_WATERMARK_ADDRESS MISSING
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#define DST_WR_INDEX_ADDRESS MISSING
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#define SRC_WATERMARK_ADDRESS MISSING
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#define SRC_WATERMARK_LOW_MASK MISSING
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#define SRC_WATERMARK_HIGH_MASK MISSING
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#define DST_WATERMARK_LOW_MASK MISSING
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#define DST_WATERMARK_HIGH_MASK MISSING
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#define CURRENT_SRRI_ADDRESS MISSING
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#define CURRENT_DRRI_ADDRESS MISSING
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#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
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#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
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#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
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#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
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#define HOST_IS_ADDRESS MISSING
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#define MISC_IS_ADDRESS MISSING
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#define HOST_IS_COPY_COMPLETE_MASK MISSING
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#define CE_WRAPPER_BASE_ADDRESS MISSING
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#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
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#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
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#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
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#if defined(WCSS_VERSION) && (WCSS_VERSION > 68)
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#define HOST_IE_ADDRESS \
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HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET)
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#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
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#define HOST_IE_ADDRESS_2 \
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HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET)
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#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
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#define HOST_IE_ADDRESS_3 \
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HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET)
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#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
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#else
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#define HOST_IE_ADDRESS UMAC_CE_COMMON_CE_HOST_IE_0
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#define HOST_IE_ADDRESS_2 UMAC_CE_COMMON_CE_HOST_IE_1
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#endif
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#define HOST_IE_COPY_COMPLETE_MASK MISSING
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#define SR_BA_ADDRESS MISSING
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#define SR_BA_ADDRESS_HIGH MISSING
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#define SR_SIZE_ADDRESS MISSING
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#define CE_CTRL1_ADDRESS MISSING
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#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
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#define DR_BA_ADDRESS MISSING
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#define DR_BA_ADDRESS_HIGH MISSING
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#define DR_SIZE_ADDRESS MISSING
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#define CE_CMD_REGISTER MISSING
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#define CE_MSI_ADDRESS MISSING
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#define CE_MSI_ADDRESS_HIGH MISSING
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#define CE_MSI_DATA MISSING
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#define CE_MSI_ENABLE_BIT MISSING
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#define MISC_IE_ADDRESS MISSING
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#define MISC_IS_AXI_ERR_MASK MISSING
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#define MISC_IS_DST_ADDR_ERR_MASK MISSING
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#define MISC_IS_SRC_LEN_ERR_MASK MISSING
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#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
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#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
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#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
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#define SRC_WATERMARK_LOW_LSB MISSING
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#define SRC_WATERMARK_HIGH_LSB MISSING
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#define DST_WATERMARK_LOW_LSB MISSING
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#define DST_WATERMARK_HIGH_LSB MISSING
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
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#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
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#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
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#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
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#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
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#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
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#define CE_WRAPPER_DEBUG_OFFSET MISSING
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#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
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#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
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#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
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#define CE_DEBUG_OFFSET MISSING
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#define CE_DEBUG_SEL_MSB MISSING
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#define CE_DEBUG_SEL_LSB MISSING
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#define CE_DEBUG_SEL_MASK MISSING
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#define CE0_BASE_ADDRESS MISSING
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#define CE1_BASE_ADDRESS MISSING
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#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
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#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
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#define QCA8074V2_BOARD_DATA_SZ MISSING
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#define QCA8074V2_BOARD_EXT_DATA_SZ MISSING
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#define MY_TARGET_DEF QCA8074V2_TARGETDEF
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#define MY_HOST_DEF QCA8074V2_HOSTDEF
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#define MY_CEREG_DEF QCA8074V2_CE_TARGETDEF
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#define MY_TARGET_BOARD_DATA_SZ QCA8074V2_BOARD_DATA_SZ
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#define MY_TARGET_BOARD_EXT_DATA_SZ QCA8074V2_BOARD_EXT_DATA_SZ
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#include "targetdef.h"
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#include "hostdef.h"
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qdf_export_symbol(QCA8074V2_CE_TARGETDEF);
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#else
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#include "common_drv.h"
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#include "targetdef.h"
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#include "hostdef.h"
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struct targetdef_s *QCA8074V2_TARGETDEF;
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struct hostdef_s *QCA8074V2_HOSTDEF;
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#endif /*QCA8074V2_HEADERS_DEF */
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qdf_export_symbol(QCA8074V2_TARGETDEF);
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qdf_export_symbol(QCA8074V2_HOSTDEF);
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