samsung-sm8650/android_kernel_samsung_sm8650-modules
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qcacmn: fix batch timer/count threshold register config

Kaynağa Gözat 
Fix the SRC/DST batch timer/count threshold register configurations.

Change-Id: I356fe72e6a2044a12c9e772ed043f2ee286d36c6
CRs-Fixed: 3483043
Bu işleme şunda yer alıyor:
Venkateswara Naralasetty
2023-04-27 20:46:37 +05:30
işlemeyi yapan: Madan Koyyalamudi
ebeveyn 3b082b0bf8
işleme 81f874fc13
1 değiştirilmiş dosya ile 12 ekleme ve 16 silme
Yama Dosyasını İndir Diff Dosyasını İndir Tüm dosyaları genişlet Tüm dosyaları daralt

28
hif/src/ce/ce_service_legacy.c
Dosyayı Görüntüle

@@ -1307,17 +1307,15 @@ static void ce_legacy_src_intr_thres_setup(struct hif_softc *scn,
tmp = CE_CHANNEL_SRC_BATCH_TIMER_INT_SETUP_GET(scn, ctrl_addr);
if (count_thrs) {
tmp &= ~(CE_SRC_BATCH_COUNTER_THRESH_MASK <<
CE_SRC_BATCH_COUNTER_THRESH_LSB);
tmp |= ((count_thrs & CE_SRC_BATCH_COUNTER_THRESH_MASK) <<
CE_SRC_BATCH_COUNTER_THRESH_LSB);
tmp &= ~CE_SRC_BATCH_COUNTER_THRESH_MASK;
tmp |= ((count_thrs << CE_SRC_BATCH_COUNTER_THRESH_LSB) &
CE_SRC_BATCH_COUNTER_THRESH_MASK);
}
if (timer_thrs) {
tmp &= ~(CE_SRC_BATCH_TIMER_THRESH_MASK <<
CE_SRC_BATCH_TIMER_THRESH_LSB);
tmp |= ((timer_thrs & CE_SRC_BATCH_TIMER_THRESH_MASK) <<
CE_SRC_BATCH_TIMER_THRESH_LSB);
tmp &= ~CE_SRC_BATCH_TIMER_THRESH_MASK;
tmp |= ((timer_thrs << CE_SRC_BATCH_TIMER_THRESH_LSB) &
CE_SRC_BATCH_TIMER_THRESH_MASK);
}
CE_CHANNEL_SRC_BATCH_TIMER_INT_SETUP(scn, ctrl_addr, tmp);
@@ -1335,17 +1333,15 @@ static void ce_legacy_dest_intr_thres_setup(struct hif_softc *scn,
tmp = CE_CHANNEL_DST_BATCH_TIMER_INT_SETUP_GET(scn, ctrl_addr);
if (count_thrs) {
tmp &= ~(CE_DST_BATCH_COUNTER_THRESH_MASK <<
CE_DST_BATCH_COUNTER_THRESH_LSB);
tmp |= ((count_thrs & CE_DST_BATCH_COUNTER_THRESH_MASK) <<
CE_DST_BATCH_COUNTER_THRESH_LSB);
tmp &= ~CE_DST_BATCH_COUNTER_THRESH_MASK;
tmp |= ((count_thrs << CE_DST_BATCH_COUNTER_THRESH_LSB) &
CE_DST_BATCH_COUNTER_THRESH_MASK);
}
if (timer_thrs) {
tmp &= ~(CE_DST_BATCH_TIMER_THRESH_MASK <<
CE_DST_BATCH_TIMER_THRESH_LSB);
tmp |= ((timer_thrs & CE_DST_BATCH_TIMER_THRESH_MASK) <<
CE_DST_BATCH_TIMER_THRESH_LSB);
tmp &= ~CE_DST_BATCH_TIMER_THRESH_MASK;
tmp |= ((timer_thrs << CE_DST_BATCH_TIMER_THRESH_LSB) &
CE_DST_BATCH_TIMER_THRESH_MASK);
}
CE_CHANNEL_DST_BATCH_TIMER_INT_SETUP(scn, ctrl_addr, tmp);