qcacmn: Add sg formation check
Add check for sg formation. Only enable chfrag_cont and msdu_continuation if reo error code is HAL_RX_WBM_ERR_SRC_REO or rxdma_err_code is HAL_RXDMA_ERR_UNENCRYPTED. Also chain all nbuf in case of sg in separate buffer and finally loop through that. This is added because sometime we dont get desc in sync with hw. To avoid such mismatch, this buffer is added. We will process nbuf only when all msdus has been received. Change-Id: I3b154a68955db61f3acaa0cb8d130c8918a3d450 CRs-Fixed: 2672126
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@@ -690,6 +690,19 @@ void dp_2k_jump_handle(struct dp_soc *soc, qdf_nbuf_t nbuf, uint8_t *rx_tlv_hdr,
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qdf_nbuf_set_next((tail), NULL); \
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} while (0)
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#define DP_RX_MERGE_TWO_LIST(phead, ptail, chead, ctail) \
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do { \
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if (!(phead)) { \
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(phead) = (chead); \
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} else { \
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qdf_nbuf_set_next((ptail), (chead)); \
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QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(phead) += \
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QDF_NBUF_CB_RX_NUM_ELEMENTS_IN_LIST(chead); \
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} \
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(ptail) = (ctail); \
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qdf_nbuf_set_next((ptail), NULL); \
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} while (0)
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/*for qcn9000 emulation the pcie is complete phy and no address restrictions*/
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#if !defined(BUILD_X86) || defined(QCA_WIFI_QCN9000)
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static inline int check_x86_paddr(struct dp_soc *dp_soc, qdf_nbuf_t *rx_netbuf,
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@@ -1238,7 +1251,37 @@ dp_rx_srng_access_end(struct dp_intr *int_ctx, struct dp_soc *soc,
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{
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dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
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}
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#endif
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/*
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* dp_rx_wbm_sg_list_reset() - Initialize sg list
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*
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* This api should be called at soc init and afterevery sg processing.
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*@soc: DP SOC handle
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*/
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static inline void dp_rx_wbm_sg_list_reset(struct dp_soc *soc)
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{
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if (soc) {
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soc->wbm_sg_param.wbm_is_first_msdu_in_sg = false;
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soc->wbm_sg_param.wbm_sg_nbuf_head = NULL;
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soc->wbm_sg_param.wbm_sg_nbuf_tail = NULL;
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soc->wbm_sg_param.wbm_sg_desc_msdu_len = 0;
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}
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}
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/*
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* dp_rx_wbm_sg_list_deinit() - De-initialize sg list
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*
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* This api should be called in down path, to avoid any leak.
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*@soc: DP SOC handle
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*/
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static inline void dp_rx_wbm_sg_list_deinit(struct dp_soc *soc)
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{
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if (soc) {
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if (soc->wbm_sg_param.wbm_sg_nbuf_head)
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qdf_nbuf_list_free(soc->wbm_sg_param.wbm_sg_nbuf_head);
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dp_rx_wbm_sg_list_reset(soc);
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}
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}
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#endif /* _DP_RX_H */
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