disp: msm: sde: check fetch active registers for active data planes
Continuous splash setup checks the CTL configuration to determine and log all planes that have been enabled for continuous splash boot. This logic currently only checks the planes mapped to each LM on a given control path, resulting in data planes being missed. Update the boot plane enumeration logic to additionally check the CTL fetch active registers to detect and log missed planes. This logic checks against all planes found through the original enumeration path to avoid logging the same plane twice. Note that planes found via the fetch registers are assumed to be used across both rectangles due to hardware logging limitations. Change-Id: Ic1f4aaba94111fe096ba9764eeaef242beb6adf5 Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
This commit is contained in:

committed by
Gopikrishnaiah Anandan

parent
db39b61a5f
commit
812782e76b
@@ -1857,6 +1857,60 @@ static int _sde_rm_make_next_rsvp(struct sde_rm *rm, struct drm_encoder *enc,
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return ret;
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}
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static int _sde_rm_update_pipe_cnt_from_active(
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struct sde_splash_display *splash_display,
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u32 active_pipes_mask)
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{
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int i;
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u32 sspp_present = 0, space_remain = 0;
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if (!active_pipes_mask) {
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return 0;
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} else if (!splash_display) {
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SDE_ERROR("invalid splash display provided\n");
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return -EINVAL;
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} else if (splash_display->pipe_cnt >=
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ARRAY_SIZE(splash_display->pipes)) {
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SDE_ERROR("no room to add active pipes to pipe array\n");
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return -EINVAL;
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}
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for (i = 0; i < splash_display->pipe_cnt; i++)
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sspp_present |= BIT(splash_display->pipes[i].sspp);
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space_remain = ARRAY_SIZE(splash_display->pipes)
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- splash_display->pipe_cnt;
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for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
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/* Skip planes already present in the array */
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if (!(active_pipes_mask & BIT(i)) ||
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(sspp_present & BIT(i)))
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continue;
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if (space_remain < R_MAX) {
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SDE_ERROR("not enough room to add active pipe %d", i);
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return -EINVAL;
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}
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/*
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* A plane in active but not sspp_present indicates a non-pixel
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* plane. Register both rectangles as we can't differentiate
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*/
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splash_display->pipes[splash_display->pipe_cnt].sspp = i;
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splash_display->pipes[splash_display->pipe_cnt].is_virtual =
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false;
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splash_display->pipe_cnt++;
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space_remain--;
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splash_display->pipes[splash_display->pipe_cnt].sspp = i;
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splash_display->pipes[splash_display->pipe_cnt].is_virtual =
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true;
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splash_display->pipe_cnt++;
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space_remain--;
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}
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return 0;
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}
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/**
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* _sde_rm_get_hw_blk_for_cont_splash - retrieve the LM blocks on given CTL
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* and populate the connected HW blk ids in sde_splash_display
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@@ -1869,9 +1923,10 @@ static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
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struct sde_hw_ctl *ctl,
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struct sde_splash_display *splash_display)
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{
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u32 lm_reg;
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u32 lm_reg, max_cnt, active_pipes_mask = 0;
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struct sde_rm_hw_iter iter_lm, iter_dsc;
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struct sde_kms *sde_kms;
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size_t start_count;
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if (!rm || !ctl || !splash_display) {
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SDE_ERROR("invalid input parameters\n");
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@@ -1879,6 +1934,7 @@ static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
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}
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sde_kms = container_of(rm, struct sde_kms, rm);
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max_cnt = ARRAY_SIZE(splash_display->pipes);
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sde_rm_init_hw_iter(&iter_lm, 0, SDE_HW_BLK_LM);
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sde_rm_init_hw_iter(&iter_dsc, 0, SDE_HW_BLK_DSC);
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@@ -1895,24 +1951,41 @@ static int _sde_rm_get_hw_blk_for_cont_splash(struct sde_rm *rm,
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SDE_DEBUG("lm_cnt=%d lm_reg[%d]=0x%x\n", splash_display->lm_cnt,
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iter_lm.blk->id - LM_0, lm_reg);
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if (ctl->ops.get_staged_sspp &&
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ctl->ops.get_staged_sspp(ctl, iter_lm.blk->id,
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&splash_display->pipes[
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splash_display->pipe_cnt], 1)) {
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splash_display->pipe_cnt++;
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} else if (sde_kms->splash_data.type == SDE_VM_HANDOFF) {
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start_count = splash_display->pipe_cnt;
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if (ctl->ops.get_staged_sspp) {
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struct sde_sspp_index_info *start =
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&splash_display->pipes[
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splash_display->pipe_cnt];
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splash_display->pipe_cnt += ctl->ops.get_staged_sspp(
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ctl, iter_lm.blk->id, start,
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max_cnt - splash_display->pipe_cnt);
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}
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if (sde_kms->splash_data.type == SDE_VM_HANDOFF) {
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/* Allow VM handoff without any pipes, as it is a
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* valid case to have NULL commit before the
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* transition.
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*/
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SDE_DEBUG("VM handoff with no pipes staged\n");
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} else {
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SDE_ERROR("no pipe detected on LM-%d\n",
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} else if (start_count == splash_display->pipe_cnt) {
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SDE_ERROR("no pipes detected on LM-%d\n",
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iter_lm.blk->id - LM_0);
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return 0;
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} else if (splash_display->pipe_cnt > max_cnt) {
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SDE_ERROR("found %d pipes exceed max of %d\n",
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splash_display->pipe_cnt, max_cnt);
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return 0;
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}
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}
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if (ctl->ops.get_active_pipes)
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active_pipes_mask = ctl->ops.get_active_pipes(ctl);
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if (_sde_rm_update_pipe_cnt_from_active(splash_display,
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active_pipes_mask))
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return 0;
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while (_sde_rm_get_hw_locked(rm, &iter_dsc)) {
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if (ctl->ops.read_active_status &&
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!(ctl->ops.read_active_status(ctl,
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