Merge "msm: camera: cpas: Add support for verifying test irq" into camera-kernel.lnx.6.0

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -545,10 +545,73 @@ static int cam_cpastop_handle_ahb_timeout_err(struct cam_hw_info *cpas_hw,
 	return 0;
 }
 
+#if (defined(CONFIG_CAM_TEST_IRQ_LINE) && defined(CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE))
+static int cam_cpastop_enable_test_irq(struct cam_hw_info *cpas_hw)
+{
+	int i;
+
+	camnoc_info->irq_sbm->sbm_enable.value |= camnoc_info->test_irq_info.sbm_enable_mask;
+	camnoc_info->irq_sbm->sbm_clear.value |= camnoc_info->test_irq_info.sbm_clear_mask;
+
+	for (i = 0; i < camnoc_info->irq_err_size; i++) {
+		if (camnoc_info->irq_err[i].irq_type == CAM_CAMNOC_HW_IRQ_CAMNOC_TEST)
+			camnoc_info->irq_err[i].enable = true;
+	}
+
+	return 0;
+}
+
+static int cam_cpastop_disable_test_irq(struct cam_hw_info *cpas_hw)
+{
+	int i;
+
+	camnoc_info->irq_sbm->sbm_enable.value &= ~camnoc_info->test_irq_info.sbm_enable_mask;
+	camnoc_info->irq_sbm->sbm_clear.value &= ~camnoc_info->test_irq_info.sbm_clear_mask;
+
+	for (i = 0; i < camnoc_info->irq_err_size; i++) {
+		if (camnoc_info->irq_err[i].irq_type == CAM_CAMNOC_HW_IRQ_CAMNOC_TEST)
+			camnoc_info->irq_err[i].enable = false;
+	}
+
+	return 0;
+}
+
+static void cam_cpastop_check_test_irq(struct cam_hw_info *cpas_hw, uint32_t irq_status)
+{
+	int i;
+
+	for (i = 0; i < camnoc_info->irq_err_size; i++) {
+		if ((camnoc_info->irq_err[i].irq_type == CAM_CAMNOC_HW_IRQ_CAMNOC_TEST) &&
+			(irq_status & camnoc_info->irq_err[i].sbm_port)) {
+			CAM_INFO(CAM_CPAS, "CAMNOC Test IRQ triggerred");
+			complete(&cpas_hw->hw_complete);
+		}
+	}
+}
+#endif
+
 static int cam_cpastop_reset_irq(struct cam_hw_info *cpas_hw)
 {
 	int i;
 
+#if (defined(CONFIG_CAM_TEST_IRQ_LINE) && defined(CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE))
+	static int counter;
+	bool wait_for_irq = false;
+	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
+
+	if (counter == 0)  {
+		CAM_INFO(CAM_CPAS, "Enabling camnoc test irq");
+		cam_cpastop_enable_test_irq(cpas_hw);
+		wait_for_irq = true;
+		reinit_completion(&cpas_hw->hw_complete);
+		counter = 1;
+	} else if (counter == 1) {
+		CAM_INFO(CAM_CPAS, "Disabling camnoc test irq");
+		cam_cpastop_disable_test_irq(cpas_hw);
+		counter = 2;
+	}
+#endif
+
 	if (camnoc_info->irq_sbm->sbm_enable.enable == false)
 		return 0;
 
@@ -568,6 +631,14 @@ static int cam_cpastop_reset_irq(struct cam_hw_info *cpas_hw)
 				&camnoc_info->irq_err[i].err_enable);
 	}
 
+#if (defined(CONFIG_CAM_TEST_IRQ_LINE) && defined(CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE))
+	if (wait_for_irq) {
+		if (!cam_common_wait_for_completion_timeout(&cpas_hw->hw_complete,
+			msecs_to_jiffies(2000)))
+			CAM_ERR(CAM_CPAS, "CAMNOC Test IRQ line verification timed out");
+	}
+#endif
+
 	return 0;
 }
 
@@ -714,6 +785,10 @@ static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data)
 
 	CAM_DBG(CAM_CPAS, "IRQ callback, irq_status=0x%x", payload->irq_status);
 
+#if (defined(CONFIG_CAM_TEST_IRQ_LINE) && defined(CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE))
+	cam_cpastop_check_test_irq(cpas_hw, payload->irq_status);
+#endif
+
 	payload->hw = cpas_hw;
 	INIT_WORK((struct work_struct *)&payload->work, cam_cpastop_work);
 

drivers/cam_cpas/cpas_top/cam_cpastop_hw.h

@@ -332,6 +332,18 @@ struct cam_camnoc_err_logger_info {
 	uint32_t errlog3_high;
 };
 
+/**
+ * struct cam_cpas_test_irq_info : CAMNOC Test IRQ mask information
+ *
+ * @sbm_enable_mask: sbm mask to enable camnoc test irq
+ * @sbm_clear_mask: sbm mask to clear camnoc test irq
+ *
+ */
+struct cam_cpas_test_irq_info {
+	uint32_t sbm_enable_mask;
+	uint32_t sbm_clear_mask;
+};
+
 /**
  * struct cam_camnoc_info : Overall CAMNOC settings info
  *
@@ -342,6 +354,7 @@ struct cam_camnoc_err_logger_info {
  * @irq_err_size: Array size of IRQ Error settings
  * @err_logger: Pointer to CAMNOC IRQ Error logger read registers
  * @errata_wa_list: HW Errata workaround info
+ * @test_irq_info: CAMNOC Test IRQ info
  *
  */
 struct cam_camnoc_info {
@@ -352,6 +365,7 @@ struct cam_camnoc_info {
 	int irq_err_size;
 	struct cam_camnoc_err_logger_info *err_logger;
 	struct cam_cpas_hw_errata_wa_list *errata_wa_list;
+	struct cam_cpas_test_irq_info test_irq_info;
 };
 
 /**

drivers/cam_cpas/cpas_top/cpastop_v520_100.h

@@ -6,17 +6,12 @@
 #ifndef _CPASTOP_V520_100_H_
 #define _CPASTOP_V520_100_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v520_100_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
 		.enable = true,
 		.offset = 0xA40, /* SBM_FAULTINEN0_LOW */
-		.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
-			(TEST_IRQ_ENABLE ?
-			0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
-			0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */,
+		.value = 0x1,    /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -27,7 +22,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v520_100_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x3 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -57,7 +52,7 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -252,6 +247,10 @@ static struct cam_camnoc_info cam520_cpas100_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v520_100_irq_err),
 	.err_logger = &cam520_cpas100_err_logger_offsets,
 	.errata_wa_list = NULL,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x2,
+		.sbm_clear_mask = 0x2,
+	}
 };
 
 static struct cam_cpas_camnoc_qchannel cam520_cpas100_qchannel_info = {

drivers/cam_cpas/cpas_top/cpastop_v540_100.h

@@ -6,17 +6,12 @@
 #ifndef _CPASTOP_V540_100_H_
 #define _CPASTOP_V540_100_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v540_100_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
 		.enable = true,
 		.offset = 0xA40, /* SBM_FAULTINEN0_LOW */
-		.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
-			(TEST_IRQ_ENABLE ?
-			0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
-			0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */,
+		.value = 0x1,    /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -27,7 +22,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v540_100_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x3 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -57,7 +52,7 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -253,6 +248,10 @@ static struct cam_camnoc_info cam540_cpas100_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v540_100_irq_err),
 	.err_logger = &cam540_cpas100_err_logger_offsets,
 	.errata_wa_list = NULL,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x2,
+		.sbm_clear_mask = 0x2,
+	}
 };
 
 static struct cam_cpas_camnoc_qchannel cam540_cpas100_qchannel_info = {

drivers/cam_cpas/cpas_top/cpastop_v545_100.h

@@ -6,17 +6,12 @@
 #ifndef _CPASTOP_V545_100_H_
 #define _CPASTOP_V545_100_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v545_100_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
 		.enable = true,
 		.offset = 0xA40, /* SBM_FAULTINEN0_LOW */
-		.value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
-			(TEST_IRQ_ENABLE ?
-			0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
-			0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */,
+		.value = 0x1,    /* SBM_FAULTINEN0_LOW_PORT0_MASK*/
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -27,7 +22,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v545_100_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x3 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -57,7 +52,7 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -346,6 +341,10 @@ static struct cam_camnoc_info cam545_cpas100_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v545_100_irq_err),
 	.err_logger = &cam545_cpas100_err_logger_offsets,
 	.errata_wa_list = NULL,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x2,
+		.sbm_clear_mask = 0x2,
+	}
 };
 
 static struct cam_cpas_camnoc_qchannel cam545_cpas100_qchannel_info = {

drivers/cam_cpas/cpas_top/cpastop_v570_200.h

@@ -6,8 +6,6 @@
 #ifndef _CPASTOP_V570_200_H_
 #define _CPASTOP_V570_200_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v570_200_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -17,10 +15,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v570_200_irq_sbm = {
 			0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
 			0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
 			0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
-			0x1000 | /* SBM_FAULTINEN0_LOW_PORT12_MASK */
-			(TEST_IRQ_ENABLE ?
-			0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
-			0x0),
+			0x1000, /* SBM_FAULTINEN0_LOW_PORT12_MASK */
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -31,7 +26,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v570_200_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -178,7 +173,7 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -925,6 +920,10 @@ static struct cam_camnoc_info cam570_cpas200_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v570_200_irq_err),
 	.err_logger = &cam570_cpas200_err_logger_offsets,
 	.errata_wa_list = &cam570_cpas200_errata_wa_list,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x40,
+		.sbm_clear_mask = 0x4,
+	}
 };
 
 static struct cam_cpas_camnoc_qchannel cam570_cpas200_qchannel_info = {

drivers/cam_cpas/cpas_top/cpastop_v580_100.h

@@ -6,8 +6,6 @@
 #ifndef _CPASTOP_V580_100_H_
 #define _CPASTOP_V580_100_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v580_100_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -17,10 +15,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v580_100_irq_sbm = {
 			0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
 			0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
 			0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
-			0x1000 | /* SBM_FAULTINEN0_LOW_PORT12_MASK */
-			(TEST_IRQ_ENABLE ?
-			0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
-			0x0),
+			0x1000, /* SBM_FAULTINEN0_LOW_PORT12_MASK */
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -31,7 +26,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v580_100_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -178,7 +173,7 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -1102,6 +1097,10 @@ static struct cam_camnoc_info cam580_cpas100_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v580_100_irq_err),
 	.err_logger = &cam580_cpas100_err_logger_offsets,
 	.errata_wa_list = &cam580_cpas100_errata_wa_list,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x40,
+		.sbm_clear_mask = 0x4,
+	}
 };
 
 static struct cam_cpas_camnoc_qchannel cam580_cpas100_qchannel_info = {

drivers/cam_cpas/cpas_top/cpastop_v580_custom.h

@@ -6,8 +6,6 @@
 #ifndef _CPASTOP_V580_CUSTOM_H_
 #define _CPASTOP_V580_CUSTOM_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v580_custom_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -17,10 +15,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v580_custom_irq_sbm = {
 			0x4 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */
 			0x8 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */
 			0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */
-			0x1000 | /* SBM_FAULTINEN0_LOW_PORT12_MASK */
-			(TEST_IRQ_ENABLE ?
-			0x40 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */
-			0x0),
+			0x1000, /* SBM_FAULTINEN0_LOW_PORT12_MASK */
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -31,7 +26,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v580_custom_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0x3880, /* SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -178,7 +173,7 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -1041,6 +1036,10 @@ static struct cam_camnoc_info cam580_custom_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v580_custom_irq_err),
 	.err_logger = &cam580_custom_err_logger_offsets,
 	.errata_wa_list = &cam580_custom_errata_wa_list,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x40,
+		.sbm_clear_mask = 0x4,
+	}
 };
 
 #endif /* _CPASTOP_V580_CUSTOM_H_ */

drivers/cam_cpas/cpas_top/cpastop_v680_100.h

@@ -6,21 +6,16 @@
 #ifndef _CPASTOP_V680_100_H_
 #define _CPASTOP_V680_100_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v680_100_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
 		.enable = true,
 		.offset = 0x2240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
 		.value = 0x2 |    /* SBM_FAULTINEN0_LOW_PORT1_MASK */
-			0x04 |     /* SBM_FAULTINEN0_LOW_PORT2_MASK */
-			0x08 |     /* SBM_FAULTINEN0_LOW_PORT3_MASK */
+			0x04 |    /* SBM_FAULTINEN0_LOW_PORT2_MASK */
+			0x08 |    /* SBM_FAULTINEN0_LOW_PORT3_MASK */
 			0x10 |    /* SBM_FAULTINEN0_LOW_PORT4_MASK */
-			0x20 |    /* SBM_FAULTINEN0_LOW_PORT5_MASK */
-			(TEST_IRQ_ENABLE ?
-			0x80 :    /* SBM_FAULTINEN0_LOW_PORT7_MASK */
-			0x0),
+			0x20,     /* SBM_FAULTINEN0_LOW_PORT5_MASK */
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -31,7 +26,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v680_100_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0x2280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -198,7 +193,7 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x80, /* SBM_FAULTINSTATUS0_LOW_PORT7_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -1285,6 +1280,10 @@ static struct cam_camnoc_info cam680_cpas100_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v680_100_irq_err),
 	.err_logger = &cam680_cpas100_err_logger_offsets,
 	.errata_wa_list = &cam680_cpas100_errata_wa_list,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x80,
+		.sbm_clear_mask = 0x4,
+	}
 };
 
 static struct cam_cpas_camnoc_qchannel cam680_cpas100_qchannel_info = {

drivers/cam_cpas/cpas_top/cpastop_v780_100.h

@@ -6,21 +6,16 @@
 #ifndef _CPASTOP_V780_100_H_
 #define _CPASTOP_V780_100_H_
 
-#define TEST_IRQ_ENABLE 0
-
 static struct cam_camnoc_irq_sbm cam_cpas_v780_100_irq_sbm = {
 	.sbm_enable = {
 		.access_type = CAM_REG_TYPE_READ_WRITE,
 		.enable = true,
-		.offset = 0x240, /* CAM_NOC_SBM_FAULTINEN0_LOW */
+		.offset = 0x240,  /* CAM_NOC_SBM_FAULTINEN0_LOW */
 		.value = 0x2 |    /* SBM_FAULTINEN0_LOW_PORT1_MASK */
-			0x04 |     /* SBM_FAULTINEN0_LOW_PORT2_MASK */
-			0x08 |     /* SBM_FAULTINEN0_LOW_PORT3_MASK */
+			0x04 |    /* SBM_FAULTINEN0_LOW_PORT2_MASK */
+			0x08 |    /* SBM_FAULTINEN0_LOW_PORT3_MASK */
 			0x10 |    /* SBM_FAULTINEN0_LOW_PORT4_MASK */
-			0x20 |    /* SBM_FAULTINEN0_LOW_PORT5_MASK */
-			(TEST_IRQ_ENABLE ?
-			0x80 :    /* SBM_FAULTINEN0_LOW_PORT7_MASK */
-			0x0),
+			0x20,     /* SBM_FAULTINEN0_LOW_PORT5_MASK */
 	},
 	.sbm_status = {
 		.access_type = CAM_REG_TYPE_READ,
@@ -31,7 +26,7 @@ static struct cam_camnoc_irq_sbm cam_cpas_v780_100_irq_sbm = {
 		.access_type = CAM_REG_TYPE_WRITE,
 		.enable = true,
 		.offset = 0x280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
-		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+		.value = 0x1,
 	}
 };
 
@@ -198,13 +193,13 @@ static struct cam_camnoc_irq_err
 	},
 	{
 		.irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST,
-		.enable = TEST_IRQ_ENABLE ? true : false,
+		.enable = false,
 		.sbm_port = 0x80, /* SBM_FAULTINSTATUS0_LOW_PORT7_MASK */
 		.err_enable = {
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.enable = true,
 			.offset = 0x288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
-			.value = 0x5,
+			.value = 0x3,
 		},
 		.err_status = {
 			.access_type = CAM_REG_TYPE_READ,
@@ -1206,6 +1201,10 @@ static struct cam_camnoc_info cam780_cpas100_camnoc_info = {
 	.irq_err_size = ARRAY_SIZE(cam_cpas_v780_100_irq_err),
 	.err_logger = &cam780_cpas100_err_logger_offsets,
 	.errata_wa_list = &cam780_cpas100_errata_wa_list,
+	.test_irq_info = {
+		.sbm_enable_mask = 0x80,
+		.sbm_clear_mask = 0x2,
+	}
 };
 
 static struct cam_cpas_camnoc_qchannel cam780_cpas100_qchannel_info = {