msm: eva: add AON mapping for FW
added support to map AON reg range for FW updated clk_get return check Change-Id: I93732f840a6354558853d6c6644b569c53fa93db Signed-off-by: Yu SI <quic_ysi@quicinc.com>
This commit is contained in:
@@ -1928,27 +1928,44 @@ static int __hwfence_regs_map(struct iris_hfi_device *device)
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return -EINVAL;
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}
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rc = iommu_map(cb->domain, device->res->ipclite_iova,
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if (device->res->ipclite_phyaddr != 0) {
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rc = iommu_map(cb->domain, device->res->ipclite_iova,
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device->res->ipclite_phyaddr,
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device->res->ipclite_size,
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IOMMU_READ | IOMMU_WRITE);
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if (rc) {
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dprintk(CVP_ERR, "map ipclite fail %d %#x %#x %#x\n",
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rc, device->res->ipclite_iova,
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device->res->ipclite_phyaddr,
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device->res->ipclite_size);
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return rc;
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if (rc) {
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dprintk(CVP_ERR, "map ipclite fail %d %#x %#x %#x\n",
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rc, device->res->ipclite_iova,
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device->res->ipclite_phyaddr,
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device->res->ipclite_size);
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return rc;
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}
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}
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rc = iommu_map(cb->domain, device->res->hwmutex_iova,
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if (device->res->hwmutex_phyaddr != 0) {
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rc = iommu_map(cb->domain, device->res->hwmutex_iova,
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device->res->hwmutex_phyaddr,
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device->res->hwmutex_size,
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IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
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if (rc) {
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dprintk(CVP_ERR, "map hwmutex fail %d %#x %#x %#x\n",
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rc, device->res->hwmutex_iova,
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device->res->hwmutex_phyaddr,
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device->res->hwmutex_size);
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return rc;
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if (rc) {
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dprintk(CVP_ERR, "map hwmutex fail %d %#x %#x %#x\n",
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rc, device->res->hwmutex_iova,
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device->res->hwmutex_phyaddr,
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device->res->hwmutex_size);
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return rc;
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}
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}
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if (device->res->aon_phyaddr != 0) {
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rc = iommu_map(cb->domain, device->res->aon_iova,
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device->res->aon_phyaddr,
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device->res->aon_size,
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IOMMU_READ | IOMMU_WRITE);
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if (rc) {
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dprintk(CVP_ERR, "map aon fail %d %#x %#x %#x\n",
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rc, device->res->aon_iova,
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device->res->aon_phyaddr,
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device->res->aon_size);
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return rc;
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}
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}
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return rc;
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}
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@@ -1964,10 +1981,18 @@ static int __hwfence_regs_unmap(struct iris_hfi_device *device)
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return -EINVAL;
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}
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iommu_unmap(cb->domain, device->res->ipclite_iova,
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if (device->res->ipclite_iova != 0) {
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iommu_unmap(cb->domain, device->res->ipclite_iova,
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device->res->ipclite_size);
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iommu_unmap(cb->domain, device->res->hwmutex_iova,
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}
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if (device->res->hwmutex_iova != 0) {
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iommu_unmap(cb->domain, device->res->hwmutex_iova,
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device->res->hwmutex_size);
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}
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if (device->res->aon_iova != 0) {
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iommu_unmap(cb->domain, device->res->aon_iova,
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device->res->aon_size);
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}
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return rc;
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}
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@@ -416,10 +416,11 @@ int msm_cvp_init_clocks(struct iris_hfi_device *device)
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iris_hfi_for_each_clock(device, cl) {
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if (!cl->clk) {
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cl->clk = clk_get(&device->res->pdev->dev, cl->name);
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if (IS_ERR_OR_NULL(cl->clk)) {
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if (IS_ERR(cl->clk)) {
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rc = PTR_ERR(cl->clk);
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dprintk(CVP_ERR,
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"Failed to get clock: %s\n", cl->name);
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rc = PTR_ERR(cl->clk) ? : -EINVAL;
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"Failed to get clock: %s, rc %d\n",
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cl->name, rc);
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cl->clk = NULL;
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goto err_clk_get;
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}
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@@ -146,6 +146,7 @@ static int msm_cvp_load_regspace_mapping(struct msm_cvp_platform_resources *res)
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int ret = 0;
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unsigned int ipclite_mapping_config[3];
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unsigned int hwmutex_mapping_config[3];
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unsigned int aon_mapping_config[3];
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struct platform_device *pdev = res->pdev;
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ret = of_property_read_u32_array(pdev->dev.of_node, "ipclite_mappings",
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@@ -170,6 +171,20 @@ static int msm_cvp_load_regspace_mapping(struct msm_cvp_platform_resources *res)
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dprintk(CVP_CORE, "ipclite %#x %#x %#x hwmutex %#x %#x %#x\n",
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res->ipclite_iova, res->ipclite_phyaddr, res->ipclite_size,
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res->hwmutex_iova, res->hwmutex_phyaddr, res->hwmutex_size);
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ret = of_property_read_u32_array(pdev->dev.of_node, "aon_mappings",
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aon_mapping_config, 3);
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if (ret) {
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dprintk(CVP_ERR, "Failed to read aon reg: %d\n", ret);
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return ret;
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}
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res->aon_iova = aon_mapping_config[0];
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res->aon_size = aon_mapping_config[1];
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res->aon_phyaddr = aon_mapping_config[2];
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dprintk(CVP_CORE, "aon %#x %#x %#x \n",
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res->hwmutex_iova, res->hwmutex_phyaddr, res->hwmutex_size);
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return ret;
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}
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@@ -167,6 +167,9 @@ struct msm_cvp_platform_resources {
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phys_addr_t hwmutex_iova;
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phys_addr_t hwmutex_phyaddr;
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uint32_t hwmutex_size;
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phys_addr_t aon_iova;
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phys_addr_t aon_phyaddr;
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uint32_t aon_size;
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uint32_t irq;
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uint32_t sku_version;
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struct allowed_clock_rates_table *allowed_clks_tbl;
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