cnss2: Fix a few issues which may impact DRV feature

Always use default PCIe link width since it will not change for the
device at run time. Also avoid accessing the bus if preventing PCIe
L1 state fails.

Change-Id: Id6d55c47f4e60788a157f060a33f5fd6e52fef1b

cnss2/pci.c

@@ -1258,7 +1258,8 @@ static int cnss_pci_get_link_status(struct cnss_pci_data *pci_priv)
 static int cnss_set_pci_link_status(struct cnss_pci_data *pci_priv,
 				    enum pci_link_status status)
 {
-	u16 link_speed, link_width;
+	u16 link_speed, link_width = pci_priv->def_link_width;
+	u16 one_lane = PCI_EXP_LNKSTA_NLW_X1 >> PCI_EXP_LNKSTA_NLW_SHIFT;
 	int ret;
 
 	cnss_pr_vdbg("Set PCI link status to: %u\n", status);
@@ -1266,16 +1267,17 @@ static int cnss_set_pci_link_status(struct cnss_pci_data *pci_priv,
 	switch (status) {
 	case PCI_GEN1:
 		link_speed = PCI_EXP_LNKSTA_CLS_2_5GB;
-		link_width = PCI_EXP_LNKSTA_NLW_X1 >> PCI_EXP_LNKSTA_NLW_SHIFT;
+		if (!link_width)
+			link_width = one_lane;
 		break;
 	case PCI_GEN2:
 		link_speed = PCI_EXP_LNKSTA_CLS_5_0GB;
-		link_width = PCI_EXP_LNKSTA_NLW_X1 >> PCI_EXP_LNKSTA_NLW_SHIFT;
+		if (!link_width)
+			link_width = one_lane;
 		break;
 	case PCI_DEF:
 		link_speed = pci_priv->def_link_speed;
-		link_width = pci_priv->def_link_width;
-		if (!link_speed && !link_width) {
+		if (!link_speed || !link_width) {
 			cnss_pr_err("PCI link speed or width is not valid\n");
 			return -EINVAL;
 		}
@@ -1966,7 +1968,11 @@ retry_mhi_suspend:
 	case CNSS_MHI_RESUME:
 		mutex_lock(&pci_priv->mhi_ctrl->pm_mutex);
 		if (pci_priv->drv_connected_last) {
-			cnss_pci_prevent_l1(&pci_priv->pci_dev->dev);
+			ret = cnss_pci_prevent_l1(&pci_priv->pci_dev->dev);
+			if (ret) {
+				mutex_unlock(&pci_priv->mhi_ctrl->pm_mutex);
+				break;
+			}
 			ret = cnss_mhi_pm_fast_resume(pci_priv, true);
 			cnss_pci_allow_l1(&pci_priv->pci_dev->dev);
 		} else {