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ASoC: wsa883x: Enable WSA883x codec driver

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Enable WSA883x codec driver to support WSA883x smart speaker
amplifier.

Change-Id: I0a773459c28ca2afc7232ec33001351152a7249a
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
This commit is contained in:
Sudheer Papothi
2019-12-17 18:24:09 +05:30
committed by Gerrit - the friendly Code Review server
parent 4a03bd5171
commit 7f9dfd57cc
7 changed files with 220 additions and 130 deletions
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1
asoc/codecs/Kbuild
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@@ -226,6 +226,7 @@ ifeq ($(KERNEL_BUILD), 1)
obj-y += wcd937x/
obj-y += wcd938x/
obj-y += bolero/
obj-y += wsa883x/
endif
# Module information used by KBuild framework
obj-$(CONFIG_WCD9XXX_CODEC_CORE) += wcd_core_dlkm.o

2
asoc/codecs/wsa883x/Kbuild
View File

@@ -51,7 +51,6 @@ ifdef CONFIG_SND_SOC_WSA883X
WSA883X_OBJS += wsa883x.o
WSA883X_OBJS += wsa883x-regmap.o
WSA883X_OBJS += wsa883x-tables.o
WSA883X_OBJS += wsa883x-temp-sensor.o
endif
LINUX_INC += -Iinclude/linux
@@ -93,6 +92,7 @@ KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wsa883x/Module.symvers
endif
# Module information used by KBuild framework

6
asoc/codecs/wsa883x/internal.h
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@@ -6,6 +6,7 @@
#ifndef WSA883X_INTERNAL_H
#define WSA883X_INTERNAL_H
#include <asoc/wcd-irq.h>
#include "wsa883x.h"
#include "wsa883x-registers.h"
@@ -63,9 +64,9 @@ enum {
};
struct wsa_ctrl_platform_data {
void *handle,
void *handle;
int (*update_wsa_event)(void *handle, u16 event, u32 data);
int (*register_notifier)(void *handle, struct notifer_block *nblock,
int (*register_notifier)(void *handle, struct notifier_block *nblock,
bool enable);
};
@@ -101,6 +102,7 @@ struct wsa883x_priv {
int pa_mute;
int curr_temp;
int variant;
u8 pa_gain;
struct irq_domain *virq;
struct wcd_irq_info irq_info;
#ifdef CONFIG_DEBUG_FS

60
asoc/codecs/wsa883x/wsa883x-registers.h
View File

@@ -15,7 +15,7 @@ enum {
RD_WR_REG,
};
#define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE+0x00000000)
#define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE+0x00000001)
#define WSA883X_REF_CTRL (WSA883X_ANA_BG_TSADC_BASE+0x0000)
#define WSA883X_TEST_CTL_0 (WSA883X_ANA_BG_TSADC_BASE+0x0001)
#define WSA883X_BIAS_0 (WSA883X_ANA_BG_TSADC_BASE+0x0002)
@@ -69,8 +69,8 @@ enum {
#define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE+0x000F)
#define WSA883X_SPKR_DRV_LF_MISC_CTL (WSA883X_ANA_SPK_TOP_BASE+0x0010)
#define WSA883X_SPKR_DRV_LF_REG_GAIN (WSA883X_ANA_SPK_TOP_BASE+0x0011)
#define WSA883X_SPKR_DRV_LF_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE+0x0012)
#define WSA883X_SPKR_DRV_LF_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE+0x0013)
#define WSA883X_SPKR_DRV_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE+0x0012)
#define WSA883X_SPKR_DRV_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE+0x0013)
#define WSA883X_SPKR_PWM_CLK_CTL (WSA883X_ANA_SPK_TOP_BASE+0x0014)
#define WSA883X_SPKR_PDRV_HS_CTL (WSA883X_ANA_SPK_TOP_BASE+0x0015)
#define WSA883X_SPKR_PDRV_LS_CTL (WSA883X_ANA_SPK_TOP_BASE+0x0016)
@@ -81,7 +81,7 @@ enum {
#define WSA883X_PA_STATUS1 (WSA883X_ANA_SPK_TOP_BASE+0x001B)
#define WSA883X_PA_STATUS2 (WSA883X_ANA_SPK_TOP_BASE+0x001C)
#define WSA883X_ANA_BOOST_BASE (WSA883X_BASE+0x00000045)
#define WSA883X_ANA_BOOST_BASE (WSA883X_BASE+0x00000043)
#define WSA883X_EN_CTRL (WSA883X_ANA_BOOST_BASE+0x0000)
#define WSA883X_CURRENT_LIMIT (WSA883X_ANA_BOOST_BASE+0x0001)
#define WSA883X_IBIAS1 (WSA883X_ANA_BOOST_BASE+0x0002)
@@ -92,34 +92,35 @@ enum {
#define WSA883X_STABILITY_CTRL2 (WSA883X_ANA_BOOST_BASE+0x0007)
#define WSA883X_PWRSTAGE_CTRL1 (WSA883X_ANA_BOOST_BASE+0x0008)
#define WSA883X_PWRSTAGE_CTRL2 (WSA883X_ANA_BOOST_BASE+0x0009)
#define WSA883X_UVLO (WSA883X_ANA_BOOST_BASE+0x000A)
#define WSA883X_SEQUENCE_CTRL (WSA883X_ANA_BOOST_BASE+0x000B)
#define WSA883X_BYPASS_1 (WSA883X_ANA_BOOST_BASE+0x000A)
#define WSA883X_BYPASS_2 (WSA883X_ANA_BOOST_BASE+0x000B)
#define WSA883X_ZX_CTRL_1 (WSA883X_ANA_BOOST_BASE+0x000C)
#define WSA883X_ZX_CTRL_2 (WSA883X_ANA_BOOST_BASE+0x000D)
#define WSA883X_MISC1 (WSA883X_ANA_BOOST_BASE+0x000E)
#define WSA883X_MISC2 (WSA883X_ANA_BOOST_BASE+0x000F)
#define WSA883X_GMAMP_SUP1 (WSA883X_ANA_BOOST_BASE+0x0010)
#define WSA883X_PWRSTAGE_CTRL3 (WSA883X_ANA_BOOST_BASE+0x0011)
#define WSA883X_PRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE+0x0012)
#define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE+0x0013)
#define WSA883X_PWRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE+0x0012)
#define WSA883X_TEST1 (WSA883X_ANA_BOOST_BASE+0x0013)
#define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE+0x0014)
#define WSA883X_SPARE2 (WSA883X_ANA_BOOST_BASE+0x0015)
#define WSA883X_ANA_PON_LDOL_BASE (WSA883X_BASE+0x00000059)
#define WSA883X_PON_CTL_0 (WSA883X_ANA_PON_LDOL_BASE+0x0000)
#define WSA883X_PON_CLT_1 (WSA883X_ANA_PON_LDOL_BASE+0x0001)
#define WSA883X_PON_CTL_2 (WSA883X_ANA_PON_LDOL_BASE+0x0002)
#define WSA883X_PON_CTL_3 (WSA883X_ANA_PON_LDOL_BASE+0x0003)
#define WSA883X_PON_CTL_4 (WSA883X_ANA_PON_LDOL_BASE+0x0004)
#define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE+0x0005)
#define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE+0x0006)
#define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE+0x0007)
#define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE+0x0008)
#define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE+0x0004)
#define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE+0x0005)
#define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE+0x0006)
#define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE+0x0007)
#define WSA883X_PADSW_CTL_0 (WSA883X_ANA_PON_LDOL_BASE+0x0008)
#define WSA883X_TEST_0 (WSA883X_ANA_PON_LDOL_BASE+0x0009)
#define WSA883X_TEST_1 (WSA883X_ANA_PON_LDOL_BASE+0x000A)
#define WSA883X_STATUS_0 (WSA883X_ANA_PON_LDOL_BASE+0x000B)
#define WSA883X_STATUS_1 (WSA883X_ANA_PON_LDOL_BASE+0x000C)
#define WSA883X_DIG_CTRL_BASE (WSA883X_BASE+0x00000400)
#define WSA883X_PAGE_REGISTER (WSA883X_DIG_CTRL_BASE+0x0000)
#define WSA883X_CHIP_ID0 (WSA883X_DIG_CTRL_BASE+0x0001)
#define WSA883X_CHIP_ID1 (WSA883X_DIG_CTRL_BASE+0x0002)
#define WSA883X_CHIP_ID2 (WSA883X_DIG_CTRL_BASE+0x0003)
@@ -130,6 +131,7 @@ enum {
#define WSA883X_CDC_PATH_MODE (WSA883X_DIG_CTRL_BASE+0x0008)
#define WSA883X_CDC_CLK_CTL (WSA883X_DIG_CTRL_BASE+0x0009)
#define WSA883X_SWR_RESET_EN (WSA883X_DIG_CTRL_BASE+0x000A)
#define WSA883X_RESET_CTL (WSA883X_DIG_CTRL_BASE+0x000B)
#define WSA883X_PA_FSM_CTL (WSA883X_DIG_CTRL_BASE+0x0010)
#define WSA883X_PA_FSM_TIMER0 (WSA883X_DIG_CTRL_BASE+0x0011)
#define WSA883X_PA_FSM_TIMER1 (WSA883X_DIG_CTRL_BASE+0x0012)
@@ -137,6 +139,7 @@ enum {
#define WSA883X_PA_FSM_ERR_COND (WSA883X_DIG_CTRL_BASE+0x0014)
#define WSA883X_PA_FSM_MSK (WSA883X_DIG_CTRL_BASE+0x0015)
#define WSA883X_PA_FSM_BYP (WSA883X_DIG_CTRL_BASE+0x0016)
#define WSA883X_PA_FSM_DBG (WSA883X_DIG_CTRL_BASE+0x0017)
#define WSA883X_TADC_VALUE_CTL (WSA883X_DIG_CTRL_BASE+0x0020)
#define WSA883X_TEMP_DETECT_CTL (WSA883X_DIG_CTRL_BASE+0x0021)
#define WSA883X_TEMP_MSB (WSA883X_DIG_CTRL_BASE+0x0022)
@@ -208,8 +211,10 @@ enum {
#define WSA883X_WAVG_PER_2_3 (WSA883X_DIG_CTRL_BASE+0x0068)
#define WSA883X_WAVG_PER_4_5 (WSA883X_DIG_CTRL_BASE+0x0069)
#define WSA883X_WAVG_PER_6_7 (WSA883X_DIG_CTRL_BASE+0x006A)
#define WSA883X_WAVG_STA (WSA883X_DIG_CTRL_BASE+0x006B)
#define WSA883X_DRE_CTL_0 (WSA883X_DIG_CTRL_BASE+0x006C)
#define WSA883X_DRE_CTL_1 (WSA883X_DIG_CTRL_BASE+0x006D)
#define WSA883X_DRE_IDLE_DET_CTL (WSA883X_DIG_CTRL_BASE+0x006E)
#define WSA883X_CLSH_CTL_0 (WSA883X_DIG_CTRL_BASE+0x0070)
#define WSA883X_CLSH_CTL_1 (WSA883X_DIG_CTRL_BASE+0x0071)
#define WSA883X_CLSH_V_HD_PA (WSA883X_DIG_CTRL_BASE+0x0072)
@@ -249,26 +254,28 @@ enum {
#define WSA883X_I2C_SLAVE_CTL (WSA883X_DIG_CTRL_BASE+0x0097)
#define WSA883X_PDM_TEST_MODE (WSA883X_DIG_CTRL_BASE+0x00A0)
#define WSA883X_ATE_TEST_MODE (WSA883X_DIG_CTRL_BASE+0x00A1)
#define WSA883X_DRE_TEST (WSA883X_DIG_CTRL_BASE+0x00A2)
#define WSA883X_DIG_DEBUG_MODE (WSA883X_DIG_CTRL_BASE+0x00A3)
#define WSA883X_DIG_DEBUG_SEL (WSA883X_DIG_CTRL_BASE+0x00A4)
#define WSA883X_DIG_DEBUG_EN (WSA883X_DIG_CTRL_BASE+0x00A5)
#define WSA883X_SWR_HM_TEST0 (WSA883X_DIG_CTRL_BASE+0x00A6)
#define WSA883X_SWR_HM_TEST1 (WSA883X_DIG_CTRL_BASE+0x00A7)
#define WSA883X_SWR_PAD_CTL (WSA883X_DIG_CTRL_BASE+0x00A8)
#define WSA883X_TEMP_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE+0x00A9)
#define WSA883X_TEMP_DEBUG_MSB (WSA883X_DIG_CTRL_BASE+0x00AA)
#define WSA883X_TEMP_DEBUG_LSB (WSA883X_DIG_CTRL_BASE+0x00AB)
#define WSA883X_TADC_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE+0x00A9)
#define WSA883X_TADC_DEBUG_MSB (WSA883X_DIG_CTRL_BASE+0x00AA)
#define WSA883X_TADC_DEBUG_LSB (WSA883X_DIG_CTRL_BASE+0x00AB)
#define WSA883X_SAMPLE_EDGE_SEL (WSA883X_DIG_CTRL_BASE+0x00AC)
#define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE+0x00AD)
#define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE+0x00AE)
#define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE+0x00B0)
#define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE+0x00B1)
#define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE+0x00B2)
#define WSA883X_SWR_EDGE_SEL (WSA883X_DIG_CTRL_BASE+0x00AD)
#define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE+0x00AE)
#define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE+0x00AF)
#define WSA883X_ANA_CSR_DBG_ADD (WSA883X_DIG_CTRL_BASE+0x00B0)
#define WSA883X_ANA_CSR_DBG_CTL (WSA883X_DIG_CTRL_BASE+0x00B1)
#define WSA883X_SPARE_R (WSA883X_DIG_CTRL_BASE+0x00BC)
#define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE+0x00BD)
#define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE+0x00BE)
#define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE+0x00BF)
#define WSA883X_SCODE (WSA883X_DIG_CTRL_BASE+0x00C0)
#define WSA883X_DIG_TRIM_BASE (WSA883X_BASE+0x00000500)
#define WSA883X_PAGE_REGISTER (WSA883X_DIG_TRIM_BASE+0x0000)
#define WSA883X_OTP_REG_0 (WSA883X_DIG_TRIM_BASE+0x0080)
#define WSA883X_OTP_REG_1 (WSA883X_DIG_TRIM_BASE+0x0081)
#define WSA883X_OTP_REG_2 (WSA883X_DIG_TRIM_BASE+0x0082)
@@ -301,7 +308,10 @@ enum {
#define WSA883X_OTP_REG_29 (WSA883X_DIG_TRIM_BASE+0x009D)
#define WSA883X_OTP_REG_30 (WSA883X_DIG_TRIM_BASE+0x009E)
#define WSA883X_OTP_REG_31 (WSA883X_DIG_TRIM_BASE+0x009F)
#define WSA883X_OTP_REG_SCODE (WSA883X_DIG_TRIM_BASE+0x00A0)
#define WSA883X_OTP_REG_32 (WSA883X_DIG_TRIM_BASE+0x00A0)
#define WSA883X_OTP_REG_33 (WSA883X_DIG_TRIM_BASE+0x00A1)
#define WSA883X_OTP_REG_34 (WSA883X_DIG_TRIM_BASE+0x00A2)
#define WSA883X_OTP_REG_35 (WSA883X_DIG_TRIM_BASE+0x00A3)
#define WSA883X_OTP_REG_63 (WSA883X_DIG_TRIM_BASE+0x00BF)
#define WSA883X_DIG_EMEM_BASE (WSA883X_BASE+0x000005C0)

160
asoc/codecs/wsa883x/wsa883x-regmap.c
View File

@@ -11,100 +11,101 @@
extern const u8 wsa883x_reg_access[WSA883X_NUM_REGISTERS];
static struct reg_default wsa883x_defaults[] = {
{WSA883X_REF_CTRL, 0x6C},
{WSA883X_REF_CTRL, 0xD5},
{WSA883X_TEST_CTL_0, 0x06},
{WSA883X_BIAS_0, 0xD2},
{WSA883X_OP_CTL, 0xE0},
{WSA883X_IREF_CTL, 0x58},
{WSA883X_IREF_CTL, 0x57},
{WSA883X_ISENS_CTL, 0x47},
{WSA883X_CLK_CTL, 0x87},
{WSA883X_TEST_CTL_1, 0x00},
{WSA883X_BIAS_1, 0x51},
{WSA883X_ADC_CTL, 0x03},
{WSA883X_ADC_CTL, 0x01},
{WSA883X_DOUT_MSB, 0x00},
{WSA883X_DOUT_LSB, 0x00},
{WSA883X_VBAT_SNS, 0x00},
{WSA883X_ITRIM_CODE, 0x1F},
{WSA883X_EN, 0x00},
{WSA883X_VBAT_SNS, 0x40},
{WSA883X_ITRIM_CODE, 0x9F},
{WSA883X_EN, 0x20},
{WSA883X_OVERRIDE1, 0x00},
{WSA883X_OVERRIDE2, 0x08},
{WSA883X_VSENSE1, 0xD3},
{WSA883X_ISENSE1, 0xD4},
{WSA883X_ISENSE2, 0x20},
{WSA883X_ISENSE_CAL, 0x00},
{WSA883X_MISC, 0x00},
{WSA883X_MISC, 0x08},
{WSA883X_ADC_0, 0x00},
{WSA883X_ADC_1, 0x00},
{WSA883X_ADC_2, 0x00},
{WSA883X_ADC_3, 0x00},
{WSA883X_ADC_4, 0x45},
{WSA883X_ADC_5, 0x20},
{WSA883X_ADC_6, 0x10},
{WSA883X_ADC_7, 0x00},
{WSA883X_ADC_2, 0x40},
{WSA883X_ADC_3, 0x80},
{WSA883X_ADC_4, 0x25},
{WSA883X_ADC_5, 0x25},
{WSA883X_ADC_6, 0x08},
{WSA883X_ADC_7, 0x81},
{WSA883X_STATUS, 0x00},
{WSA883X_DAC_CTRL_REG, 0x41},
{WSA883X_DAC_CTRL_REG, 0x53},
{WSA883X_DAC_EN_DEBUG_REG, 0x00},
{WSA883X_DAC_OPAMP_BIAS1_REG, 0x48},
{WSA883X_DAC_OPAMP_BIAS2_REG, 0x48},
{WSA883X_DAC_VCM_CTRL_REG, 0x0B},
{WSA883X_DAC_VOLTAGE_CTRL_REG, 0x05},
{WSA883X_DAC_VCM_CTRL_REG, 0x88},
{WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5},
{WSA883X_ATEST1_REG, 0x00},
{WSA883X_ATEST2_REG, 0x00},
{WSA883X_SPKR_TOP_BIAS_REG1, 0x4A},
{WSA883X_SPKR_TOP_BIAS_REG1, 0x6A},
{WSA883X_SPKR_TOP_BIAS_REG2, 0x65},
{WSA883X_SPKR_TOP_BIAS_REG3, 0x55},
{WSA883X_SPKR_TOP_BIAS_REG4, 0xA9},
{WSA883X_SPKR_CLIP_DET_REG, 0x00},
{WSA883X_SPKR_CLIP_DET_REG, 0x9C},
{WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F},
{WSA883X_SPKR_DRV_LF_EN, 0x0A},
{WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00},
{WSA883X_SPKR_DRV_LF_MISC_CTL, 0x32},
{WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A},
{WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00},
{WSA883X_SPKR_DRV_LF_OS_CAL_CTL1, 0x90},
{WSA883X_SPKR_DRV_LF_OS_CAL_CTL, 0x00},
{WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00},
{WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90},
{WSA883X_SPKR_PWM_CLK_CTL, 0x00},
{WSA883X_SPKR_PDRV_HS_CTL, 0x50},
{WSA883X_SPKR_PDRV_HS_CTL, 0x52},
{WSA883X_SPKR_PDRV_LS_CTL, 0x48},
{WSA883X_SPKR_PWRSTG_DBG, 0x00},
{WSA883X_SPKR_OCP_CTL, 0x00},
{WSA883X_SPKR_BBM_CTL, 0x90},
{WSA883X_SPKR_PWRSTG_DBG, 0x08},
{WSA883X_SPKR_OCP_CTL, 0xE2},
{WSA883X_SPKR_BBM_CTL, 0x92},
{WSA883X_PA_STATUS0, 0x00},
{WSA883X_PA_STATUS1, 0x00},
{WSA883X_PA_STATUS2, 0x00},
{WSA883X_EN_CTRL, 0x54},
{WSA883X_CURRENT_LIMIT, 0x90},
{WSA883X_PA_STATUS2, 0x80},
{WSA883X_EN_CTRL, 0x44},
{WSA883X_CURRENT_LIMIT, 0xCC},
{WSA883X_IBIAS1, 0x00},
{WSA883X_IBIAS2, 0x00},
{WSA883X_IBIAS3, 0x00},
{WSA883X_LDO_PROG, 0x2A},
{WSA883X_LDO_PROG, 0x02},
{WSA883X_STABILITY_CTRL1, 0x8E},
{WSA883X_STABILITY_CTRL2, 0x00},
{WSA883X_PWRSTAGE_CTRL1, 0x00},
{WSA883X_PWRSTAGE_CTRL2, 0x40},
{WSA883X_UVLO, 0xE9},
{WSA883X_SEQUENCE_CTRL, 0x11},
{WSA883X_STABILITY_CTRL2, 0x10},
{WSA883X_PWRSTAGE_CTRL1, 0x06},
{WSA883X_PWRSTAGE_CTRL2, 0x00},
{WSA883X_BYPASS_1, 0x19},
{WSA883X_BYPASS_2, 0x13},
{WSA883X_ZX_CTRL_1, 0xF0},
{WSA883X_ZX_CTRL_2, 0x06},
{WSA883X_MISC1, 0x02},
{WSA883X_MISC2, 0x81},
{WSA883X_GMAMP_SUP1, 0x84},
{WSA883X_PWRSTAGE_CTRL3, 0x14},
{WSA883X_PRSTAGE_CTRL4, 0x5F},
{WSA883X_ZX_CTRL_2, 0x04},
{WSA883X_MISC1, 0x06},
{WSA883X_MISC2, 0xA0},
{WSA883X_GMAMP_SUP1, 0x82},
{WSA883X_PWRSTAGE_CTRL3, 0x39},
{WSA883X_PWRSTAGE_CTRL4, 0x5F},
{WSA883X_TEST1, 0x00},
{WSA883X_SPARE1, 0x00},
{WSA883X_PON_CTL_0, 0xE3},
{WSA883X_PON_CLT_1, 0x70},
{WSA883X_PON_CTL_2, 0x00},
{WSA883X_PON_CTL_3, 0x00},
{WSA883X_PON_CTL_4, 0x00},
{WSA883X_SPARE2, 0x00},
{WSA883X_PON_CTL_0, 0x10},
{WSA883X_PON_CLT_1, 0xE0},
{WSA883X_PON_CTL_2, 0x90},
{WSA883X_PON_CTL_3, 0x70},
{WSA883X_CKWD_CTL_0, 0x34},
{WSA883X_CKWD_CTL_1, 0x80},
{WSA883X_CKWD_CTL_1, 0x0F},
{WSA883X_CKWD_CTL_2, 0x00},
{WSA883X_CKSK_CTL_0, 0x0A},
{WSA883X_CKSK_CTL_0, 0x00},
{WSA883X_PADSW_CTL_0, 0x00},
{WSA883X_TEST_0, 0x00},
{WSA883X_TEST_1, 0x00},
{WSA883X_STATUS_0, 0x00},
{WSA883X_STATUS_1, 0x00},
{WSA883X_PAGE_REGISTER, 0x00},
{WSA883X_CHIP_ID0, 0x00},
{WSA883X_CHIP_ID1, 0x00},
{WSA883X_CHIP_ID2, 0x02},
@@ -115,13 +116,15 @@ static struct reg_default wsa883x_defaults[] = {
{WSA883X_CDC_PATH_MODE, 0x00},
{WSA883X_CDC_CLK_CTL, 0xFF},
{WSA883X_SWR_RESET_EN, 0x00},
{WSA883X_RESET_CTL, 0x00},
{WSA883X_PA_FSM_CTL, 0x00},
{WSA883X_PA_FSM_TIMER0, 0x80},
{WSA883X_PA_FSM_TIMER1, 0x80},
{WSA883X_PA_FSM_STA, 0x00},
{WSA883X_PA_FSM_ERR_COND, 0x00},
{WSA883X_PA_FSM_MSK, 0x00},
{WSA883X_PA_FSM_BYP, 0x00},
{WSA883X_PA_FSM_BYP, 0x01},
{WSA883X_PA_FSM_DBG, 0x00},
{WSA883X_TADC_VALUE_CTL, 0x03},
{WSA883X_TEMP_DETECT_CTL, 0x01},
{WSA883X_TEMP_MSB, 0x00},
@@ -193,15 +196,17 @@ static struct reg_default wsa883x_defaults[] = {
{WSA883X_WAVG_PER_2_3, 0x88},
{WSA883X_WAVG_PER_4_5, 0x88},
{WSA883X_WAVG_PER_6_7, 0x88},
{WSA883X_DRE_CTL_0, 0x30},
{WSA883X_DRE_CTL_1, 0x20},
{WSA883X_WAVG_STA, 0x00},
{WSA883X_DRE_CTL_0, 0x70},
{WSA883X_DRE_CTL_1, 0x08},
{WSA883X_DRE_IDLE_DET_CTL, 0x1F},
{WSA883X_CLSH_CTL_0, 0x37},
{WSA883X_CLSH_CTL_1, 0x81},
{WSA883X_CLSH_V_HD_PA, 0x0F},
{WSA883X_CLSH_V_PA_MIN, 0x00},
{WSA883X_CLSH_OVRD_VAL, 0x00},
{WSA883X_CLSH_HARD_MAX, 0xFF},
{WSA883X_CLSH_SOFT_MAX, 0xFF},
{WSA883X_CLSH_SOFT_MAX, 0xF5},
{WSA883X_CLSH_SIG_DP, 0x00},
{WSA883X_TAGC_CTL, 0x10},
{WSA883X_TAGC_TIME, 0x20},
@@ -212,18 +217,18 @@ static struct reg_default wsa883x_defaults[] = {
{WSA883X_VAGC_ATTN_LVL_1_2, 0x21},
{WSA883X_VAGC_ATTN_LVL_3, 0x03},
{WSA883X_INTR_MODE, 0x00},
{WSA883X_INTR_MASK0, 0x1B},
{WSA883X_INTR_MASK1, 0x03},
{WSA883X_INTR_MASK0, 0x90},
{WSA883X_INTR_MASK1, 0x00},
{WSA883X_INTR_STATUS0, 0x00},
{WSA883X_INTR_STATUS1, 0x00},
{WSA883X_INTR_CLEAR0, 0x00},
{WSA883X_INTR_CLEAR1, 0x03},
{WSA883X_INTR_CLEAR1, 0x00},
{WSA883X_INTR_LEVEL0, 0x00},
{WSA883X_INTR_LEVEL1, 0x03},
{WSA883X_INTR_LEVEL1, 0x00},
{WSA883X_INTR_SET0, 0x00},
{WSA883X_INTR_SET1, 0x03},
{WSA883X_INTR_SET1, 0x00},
{WSA883X_INTR_TEST0, 0x00},
{WSA883X_INTR_TEST1, 0x03},
{WSA883X_INTR_TEST1, 0x00},
{WSA883X_OTP_CTRL0, 0x00},
{WSA883X_OTP_CTRL1, 0x00},
{WSA883X_HDRIVE_CTL_GROUP1, 0x00},
@@ -234,25 +239,27 @@ static struct reg_default wsa883x_defaults[] = {
{WSA883X_I2C_SLAVE_CTL, 0x00},
{WSA883X_PDM_TEST_MODE, 0x00},
{WSA883X_ATE_TEST_MODE, 0x00},
{WSA883X_DRE_TEST, 0x00},
{WSA883X_DIG_DEBUG_MODE, 0x00},
{WSA883X_DIG_DEBUG_SEL, 0x00},
{WSA883X_DIG_DEBUG_EN, 0x00},
{WSA883X_SWR_HM_TEST0, 0x08},
{WSA883X_SWR_HM_TEST1, 0x00},
{WSA883X_SWR_PAD_CTL, 0x45},
{WSA883X_TEMP_DETECT_DBG_CTL, 0x00},
{WSA883X_TEMP_DEBUG_MSB, 0x00},
{WSA883X_TEMP_DEBUG_LSB, 0x00},
{WSA883X_SWR_PAD_CTL, 0x37},
{WSA883X_TADC_DETECT_DBG_CTL, 0x00},
{WSA883X_TADC_DEBUG_MSB, 0x00},
{WSA883X_TADC_DEBUG_LSB, 0x00},
{WSA883X_SAMPLE_EDGE_SEL, 0x7F},
{WSA883X_TEST_MODE_CTL, 0x00},
{WSA883X_SWR_EDGE_SEL, 0x00},
{WSA883X_TEST_MODE_CTL, 0x04},
{WSA883X_IOPAD_CTL, 0x00},
{WSA883X_ANA_CSR_DBG_ADD, 0x00},
{WSA883X_ANA_CSR_DBG_CTL, 0x12},
{WSA883X_SPARE_R, 0x00},
{WSA883X_SPARE_0, 0x00},
{WSA883X_SPARE_1, 0x00},
{WSA883X_SPARE_2, 0x00},
{WSA883X_SCODE, 0x00},
{WSA883X_PAGE_REGISTER, 0x00},
{WSA883X_OTP_REG_0, 0x01},
{WSA883X_OTP_REG_0, 0x05},
{WSA883X_OTP_REG_1, 0xFF},
{WSA883X_OTP_REG_2, 0xC0},
{WSA883X_OTP_REG_3, 0xFF},
@@ -276,15 +283,18 @@ static struct reg_default wsa883x_defaults[] = {
{WSA883X_OTP_REG_21, 0xFF},
{WSA883X_OTP_REG_22, 0xFF},
{WSA883X_OTP_REG_23, 0xFF},
{WSA883X_OTP_REG_24, 0x03},
{WSA883X_OTP_REG_25, 0x01},
{WSA883X_OTP_REG_24, 0x37},
{WSA883X_OTP_REG_25, 0x3F},
{WSA883X_OTP_REG_26, 0x03},
{WSA883X_OTP_REG_27, 0x11},
{WSA883X_OTP_REG_28, 0x3F},
{WSA883X_OTP_REG_29, 0x3F},
{WSA883X_OTP_REG_30, 0x01},
{WSA883X_OTP_REG_31, 0x01},
{WSA883X_OTP_REG_SCODE, 0x00},
{WSA883X_OTP_REG_27, 0x00},
{WSA883X_OTP_REG_28, 0x00},
{WSA883X_OTP_REG_29, 0x00},
{WSA883X_OTP_REG_30, 0x00},
{WSA883X_OTP_REG_31, 0x03},
{WSA883X_OTP_REG_32, 0x00},
{WSA883X_OTP_REG_33, 0xFF},
{WSA883X_OTP_REG_34, 0x00},
{WSA883X_OTP_REG_35, 0x00},
{WSA883X_OTP_REG_63, 0x40},
{WSA883X_EMEM_0, 0x00},
{WSA883X_EMEM_1, 0x00},
@@ -377,7 +387,7 @@ static bool wsa883x_volatile_register(struct device *dev, unsigned int reg)
!(wsa883x_reg_access[WSA883X_REG(reg)] & WR_REG));
}
struct regmap_config wsa881x_regmap_config = {
struct regmap_config wsa883x_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,

40
asoc/codecs/wsa883x/wsa883x-tables.c
View File

@@ -57,14 +57,14 @@ const u8 wsa883x_reg_readable[WSA883X_NUM_REGISTERS] = {
[WSA883X_REG(WSA883X_SPKR_DRV_LF_MASK_DCC_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_DRV_LF_MISC_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_DRV_LF_REG_GAIN)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_DRV_LF_OS_CAL_CTL1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_DRV_LF_OS_CAL_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_DRV_OS_CAL_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_DRV_OS_CAL_CTL1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_PWM_CLK_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_PDRV_HS_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_PDRV_LS_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_PWRSTG_DBG)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_OCP_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPKR_BBM_CTL)] = RD_REG,
[WSA883X_REG(WSA883X_SPKR_BBM_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PA_STATUS0)] = RD_REG,
[WSA883X_REG(WSA883X_PA_STATUS1)] = RD_REG,
[WSA883X_REG(WSA883X_PA_STATUS2)] = RD_REG,
@@ -78,30 +78,31 @@ const u8 wsa883x_reg_readable[WSA883X_NUM_REGISTERS] = {
[WSA883X_REG(WSA883X_STABILITY_CTRL2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PWRSTAGE_CTRL1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PWRSTAGE_CTRL2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_UVLO)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SEQUENCE_CTRL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_BYPASS_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_BYPASS_2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_ZX_CTRL_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_ZX_CTRL_2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_MISC1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_MISC2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_GMAMP_SUP1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PWRSTAGE_CTRL3)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PRSTAGE_CTRL4)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PWRSTAGE_CTRL4)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEST1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPARE1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPARE2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PON_CTL_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PON_CLT_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PON_CTL_2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PON_CTL_3)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PON_CTL_4)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CKWD_CTL_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CKWD_CTL_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CKWD_CTL_2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CKSK_CTL_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PADSW_CTL_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEST_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEST_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_STATUS_0)] = RD_REG,
[WSA883X_REG(WSA883X_STATUS_1)] = RD_REG,
[WSA883X_REG(WSA883X_PAGE_REGISTER)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CHIP_ID0)] = RD_REG,
[WSA883X_REG(WSA883X_CHIP_ID1)] = RD_REG,
[WSA883X_REG(WSA883X_CHIP_ID2)] = RD_REG,
@@ -112,6 +113,7 @@ const u8 wsa883x_reg_readable[WSA883X_NUM_REGISTERS] = {
[WSA883X_REG(WSA883X_CDC_PATH_MODE)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CDC_CLK_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SWR_RESET_EN)] = RD_WR_REG,
[WSA883X_REG(WSA883X_RESET_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PA_FSM_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PA_FSM_TIMER0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PA_FSM_TIMER1)] = RD_WR_REG,
@@ -119,6 +121,7 @@ const u8 wsa883x_reg_readable[WSA883X_NUM_REGISTERS] = {
[WSA883X_REG(WSA883X_PA_FSM_ERR_COND)] = RD_REG,
[WSA883X_REG(WSA883X_PA_FSM_MSK)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PA_FSM_BYP)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PA_FSM_DBG)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TADC_VALUE_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEMP_DETECT_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEMP_MSB)] = RD_REG,
@@ -190,8 +193,10 @@ const u8 wsa883x_reg_readable[WSA883X_NUM_REGISTERS] = {
[WSA883X_REG(WSA883X_WAVG_PER_2_3)] = RD_WR_REG,
[WSA883X_REG(WSA883X_WAVG_PER_4_5)] = RD_WR_REG,
[WSA883X_REG(WSA883X_WAVG_PER_6_7)] = RD_WR_REG,
[WSA883X_REG(WSA883X_WAVG_STA)] = RD_REG,
[WSA883X_REG(WSA883X_DRE_CTL_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_DRE_CTL_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_DRE_IDLE_DET_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CLSH_CTL_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CLSH_CTL_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_CLSH_V_HD_PA)] = RD_WR_REG,
@@ -231,24 +236,26 @@ const u8 wsa883x_reg_readable[WSA883X_NUM_REGISTERS] = {
[WSA883X_REG(WSA883X_I2C_SLAVE_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PDM_TEST_MODE)] = RD_WR_REG,
[WSA883X_REG(WSA883X_ATE_TEST_MODE)] = RD_REG,
[WSA883X_REG(WSA883X_DRE_TEST)] = RD_WR_REG,
[WSA883X_REG(WSA883X_DIG_DEBUG_MODE)] = RD_WR_REG,
[WSA883X_REG(WSA883X_DIG_DEBUG_SEL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_DIG_DEBUG_EN)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SWR_HM_TEST0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SWR_HM_TEST1)] = RD_REG,
[WSA883X_REG(WSA883X_SWR_PAD_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEMP_DETECT_DBG_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEMP_DEBUG_MSB)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEMP_DEBUG_LSB)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TADC_DETECT_DBG_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TADC_DEBUG_MSB)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TADC_DEBUG_LSB)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SAMPLE_EDGE_SEL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SWR_EDGE_SEL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_TEST_MODE_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_IOPAD_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_ANA_CSR_DBG_ADD)] = RD_WR_REG,
[WSA883X_REG(WSA883X_ANA_CSR_DBG_CTL)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPARE_R)] = RD_REG,
[WSA883X_REG(WSA883X_SPARE_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPARE_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SPARE_2)] = RD_WR_REG,
[WSA883X_REG(WSA883X_SCODE)] = RD_WR_REG,
[WSA883X_REG(WSA883X_PAGE_REGISTER)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_1)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_2)] = RD_WR_REG,
@@ -280,8 +287,11 @@ const u8 wsa883x_reg_readable[WSA883X_NUM_REGISTERS] = {
[WSA883X_REG(WSA883X_OTP_REG_28)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_29)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_30)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_31)] = RD_REG,
[WSA883X_REG(WSA883X_OTP_REG_SCODE)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_31)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_32)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_33)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_34)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_35)] = RD_WR_REG,
[WSA883X_REG(WSA883X_OTP_REG_63)] = RD_WR_REG,
[WSA883X_REG(WSA883X_EMEM_0)] = RD_WR_REG,
[WSA883X_REG(WSA883X_EMEM_1)] = RD_WR_REG,

81
asoc/codecs/wsa883x/wsa883x.c
View File

@@ -16,6 +16,7 @@
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#include <linux/regmap.h>
#include <linux/debugfs.h>
#include <soc/soundwire.h>
@@ -35,6 +36,8 @@
#define TEMP_INVALID 0xFFFF
#define WSA883X_TEMP_RETRY 3
#define DRV_NAME "wsa-codec"
enum {
WSA_4OHMS =4,
WSA_8OHMS = 8,
@@ -51,6 +54,56 @@ struct wsa_temp_register {
u8 dmeas_lsb;
};
struct wsa_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
static const struct wsa_reg_mask_val reg_init[] = {
{WSA883X_PA_FSM_BYP, 0x01, 0x00},
{WSA883X_CDC_SPK_DSM_A2_0, 0xFF, 0x0A},
{WSA883X_CDC_SPK_DSM_A2_1, 0x0F, 0x08},
{WSA883X_CDC_SPK_DSM_A3_0, 0xFF, 0xF3},
{WSA883X_CDC_SPK_DSM_A3_1, 0x07, 0x07},
{WSA883X_CDC_SPK_DSM_A4_0, 0xFF, 0x79},
{WSA883X_CDC_SPK_DSM_A4_1, 0x03, 0x02},
{WSA883X_CDC_SPK_DSM_A5_0, 0xFF, 0x0B},
{WSA883X_CDC_SPK_DSM_A5_1, 0x03, 0x02},
{WSA883X_CDC_SPK_DSM_A6_0, 0xFF, 0x8A},
{WSA883X_CDC_SPK_DSM_A7_0, 0xFF, 0x9B},
{WSA883X_CDC_SPK_DSM_C_0, 0xFF, 0x68},
{WSA883X_CDC_SPK_DSM_C_1, 0xFF, 0x54},
{WSA883X_CDC_SPK_DSM_C_2, 0xFF, 0xF2},
{WSA883X_CDC_SPK_DSM_C_3, 0x3F, 0x20},
{WSA883X_CDC_SPK_DSM_R1, 0xFF, 0x83},
{WSA883X_CDC_SPK_DSM_R2, 0xFF, 0x7F},
{WSA883X_CDC_SPK_DSM_R3, 0xFF, 0x9D},
{WSA883X_CDC_SPK_DSM_R4, 0xFF, 0x82},
{WSA883X_CDC_SPK_DSM_R5, 0xFF, 0x8B},
{WSA883X_CDC_SPK_DSM_R6, 0xFF, 0x9B},
{WSA883X_CDC_SPK_DSM_R7, 0xFF, 0x3F},
{WSA883X_DRE_CTL_0, 0xF0, 0x90},
{WSA883X_DRE_IDLE_DET_CTL, 0x10, 0x00},
{WSA883X_PDM_WD_CTL, 0x01, 0x01},
{WSA883X_CURRENT_LIMIT, 0x78, 0x40},
{WSA883X_DRE_CTL_0, 0x07, 0x02},
{WSA883X_VAGC_TIME, 0x03, 0x02},
{WSA883X_VAGC_CTL, 0x01, 0x01},
{WSA883X_TAGC_CTL, 0x0E, 0x0A},
{WSA883X_TAGC_TIME, 0x0C, 0x0C},
{WSA883X_TAGC_E2E_GAIN, 0x1F, 0x02},
{WSA883X_TEMP_CONFIG0, 0x07, 0x02},
{WSA883X_TEMP_CONFIG1, 0x07, 0x02},
{WSA883X_OTP_REG_1, 0xFF, 0x49},
{WSA883X_OTP_REG_2, 0xC0, 0x80},
{WSA883X_OTP_REG_3, 0xFF, 0xC9},
{WSA883X_OTP_REG_4, 0xC0, 0x40},
{WSA883X_TAGC_CTL, 0x01, 0x01},
{WSA883X_CKWD_CTL_0, 0x60, 0x00},
{WSA883X_CKWD_CTL_1, 0x1F, 0x1B},
};
static int wsa883x_get_temperature(struct snd_soc_component *component,
int *temp);
enum {
@@ -69,6 +122,7 @@ enum {
WSA883X_IRQ_INT_INTR_PIN,
WSA883X_IRQ_INT_UVLO,
WSA883X_IRQ_INT_PA_ON_ERR,
WSA883X_NUM_IRQS,
};
static const struct regmap_irq wsa883x_irqs[WSA883X_NUM_IRQS] = {
@@ -826,12 +880,12 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
int min_gain, max_gain;
dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* TODO Vote for Global PA */
snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL,
0x01, 0x01);
break;
case SND_SOC_DAPM_POST_PMU:
@@ -840,7 +894,8 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
wsa883x->swr_slave->dev_num);
break;
case SND_SOC_DAPM_POST_PMD:
/* TODO Unvote for Global PA */
snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL,
0x01, 0x00);
break;
}
return 0;
@@ -891,10 +946,14 @@ EXPORT_SYMBOL(wsa883x_set_channel_map);
static void wsa883x_codec_init(struct snd_soc_component *component)
{
struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
int i;
if (!wsa883x)
return;
for (i = 0; i < ARRAY_SIZE(reg_init); i++)
snd_soc_component_update_bits(component, reg_init[i].reg,
reg_init[i].mask, reg_init[i].val);
}
static int32_t wsa883x_temp_reg_read(struct snd_soc_component *component,
@@ -936,7 +995,6 @@ static int32_t wsa883x_temp_reg_read(struct snd_soc_component *component,
static int wsa883x_get_temperature(struct snd_soc_component *component,
int *temp)
{
struct snd_soc_component *component;
struct wsa_temp_register reg;
int dmeas, d1, d2;
int ret = 0;
@@ -950,7 +1008,7 @@ static int wsa883x_get_temperature(struct snd_soc_component *component,
return -EINVAL;
do {
ret = wsa883x_temp_reg_read(component, &reg)
ret = wsa883x_temp_reg_read(component, &reg);
if (ret) {
pr_err("%s: temp read failed: %d, current temp: %d\n",
__func__, ret, wsa883x->curr_temp);
@@ -1075,13 +1133,12 @@ static int wsa883x_event_notify(struct notifier_block *nb,
switch (event) {
case BOLERO_WSA_EVT_PA_OFF_PRE_SSR:
snd_soc_component_update_bits(wsa883x->component,
WSA883X_SPKR_DRV_GAIN,
0xF0, 0xC0);
snd_soc_component_update_bits(wsa883x->component,
WSA883X_SPKR_DRV_EN,
0x80, 0x00);
WSA883X_PA_FSM_CTL,
0x01, 0x00);
break;
default:
dev_dbg(wsa883x->dev, "%s: unknown event %d\n",
__func__, event);
break;
}
@@ -1090,7 +1147,7 @@ static int wsa883x_event_notify(struct notifier_block *nb,
static int wsa883x_swr_probe(struct swr_device *pdev)
{
int ret = 0;
int ret = 0, i = 0;
struct wsa883x_priv *wsa883x;
u8 devnum = 0;
bool pin_state_current = false;
@@ -1143,7 +1200,7 @@ static int wsa883x_swr_probe(struct swr_device *pdev)
wsa883x->irq_info.wcd_regmap_irq_chip = &wsa883x_regmap_irq_chip;
wsa883x->irq_info.codec_name = "WSA883X";
wsa883x->irq_info.regmap = wsa883x->regmap;
wsa883x->irq_info.dev = dev;
wsa883x->irq_info.dev = &pdev->dev;
ret = wcd_irq_init(&wsa883x->irq_info, &wsa883x->virq);
if (ret) {