asoc: codecs: error fix for soc_component_read_no_lock
the offset between LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 and LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 is 8 so updating 0x104 + 8* interp update ng block register write for NG2 mode in Kundu Change-Id: I44da894feebb5d25bd467ffd4d54adde111778e6 Signed-off-by: Shazmaan Ali <quic_shazmaan@quicinc.com>
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@@ -1316,7 +1316,7 @@ static int lpass_cdc_macro_set_idle_detect_thr(struct snd_soc_component *compone
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*/
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if (path_type == INTERP_MIX_PATH) {
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mux_reg = LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 +
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2 * interp;
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8 * interp;
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mux_reg_val = snd_soc_component_read(component, mux_reg) &
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0x0f;
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@@ -1329,7 +1329,7 @@ static int lpass_cdc_macro_set_idle_detect_thr(struct snd_soc_component *compone
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if (path_type == INTERP_MAIN_PATH) {
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mux_reg = LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 +
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2 * (interp - 1);
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8 * (interp - 1);
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mux_reg_val = snd_soc_component_read(component, mux_reg) &
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0x0f;
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i = NUM_INTERPOLATORS;
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@@ -756,11 +756,11 @@ static void wsa_noise_gate_write(struct snd_soc_component *component,
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break;
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case NG2:
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snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
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WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x28);
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WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x20);
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break;
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case NG3:
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snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
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WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x18);
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WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x10);
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break;
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default:
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snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
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