disp: msm: sde: move boolean flags in catalog to a bitmap

Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.

Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>

msm/sde/sde_color_processing.c

@@ -3061,7 +3061,7 @@ static void _dspp_rc_install_property(struct drm_crtc *crtc)
 				sizeof(struct drm_msm_rc_mask_cfg));
 
 		/* Override flush mechanism to use layer mixer flush bits */
-		if (!catalog->rc_lm_flush_override)
+		if (!test_bit(SDE_FEATURE_RC_LM_FLUSH_OVERRIDE, catalog->features))
 			break;
 
 		DRM_DEBUG("rc using lm flush override\n");

msm/sde/sde_connector.c

@@ -2860,9 +2860,10 @@ static int sde_connector_populate_mode_info(struct drm_connector *conn,
 		}
 
 		sde_kms_info_add_keyint(info, "qsync_min_fps", mode_info.qsync_min_fps);
-		sde_kms_info_add_keyint(info, "has_cwb_crop", sde_kms->catalog->has_cwb_crop);
+		sde_kms_info_add_keyint(info, "has_cwb_crop", test_bit(SDE_FEATURE_CWB_CROP,
+								       sde_kms->catalog->features));
 		sde_kms_info_add_keyint(info, "has_dedicated_cwb_support",
-			sde_kms->catalog->has_dedicated_cwb_support);
+				test_bit(SDE_FEATURE_DEDICATED_CWB, sde_kms->catalog->features));
 
 		sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
 			mode_info.mdp_transfer_time_us);
@@ -3083,13 +3084,13 @@ static int _sde_connector_install_properties(struct drm_device *dev,
 			CONNECTOR_PROP_AUTOREFRESH);
 
 	if (connector_type == DRM_MODE_CONNECTOR_DSI) {
-		if (sde_kms->catalog->has_qsync && dsi_display && dsi_display->panel &&
+		if (test_bit(SDE_FEATURE_QSYNC, sde_kms->catalog->features) && dsi_display &&
-				dsi_display->panel->qsync_caps.qsync_support) {
+		    dsi_display->panel && dsi_display->panel->qsync_caps.qsync_support) {
 			msm_property_install_enum(&c_conn->property_info,
 					"qsync_mode", 0, 0, e_qsync_mode,
 					ARRAY_SIZE(e_qsync_mode), 0,
 					CONNECTOR_PROP_QSYNC_MODE);
-			if (sde_kms->catalog->has_avr_step)
+			if (test_bit(SDE_FEATURE_AVR_STEP, sde_kms->catalog->features))
 				msm_property_install_range(&c_conn->property_info,
 						"avr_step", 0x0, 0, U32_MAX, 0,
 						CONNECTOR_PROP_AVR_STEP);
@@ -3113,7 +3114,7 @@ static int _sde_connector_install_properties(struct drm_device *dev,
 			ARRAY_SIZE(e_panel_mode), 0,
 			CONNECTOR_PROP_SET_PANEL_MODE);
 
-		if (sde_kms->catalog->has_demura) {
+		if (test_bit(SDE_FEATURE_DEMURA, sde_kms->catalog->features)) {
 			msm_property_install_blob(&c_conn->property_info,
 				"DEMURA_PANEL_ID", DRM_MODE_PROP_IMMUTABLE,
 				CONNECTOR_PROP_DEMURA_PANEL_ID);
@@ -3292,7 +3293,7 @@ struct drm_connector *sde_connector_init(struct drm_device *dev,
 		goto error_cleanup_fence;
 
 	if (connector_type == DRM_MODE_CONNECTOR_DSI &&
-			sde_kms->catalog->has_demura) {
+			test_bit(SDE_FEATURE_DEMURA, sde_kms->catalog->features)) {
 		rc = sde_connector_register_event(&c_conn->base,
 			SDE_CONN_EVENT_PANEL_ID,
 			sde_connector_handle_panel_id, c_conn);

msm/sde/sde_crtc.c

@@ -1968,19 +1968,16 @@ static void _sde_drm_fb_sec_dir_trans(
 	struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
 {
 	/* secure display usecase */
-	if ((smmu_state->state == ATTACHED)
+	if ((smmu_state->state == ATTACHED) && (secure_level == SDE_DRM_SEC_ONLY)) {
-			&& (secure_level == SDE_DRM_SEC_ONLY)) {
+		smmu_state->state = (test_bit(SDE_FEATURE_SUI_NS_ALLOWED, catalog->features)) ?
-		smmu_state->state = catalog->sui_ns_allowed ?
 				    DETACH_SEC_REQ : DETACH_ALL_REQ;
 		smmu_state->secure_level = secure_level;
 		smmu_state->transition_type = PRE_COMMIT;
 		*ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
 		if (old_valid_fb)
-			*ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE  |
+			*ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE | SDE_KMS_OPS_CLEANUP_PLANE_FB);
-					SDE_KMS_OPS_CLEANUP_PLANE_FB);
+		if (test_bit(SDE_FEATURE_SUI_MISR, catalog->features))
-		if (catalog->sui_misr_supported)
+			smmu_state->sui_misr_state = SUI_MISR_ENABLE_REQ;
-			smmu_state->sui_misr_state =
-				SUI_MISR_ENABLE_REQ;
 	/* secure camera usecase */
 	} else if (smmu_state->state == ATTACHED) {
 		smmu_state->state = DETACH_SEC_REQ;
@@ -2000,16 +1997,15 @@ static void _sde_drm_fb_transactions(
 			|| ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
 				&& ((smmu_state->state == DETACHED_SEC)
 				|| (smmu_state->state == DETACH_SEC_REQ)))) {
-		smmu_state->state = catalog->sui_ns_allowed ?
+		smmu_state->state = (test_bit(SDE_FEATURE_SUI_NS_ALLOWED, catalog->features)) ?
 			ATTACH_SEC_REQ : ATTACH_ALL_REQ;
 		smmu_state->transition_type = post_commit ?
 			POST_COMMIT : PRE_COMMIT;
 		*ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
 		if (old_valid_fb)
 			*ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
-		if (catalog->sui_misr_supported)
+		if (test_bit(SDE_FEATURE_SUI_MISR, catalog->features))
-			smmu_state->sui_misr_state =
+			smmu_state->sui_misr_state = SUI_MISR_DISABLE_REQ;
-				SUI_MISR_DISABLE_REQ;
 	} else if ((smmu_state->state == DETACHED_SEC)
 			|| (smmu_state->state == DETACH_SEC_REQ)) {
 		smmu_state->state = ATTACH_SEC_REQ;
@@ -2923,9 +2919,8 @@ static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
 		user_cfg = &dim_layer_v1.layer_cfg[i];
 
 		dim_layer[i].flags = user_cfg->flags;
-		dim_layer[i].stage = (kms->catalog->has_base_layer) ?
+		dim_layer[i].stage = test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features) ?
-					user_cfg->stage : user_cfg->stage +
+					user_cfg->stage : user_cfg->stage + SDE_STAGE_0;
-					SDE_STAGE_0;
 
 		dim_layer[i].rect.x = user_cfg->rect.x1;
 		dim_layer[i].rect.y = user_cfg->rect.y1;
@@ -4570,7 +4565,7 @@ static void sde_crtc_disable(struct drm_crtc *crtc)
 		 * reset idle power-collapse to original state during suspend;
 		 * user-mode will change the state on resume, if required
 		 */
-		if (sde_kms->catalog->has_idle_pc)
+		if (test_bit(SDE_FEATURE_IDLE_PC, sde_kms->catalog->features))
 			sde_encoder_control_idle_pc(encoder, true);
 	}
 
@@ -4831,7 +4826,7 @@ static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
 			int sec_stage = cnt ? pstates[0].sde_pstate->stage :
 						cstate->dim_layer[0].stage;
 
-			if (!sde_kms->catalog->has_base_layer)
+			if (!test_bit(SDE_FEATURE_BASE_LAYER, sde_kms->catalog->features))
 				sec_stage -= SDE_STAGE_0;
 
 			if ((!cnt && !cstate->num_dim_layers) ||
@@ -5071,7 +5066,7 @@ static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
 		blend_type = sde_plane_get_property(pstates[*cnt].sde_pstate,
 			PLANE_PROP_BLEND_OP);
 
-		if (!kms->catalog->has_base_layer)
+		if (!test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features))
 			inc_sde_stage = SDE_STAGE_0;
 
 		/* check dim layer stage with every plane */
@@ -5230,7 +5225,7 @@ static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
 		rc = _sde_crtc_noise_layer_check_zpos(cstate, z_pos);
 		if (rc)
 			break;
-		if (!kms->catalog->has_base_layer)
+		if (!test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features))
 			pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
 		else
 			pstates[i].sde_pstate->stage = z_pos;
@@ -5715,11 +5710,13 @@ static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
 					"smart_dma_rev", "smart_dma_v2p5");
 	}
 
-	sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
+	sde_kms_info_add_keyint(info, "has_src_split", test_bit(SDE_FEATURE_SRC_SPLIT,
-	sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
+								catalog->features));
-	sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
+	sde_kms_info_add_keyint(info, "has_hdr", test_bit(SDE_FEATURE_HDR, catalog->features));
+	sde_kms_info_add_keyint(info, "has_hdr_plus", test_bit(SDE_FEATURE_HDR_PLUS,
+							       catalog->features));
 	sde_kms_info_add_keyint(info, "skip_inline_rot_threshold",
-			catalog->skip_inline_rot_threshold);
+				test_bit(SDE_FEATURE_INLINE_SKIP_THRESHOLD, catalog->features));
 
 	if (catalog->allowed_dsc_reservation_switch)
 		sde_kms_info_add_keyint(info, "allowed_dsc_reservation_switch",
@@ -5849,7 +5846,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 		"idle_time", 0, 0, U64_MAX, 0,
 		CRTC_PROP_IDLE_TIMEOUT);
 
-	if (catalog->has_trusted_vm_support) {
+	if (test_bit(SDE_FEATURE_TRUSTED_VM, catalog->features)) {
 		int init_idx = sde_in_trusted_vm(sde_kms) ? 1 : 0;
 
 		msm_property_install_enum(&sde_crtc->property_info,
@@ -5858,18 +5855,18 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 			CRTC_PROP_VM_REQ_STATE);
 	}
 
-	if (catalog->has_idle_pc)
+	if (test_bit(SDE_FEATURE_IDLE_PC, catalog->features))
 		msm_property_install_enum(&sde_crtc->property_info,
 			"idle_pc_state", 0x0, 0, e_idle_pc_state,
 			ARRAY_SIZE(e_idle_pc_state), 0,
 			CRTC_PROP_IDLE_PC_STATE);
 
-	if (catalog->has_dedicated_cwb_support)
+	if (test_bit(SDE_FEATURE_DEDICATED_CWB, catalog->features))
 		msm_property_install_enum(&sde_crtc->property_info,
 				"capture_mode", 0, 0, e_dcwb_data_points,
 				ARRAY_SIZE(e_dcwb_data_points), 0,
 				CRTC_PROP_CAPTURE_OUTPUT);
-	else if (catalog->has_cwb_support)
+	else if (test_bit(SDE_FEATURE_CWB, catalog->features))
 		msm_property_install_enum(&sde_crtc->property_info,
 				"capture_mode", 0, 0, e_cwb_data_points,
 				ARRAY_SIZE(e_cwb_data_points), 0,
@@ -5883,13 +5880,13 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 			ARRAY_SIZE(e_secure_level), 0,
 			CRTC_PROP_SECURITY_LEVEL);
 
-	if (catalog->syscache_supported)
+	if (test_bit(SDE_FEATURE_SYSCACHE, catalog->features))
 		msm_property_install_enum(&sde_crtc->property_info, "cache_state",
 			0x0, 0, e_cache_state,
 			ARRAY_SIZE(e_cache_state), 0,
 			CRTC_PROP_CACHE_STATE);
 
-	if (catalog->has_dim_layer) {
+	if (test_bit(SDE_FEATURE_DIM_LAYER, catalog->features)) {
 		msm_property_install_volatile_range(&sde_crtc->property_info,
 			"dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
 		sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
@@ -5921,7 +5918,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 		DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
 
 	sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
-			 catalog->has_base_layer);
+				test_bit(SDE_FEATURE_BASE_LAYER, catalog->features));
 
 	msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
 			info->data, SDE_KMS_INFO_DATALEN(info),
@@ -5929,7 +5926,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 
 	sde_crtc_install_noise_layer_properties(sde_crtc, catalog, info);
 
-	if (catalog->has_ubwc_stats)
+	if (test_bit(SDE_FEATURE_UBWC_STATS, catalog->features))
 		msm_property_install_range(&sde_crtc->property_info, "frame_data",
 				0x0, 0, ~0, 0, CRTC_PROP_FRAME_DATA_BUF);
 
@@ -7023,7 +7020,7 @@ void sde_crtc_static_img_control(struct drm_crtc *crtc,
 		return;
 	}
 
-	if (!sde_kms->catalog->syscache_supported) {
+	if (!test_bit(SDE_FEATURE_SYSCACHE, sde_kms->catalog->features)) {
 		SDE_DEBUG("syscache not supported\n");
 		return;
 	}
@@ -7231,7 +7228,8 @@ struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
 				sde_crtc_frame_event_work);
 	}
 
-	crtc_funcs = kms->catalog->has_precise_vsync_ts ? &sde_crtc_funcs_v1 : &sde_crtc_funcs;
+	crtc_funcs = test_bit(SDE_FEATURE_HW_VSYNC_TS, kms->catalog->features) ?
+			&sde_crtc_funcs_v1 : &sde_crtc_funcs;
 	drm_crtc_init_with_planes(dev, crtc, plane, NULL, crtc_funcs, NULL);
 	drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
 
@@ -7640,7 +7638,7 @@ static void sde_cp_crtc_apply_noise(struct drm_crtc *crtc,
 	cfg.alpha_noise = cstate->layer_cfg.alpha_noise;
 	cfg.attn_factor = cstate->layer_cfg.attn_factor;
 	cfg.strength = cstate->layer_cfg.strength;
-	if (!kms->catalog->has_base_layer) {
+	if (!test_bit(SDE_FEATURE_BASE_LAYER, kms->catalog->features)) {
 		cfg.noise_blend_stage = cstate->layer_cfg.zposn + SDE_STAGE_0;
 		cfg.attn_blend_stage = cstate->layer_cfg.zposattn + SDE_STAGE_0;
 	} else {

msm/sde/sde_encoder.c

@@ -3355,7 +3355,8 @@ static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
 	 * calculate accurate vsync timestamp when available
 	 * set current time otherwise
 	 */
-	if (phy_enc->sde_kms && phy_enc->sde_kms->catalog->has_precise_vsync_ts)
+	if (phy_enc->sde_kms && test_bit(SDE_FEATURE_HW_VSYNC_TS,
+					 phy_enc->sde_kms->catalog->features))
 		ts = sde_encoder_calc_last_vsync_timestamp(drm_enc);
 	if (!ts)
 		ts = ktime_get();
@@ -3485,9 +3486,9 @@ static void sde_encoder_frame_done_callback(
 		is_cmd_mode = true;
 
 	/* get precise vsync timestamp for retire fence, if precise vsync timestamp is enabled */
-	if (sde_kms->catalog->has_precise_vsync_ts
+	if (test_bit(SDE_FEATURE_HW_VSYNC_TS, sde_kms->catalog->features) &&
-	    && (event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
+	    (event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE) &&
-	    && (!(event & (SDE_ENCODER_FRAME_EVENT_ERROR | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD))))
+	    (!(event & (SDE_ENCODER_FRAME_EVENT_ERROR | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD))))
 		ts = sde_encoder_calc_last_vsync_timestamp(drm_enc);
 
 	/*
@@ -5092,9 +5093,11 @@ static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
 
 	if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
 	    (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
-		sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
+		sde_enc->idle_pc_enabled = test_bit(SDE_FEATURE_IDLE_PC,
+						    sde_kms->catalog->features);
 
-	sde_enc->input_event_enabled = sde_kms->catalog->wakeup_with_touch;
+	sde_enc->input_event_enabled = test_bit(SDE_FEATURE_TOUCH_WAKEUP,
+						sde_kms->catalog->features);
 
 	mutex_lock(&sde_enc->enc_lock);
 	for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {

msm/sde/sde_encoder_phys_vid.c

@@ -230,7 +230,7 @@ static u32 programmable_fetch_get_num_lines(
 	if (start_of_frame_lines >= needed_prefill_lines) {
 		SDE_DEBUG_VIDENC(vid_enc,
 				"prog fetch always enabled case\n");
-		actual_vfp_lines = (m->delay_prg_fetch_start) ? 2 : 1;
+		actual_vfp_lines = (test_bit(SDE_FEATURE_DELAY_PRG_FETCH, m->features)) ? 2 : 1;
 	} else if (v_front_porch < needed_vfp_lines) {
 		/* Warn fetch needed, but not enough porch in panel config */
 		pr_warn_once
@@ -293,7 +293,7 @@ static void programmable_fetch_config(struct sde_encoder_phys *phys_enc,
 		 * Check if we need to throttle the fetch to start
 		 * from second line after the active region.
 		 */
-		if (m->delay_prg_fetch_start)
+		if (test_bit(SDE_FEATURE_DELAY_PRG_FETCH, m->features))
 			vfp_fetch_start_vsync_counter += horiz_total;
 
 		f.enable = 1;

msm/sde/sde_encoder_phys_wb.c

@@ -1876,7 +1876,7 @@ static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc)
 	 * If has_3d_merge_reset is not set, legacy reset
 	 * sequence is executed.
 	 */
-	if (hw_wb->catalog->has_3d_merge_reset) {
+	if (test_bit(SDE_FEATURE_3D_MERGE_RESET, hw_wb->catalog->features)) {
 		sde_encoder_helper_phys_disable(phys_enc, wb_enc);
 		goto exit;
 	}

msm/sde/sde_hw_catalog.c

@@ -1622,7 +1622,7 @@ static int _sde_sspp_setup_vigs(struct device_node *np,
 					MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT;
 		}
 
-		if (sde_cfg->inline_disable_const_clr)
+		if (test_bit(SDE_FEATURE_INLINE_DISABLE_CONST_CLR, sde_cfg->features))
 			set_bit(SDE_SSPP_INLINE_CONST_CLR, &sspp->features);
 
 	}
@@ -1914,7 +1914,7 @@ static void sde_sspp_set_features(struct sde_mdss_cfg *sde_cfg,
 		sblk->src_blk.id = SDE_SSPP_SRC;
 		set_bit(SDE_SSPP_SRC, &sspp->features);
 
-		if (sde_cfg->has_cdp)
+		if (test_bit(SDE_FEATURE_CDP, sde_cfg->features))
 			set_bit(SDE_PERF_SSPP_CDP, &sspp->perf_features);
 
 		if (sde_cfg->ts_prefill_rev == 1) {
@@ -1931,10 +1931,10 @@ static void sde_sspp_set_features(struct sde_mdss_cfg *sde_cfg,
 		if (sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
 			set_bit(SDE_PERF_SSPP_SYS_CACHE, &sspp->perf_features);
 
-		if (sde_cfg->sspp_multirect_error)
+		if (test_bit(SDE_FEATURE_MULTIRECT_ERROR, sde_cfg->features))
 			set_bit(SDE_SSPP_MULTIRECT_ERROR, &sspp->features);
 
-		if (sde_cfg->has_decimation) {
+		if (test_bit(SDE_FEATURE_DECIMATION, sde_cfg->features)) {
 			sblk->maxhdeciexp = MAX_HORZ_DECIMATION;
 			sblk->maxvdeciexp = MAX_VERT_DECIMATION;
 		} else {
@@ -1960,7 +1960,7 @@ static void sde_sspp_set_features(struct sde_mdss_cfg *sde_cfg,
 		else
 			sblk->max_per_pipe_bw_high = sblk->max_per_pipe_bw;
 
-		if (sde_cfg->has_ubwc_stats)
+		if (test_bit(SDE_FEATURE_UBWC_STATS, sde_cfg->features))
 			set_bit(SDE_SSPP_UBWC_STATS, &sspp->features);
 	}
 }
@@ -2286,11 +2286,11 @@ static int sde_mixer_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_c
 				PROP_VALUE_ACCESS(blend_props->values,
 						MIXER_BLEND_OP_OFF, j);
 
-		if (sde_cfg->has_src_split)
+		if (test_bit(SDE_FEATURE_SRC_SPLIT, sde_cfg->features))
 			set_bit(SDE_MIXER_SOURCESPLIT, &mixer->features);
-		if (sde_cfg->has_dim_layer)
+		if (test_bit(SDE_FEATURE_DIM_LAYER, sde_cfg->features))
 			set_bit(SDE_DIM_LAYER, &mixer->features);
-		if (sde_cfg->has_mixer_combined_alpha)
+		if (test_bit(SDE_FEATURE_COMBINED_ALPHA, sde_cfg->features))
 			set_bit(SDE_MIXER_COMBINED_ALPHA, &mixer->features);
 
 		of_property_read_string_index(np,
@@ -2545,17 +2545,17 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		set_bit(SDE_WB_TRAFFIC_SHAPER, &wb->features);
 		set_bit(SDE_WB_YUV_CONFIG, &wb->features);
 
-		if (sde_cfg->has_cdp)
+		if (test_bit(SDE_FEATURE_CDP, sde_cfg->features))
 			set_bit(SDE_WB_CDP, &wb->features);
 
 		set_bit(SDE_WB_QOS, &wb->features);
 		if (sde_cfg->vbif_qos_nlvl == 8)
 			set_bit(SDE_WB_QOS_8LVL, &wb->features);
 
-		if (sde_cfg->has_wb_ubwc)
+		if (test_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features))
 			set_bit(SDE_WB_UBWC, &wb->features);
 
-		if (sde_cfg->has_cwb_crop)
+		if (test_bit(SDE_FEATURE_CWB_CROP, sde_cfg->features))
 			set_bit(SDE_WB_CROP, &wb->features);
 
 		set_bit(SDE_WB_XY_ROI_OFFSET, &wb->features);
@@ -2563,7 +2563,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
 			set_bit(SDE_WB_INPUT_CTRL, &wb->features);
 
-		if (sde_cfg->has_dedicated_cwb_support) {
+		if (test_bit(SDE_FEATURE_DEDICATED_CWB, sde_cfg->features)) {
 			set_bit(SDE_WB_HAS_DCWB, &wb->features);
 			if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
 				set_bit(SDE_WB_DCWB_CTRL, &wb->features);
@@ -2575,10 +2575,10 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 				sde_cfg->cwb_blk_stride = 0x100;
 			}
 
-			if (sde_cfg->has_cwb_dither)
+			if (test_bit(SDE_FEATURE_CWB_DITHER, sde_cfg->features))
 				set_bit(SDE_WB_CWB_DITHER_CTRL, &wb->features);
 
-		} else if (sde_cfg->has_cwb_support) {
+		} else if (test_bit(SDE_FEATURE_CWB, sde_cfg->features)) {
 			set_bit(SDE_WB_HAS_CWB, &wb->features);
 			if (IS_SDE_CTL_REV_100(sde_cfg->ctl_rev))
 				set_bit(SDE_WB_CWB_CTRL, &wb->features);
@@ -3496,7 +3496,7 @@ static int sde_cache_parse_dt(struct device_node *np,
 		return -EINVAL;
 	}
 
-	if (!sde_cfg->syscache_supported)
+	if (!test_bit(SDE_FEATURE_SYSCACHE, sde_cfg->features))
 		return 0;
 
 	llcc_node = of_find_node_by_name(NULL, "cache-controller");
@@ -3675,7 +3675,7 @@ static int _sde_vbif_populate(struct sde_mdss_cfg *sde_cfg,
 	for (j = 0; j < prop_count[VBIF_MEMTYPE_1]; j++)
 		vbif->memtype[k++] = PROP_VALUE_ACCESS(
 				prop_value, VBIF_MEMTYPE_1, j);
-	if (sde_cfg->vbif_disable_inner_outer_shareable)
+	if (test_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features))
 		set_bit(SDE_VBIF_DISABLE_SHAREABLE, &vbif->features);
 
 	return 0;
@@ -3844,7 +3844,7 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 
 		if (PROP_VALUE_ACCESS(prop_value, PP_CWB, i)) {
 			set_bit(SDE_PINGPONG_CWB, &pp->features);
-			if (sde_cfg->has_dedicated_cwb_support)
+			if (test_bit(SDE_FEATURE_DEDICATED_CWB, sde_cfg->features))
 				sde_cfg->dcwb_count++;
 		}
 
@@ -3872,12 +3872,12 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg)
 		sblk->dither.version = PROP_VALUE_ACCESS(prop_value, DITHER_VER,
 								0);
 
-		if (sde_cfg->has_cwb_dither &&
+		if (test_bit(SDE_FEATURE_CWB_DITHER, sde_cfg->features) &&
 		    PROP_VALUE_ACCESS(prop_value, CWB_DITHER, i)) {
 			set_bit(SDE_PINGPONG_CWB_DITHER, &pp->features);
 		}
 
-		if (sde_cfg->dither_luma_mode_support)
+		if (test_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features))
 			set_bit(SDE_PINGPONG_DITHER_LUMA, &pp->features);
 
 		if (prop_exists[PP_MERGE_3D_ID]) {
@@ -3972,18 +3972,21 @@ static void _sde_top_parse_dt_helper(struct sde_mdss_cfg *cfg,
 					SEC_SID_MASK, i);
 	}
 
-	cfg->has_src_split = PROP_VALUE_ACCESS(props->values, SRC_SPLIT, 0);
+	if (PROP_VALUE_ACCESS(props->values, SRC_SPLIT, 0))
-	cfg->has_dim_layer = PROP_VALUE_ACCESS(props->values, DIM_LAYER, 0);
+		set_bit(SDE_FEATURE_SRC_SPLIT, cfg->features);
-	cfg->has_idle_pc = PROP_VALUE_ACCESS(props->values, IDLE_PC, 0);
+	if (PROP_VALUE_ACCESS(props->values, DIM_LAYER, 0))
-	cfg->wakeup_with_touch = PROP_VALUE_ACCESS(props->values,
+		set_bit(SDE_FEATURE_DIM_LAYER, cfg->features);
-			WAKEUP_WITH_TOUCH, 0);
+	if (PROP_VALUE_ACCESS(props->values, IDLE_PC, 0))
+		set_bit(SDE_FEATURE_IDLE_PC, cfg->features);
+	if (PROP_VALUE_ACCESS(props->values, WAKEUP_WITH_TOUCH, 0))
+		set_bit(SDE_FEATURE_TOUCH_WAKEUP, cfg->features);
 	cfg->pipe_order_type = PROP_VALUE_ACCESS(props->values,
 			PIPE_ORDER_VERSION, 0);
-	cfg->has_base_layer = PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0);
+	if (PROP_VALUE_ACCESS(props->values, BASE_LAYER, 0))
+		set_bit(SDE_FEATURE_BASE_LAYER, cfg->features);
 	cfg->qseed_hw_version = PROP_VALUE_ACCESS(props->values,
 			 QSEED_HW_VERSION, 0);
-	cfg->trusted_vm_env = PROP_VALUE_ACCESS(props->values, TRUSTED_VM_ENV,
+	cfg->trusted_vm_env = PROP_VALUE_ACCESS(props->values, TRUSTED_VM_ENV, 0);
-			 0);
 	cfg->max_trusted_vm_displays = PROP_VALUE_ACCESS(props->values,
 			MAX_TRUSTED_VM_DISPLAYS, 0);
 	if (props->exists[TVM_INCLUDE_REG]) {
@@ -4413,7 +4416,7 @@ static int _sde_perf_parse_dt_cfg(struct device_node *np,
 				cfg->perf.cdp_cfg[j].wr_enable);
 		}
 
-		cfg->has_cdp = true;
+		set_bit(SDE_FEATURE_CDP, cfg->features);
 	}
 
 	cfg->perf.cpu_mask =
@@ -4612,7 +4615,7 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
 	const struct sde_format_extended *inline_restricted_fmt_tbl = NULL;
 
 	/* cursor input formats */
-	if (sde_cfg->has_cursor) {
+	if (test_bit(SDE_FEATURE_CURSOR, sde_cfg->features)) {
 		cursor_list_size = ARRAY_SIZE(cursor_formats);
 		sde_cfg->cursor_formats = kcalloc(cursor_list_size,
 			sizeof(struct sde_format_extended), GFP_KERNEL);
@@ -4627,7 +4630,7 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
 
 	/* DMA pipe input formats */
 	dma_list_size = ARRAY_SIZE(plane_formats);
-	if (sde_cfg->has_fp16)
+	if (test_bit(SDE_FEATURE_FP16, sde_cfg->features))
 		dma_list_size += ARRAY_SIZE(fp16_formats);
 
 	sde_cfg->dma_formats = kcalloc(dma_list_size,
@@ -4639,15 +4642,15 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
 
 	index = sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
 			0, plane_formats, ARRAY_SIZE(plane_formats));
-	if (sde_cfg->has_fp16)
+	if (test_bit(SDE_FEATURE_FP16, sde_cfg->features))
 		index += sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
 			index, fp16_formats, ARRAY_SIZE(fp16_formats));
 
 	/* ViG pipe input formats */
 	vig_list_size = ARRAY_SIZE(plane_formats_vig);
-	if (sde_cfg->has_vig_p010)
+	if (test_bit(SDE_FEATURE_VIG_P010, sde_cfg->features))
 		vig_list_size += ARRAY_SIZE(p010_ubwc_formats);
-	if (sde_cfg->has_fp16)
+	if (test_bit(SDE_FEATURE_FP16, sde_cfg->features))
 		vig_list_size += ARRAY_SIZE(fp16_formats);
 
 	sde_cfg->vig_formats = kcalloc(vig_list_size,
@@ -4659,17 +4662,17 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
 
 	index = sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
 			0, plane_formats_vig, ARRAY_SIZE(plane_formats_vig));
-	if (sde_cfg->has_vig_p010)
+	if (test_bit(SDE_FEATURE_VIG_P010, sde_cfg->features))
 		index += sde_copy_formats(sde_cfg->vig_formats,
 				vig_list_size, index, p010_ubwc_formats,
 				ARRAY_SIZE(p010_ubwc_formats));
-	if (sde_cfg->has_fp16)
+	if (test_bit(SDE_FEATURE_FP16, sde_cfg->features))
 		index += sde_copy_formats(sde_cfg->vig_formats, vig_list_size,
 			index, fp16_formats, ARRAY_SIZE(fp16_formats));
 
 	/* Virtual ViG pipe input formats (all virt pipes use DMA formats) */
 	virt_vig_list_size = ARRAY_SIZE(plane_formats);
-	if (sde_cfg->has_fp16)
+	if (test_bit(SDE_FEATURE_FP16, sde_cfg->features))
 		virt_vig_list_size += ARRAY_SIZE(fp16_formats);
 
 	sde_cfg->virt_vig_formats = kcalloc(virt_vig_list_size,
@@ -4681,7 +4684,7 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
 
 	index = sde_copy_formats(sde_cfg->virt_vig_formats, virt_vig_list_size,
 			0, plane_formats, ARRAY_SIZE(plane_formats));
-	if (sde_cfg->has_fp16)
+	if (test_bit(SDE_FEATURE_FP16, sde_cfg->features))
 		index += sde_copy_formats(sde_cfg->virt_vig_formats,
 				virt_vig_list_size, index, fp16_formats,
 				ARRAY_SIZE(fp16_formats));
@@ -4752,7 +4755,7 @@ free_vig:
 free_dma:
 	kfree(sde_cfg->dma_formats);
 free_cursor:
-	if (sde_cfg->has_cursor)
+	if (test_bit(SDE_FEATURE_CURSOR, sde_cfg->features))
 		kfree(sde_cfg->cursor_formats);
 out:
 	return rc;
@@ -4810,7 +4813,12 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		return -EINVAL;
 
 	/* default settings for *MOST* targets */
-	sde_cfg->has_mixer_combined_alpha = true;
+	set_bit(SDE_FEATURE_COMBINED_ALPHA, sde_cfg->features);
+	set_bit(SDE_FEATURE_DELAY_PRG_FETCH, sde_cfg->features);
+	set_bit(SDE_FEATURE_SUI_MISR, sde_cfg->features);
+	set_bit(SDE_FEATURE_SUI_BLENDSTAGE, sde_cfg->features);
+	set_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_cfg->features);
+	set_bit(SDE_FEATURE_HDR, sde_cfg->features);
 	sde_cfg->mdss_hw_block_size = DEFAULT_MDSS_HW_BLOCK_SIZE;
 
 	for (i = 0; i < SSPP_MAX; i++) {
@@ -4821,326 +4829,271 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 	/* target specific settings */
 	if (IS_MSM8996_TARGET(hw_rev)) {
 		sde_cfg->perf.min_prefill_lines = 21;
-		sde_cfg->has_decimation = true;
+		set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
-		sde_cfg->has_mixer_combined_alpha = false;
+		clear_bit(SDE_FEATURE_COMBINED_ALPHA, sde_cfg->features);
+		clear_bit(SDE_FEATURE_HDR, sde_cfg->features);
+		clear_bit(SDE_FEATURE_DELAY_PRG_FETCH, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_MISR, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_BLENDSTAGE, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_cfg->features);
 	} else if (IS_MSM8998_TARGET(hw_rev)) {
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 25;
 		sde_cfg->vbif_qos_nlvl = 4;
 		sde_cfg->ts_prefill_rev = 1;
-		sde_cfg->has_decimation = true;
+		set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
-		sde_cfg->has_cursor = true;
+		set_bit(SDE_FEATURE_CURSOR, sde_cfg->features);
-		sde_cfg->has_hdr = true;
+		clear_bit(SDE_FEATURE_COMBINED_ALPHA, sde_cfg->features);
-		sde_cfg->has_mixer_combined_alpha = false;
+		clear_bit(SDE_FEATURE_DELAY_PRG_FETCH, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_MISR, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_BLENDSTAGE, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_cfg->features);
 	} else if (IS_SDM845_TARGET(hw_rev)) {
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x3F71;
-		sde_cfg->has_decimation = true;
+		set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
-		sde_cfg->has_hdr = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
-		sde_cfg->has_vig_p010 = true;
+		clear_bit(SDE_FEATURE_DELAY_PRG_FETCH, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_BLENDSTAGE, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_cfg->features);
 	} else if (IS_SDM670_TARGET(hw_rev)) {
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
-		sde_cfg->has_decimation = true;
+		set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
-		sde_cfg->has_hdr = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
-		sde_cfg->has_vig_p010 = true;
+		clear_bit(SDE_FEATURE_DELAY_PRG_FETCH, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_MISR, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_BLENDSTAGE, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_cfg->features);
 	} else if (IS_SM8150_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
-		sde_cfg->has_hdr = true;
+		set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
-		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
-		sde_cfg->has_vig_p010 = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x3F71;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
-		sde_cfg->has_decimation = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
 	} else if (IS_SDMSHRIKE_TARGET(hw_rev)) {
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
+		set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
-		sde_cfg->has_decimation = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
-		sde_cfg->has_hdr = true;
+		clear_bit(SDE_FEATURE_SUI_MISR, sde_cfg->features);
-		sde_cfg->has_vig_p010 = true;
+		clear_bit(SDE_FEATURE_SUI_BLENDSTAGE, sde_cfg->features);
+		clear_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_cfg->features);
 	} else if (IS_SM6150_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
+		set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
-		sde_cfg->has_decimation = true;
 		sde_cfg->sui_block_xin_mask = 0x2EE1;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
-		sde_cfg->has_hdr = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->has_vig_p010 = true;
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
 	} else if (IS_SDMMAGPIE_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
+		clear_bit(SDE_FEATURE_HDR, sde_cfg->features);
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0xE71;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
 	} else if (IS_KONA_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 35;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x3F71;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
-		sde_cfg->has_hdr = true;
-		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
-		sde_cfg->has_vig_p010 = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
 		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;
 		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_0;
-		sde_cfg->inline_disable_const_clr = true;
+		set_bit(SDE_FEATURE_INLINE_DISABLE_CONST_CLR, sde_cfg->features);
 	} else if (IS_SAIPAN_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 40;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0xE71;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
-		sde_cfg->has_hdr = true;
-		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
-		sde_cfg->has_vig_p010 = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
 		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;
-		sde_cfg->inline_disable_const_clr = true;
+		set_bit(SDE_FEATURE_INLINE_DISABLE_CONST_CLR, sde_cfg->features);
 	} else if (IS_SDMTRINKET_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0xC61;
-		sde_cfg->has_hdr = false;
+		clear_bit(SDE_FEATURE_HDR, sde_cfg->features);
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
 	} else if (IS_BENGAL_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = false;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0xC01;
-		sde_cfg->has_hdr = false;
+		clear_bit(SDE_FEATURE_HDR, sde_cfg->features);
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
 	} else if (IS_LAGOON_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 40;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x261;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
-		sde_cfg->has_hdr = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->has_vig_p010 = true;
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
 	} else if (IS_SCUBA_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = false;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x1;
-		sde_cfg->has_hdr = false;
+		clear_bit(SDE_FEATURE_HDR, sde_cfg->features);
-		sde_cfg->has_sui_blendstage = true;
 	} else if (IS_LAHAINA_TARGET(hw_rev)) {
-		sde_cfg->has_demura = true;
+		set_bit(SDE_FEATURE_DEMURA, sde_cfg->features);
 		sde_cfg->demura_supported[SSPP_DMA1][0] = 0;
 		sde_cfg->demura_supported[SSPP_DMA1][1] = 1;
 		sde_cfg->demura_supported[SSPP_DMA3][0] = 0;
 		sde_cfg->demura_supported[SSPP_DMA3][1] = 1;
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 40;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x3F71;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
-		sde_cfg->has_hdr = true;
-		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features);
-		sde_cfg->has_vig_p010 = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
 		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0;
 		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_1;
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->dither_luma_mode_support = true;
+		set_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
-		sde_cfg->has_trusted_vm_support = true;
+		set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
-		sde_cfg->syscache_supported = true;
+		set_bit(SDE_FEATURE_SYSCACHE, sde_cfg->features);
 	} else if (IS_HOLI_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = false;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0xC01;
-		sde_cfg->has_hdr = false;
+		clear_bit(SDE_FEATURE_HDR, sde_cfg->features);
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
 		sde_cfg->mdss_hw_block_size = 0x158;
-		sde_cfg->rc_lm_flush_override = true;
+		set_bit(SDE_FEATURE_RC_LM_FLUSH_OVERRIDE, sde_cfg->features);
 	} else if (IS_SHIMA_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 35;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0xE71;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
-		sde_cfg->has_hdr = true;
-		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
-		sde_cfg->has_vig_p010 = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
 		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;
-		sde_cfg->inline_disable_const_clr = true;
+		set_bit(SDE_FEATURE_INLINE_DISABLE_CONST_CLR, sde_cfg->features);
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
-		sde_cfg->has_trusted_vm_support = true;
+		set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
-		sde_cfg->syscache_supported = true;
+		set_bit(SDE_FEATURE_SYSCACHE, sde_cfg->features);
 	} else if (IS_WAIPIO_TARGET(hw_rev)) {
 		sde_cfg->allowed_dsc_reservation_switch = SDE_DP_DSC_RESERVATION_SWITCH;
-		sde_cfg->has_dedicated_cwb_support = true;
+		set_bit(SDE_FEATURE_DEDICATED_CWB, sde_cfg->features);
-		sde_cfg->has_cwb_dither = true;
+		set_bit(SDE_FEATURE_CWB_DITHER, sde_cfg->features);
-		sde_cfg->has_wb_ubwc = true;
+		set_bit(SDE_FEATURE_WB_UBWC, sde_cfg->features);
-		sde_cfg->has_cwb_crop = true;
+		set_bit(SDE_FEATURE_CWB_CROP, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 40;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->sui_ns_allowed = true;
+		set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
-		sde_cfg->sui_misr_supported = true;
+		set_bit(SDE_FEATURE_INLINE_SKIP_THRESHOLD, sde_cfg->features);
-		sde_cfg->has_sui_blendstage = true;
-		sde_cfg->has_3d_merge_reset = true;
-		sde_cfg->has_hdr = true;
-		sde_cfg->has_hdr_plus = true;
-		sde_cfg->skip_inline_rot_threshold = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features);
-		sde_cfg->has_vig_p010 = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
 		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_1;
 		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_2;
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->dither_luma_mode_support = true;
+		set_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
-		sde_cfg->syscache_supported = true;
+		set_bit(SDE_FEATURE_SYSCACHE, sde_cfg->features);
-		sde_cfg->sspp_multirect_error = true;
+		set_bit(SDE_FEATURE_MULTIRECT_ERROR, sde_cfg->features);
-		sde_cfg->has_fp16 = true;
+		set_bit(SDE_FEATURE_FP16, sde_cfg->features);
 		set_bit(SDE_MDP_PERIPH_TOP_0_REMOVED, &sde_cfg->mdp[0].features);
-		sde_cfg->has_precise_vsync_ts = true;
+		set_bit(SDE_FEATURE_DEMURA, sde_cfg->features);
-		sde_cfg->has_avr_step = true;
-		sde_cfg->has_trusted_vm_support = true;
-		sde_cfg->has_ubwc_stats = true;
-		sde_cfg->has_demura = true;
 		sde_cfg->demura_supported[SSPP_DMA1][0] = 0;
 		sde_cfg->demura_supported[SSPP_DMA1][1] = 1;
 		sde_cfg->demura_supported[SSPP_DMA3][0] = 0;
 		sde_cfg->demura_supported[SSPP_DMA3][1] = 1;
+		set_bit(SDE_FEATURE_UBWC_STATS, sde_cfg->features);
+		set_bit(SDE_FEATURE_HW_VSYNC_TS, sde_cfg->features);
+		set_bit(SDE_FEATURE_AVR_STEP, sde_cfg->features);
+		set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
 	} else if (IS_YUPIK_TARGET(hw_rev)) {
-		sde_cfg->has_cwb_support = true;
+		set_bit(SDE_FEATURE_CWB, sde_cfg->features);
-		sde_cfg->has_qsync = true;
+		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 40;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
-		sde_cfg->delay_prg_fetch_start = true;
-		sde_cfg->sui_ns_allowed = true;
-		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x261;
-		sde_cfg->has_sui_blendstage = true;
+		set_bit(SDE_FEATURE_3D_MERGE_RESET, sde_cfg->features);
-		sde_cfg->has_3d_merge_reset = true;
+		set_bit(SDE_FEATURE_HDR_PLUS, sde_cfg->features);
-		sde_cfg->has_hdr = true;
-		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features);
-		sde_cfg->has_vig_p010 = true;
+		set_bit(SDE_FEATURE_VIG_P010, sde_cfg->features);
 		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0;
-		sde_cfg->vbif_disable_inner_outer_shareable = true;
+		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
-		sde_cfg->dither_luma_mode_support = true;
+		set_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
-		sde_cfg->rc_lm_flush_override = false;
 	} else {
 		SDE_ERROR("unsupported chipset id:%X\n", hw_rev);
 		sde_cfg->perf.min_prefill_lines = 0xffff;
@@ -5164,9 +5117,8 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg,
 	if (!sde_cfg)
 		return -EINVAL;
 
-	if (sde_cfg->has_sui_blendstage)
+	if (test_bit(SDE_FEATURE_SUI_BLENDSTAGE, sde_cfg->features))
-		sde_cfg->sui_supported_blendstage =
+		sde_cfg->sui_supported_blendstage = sde_cfg->max_mixer_blendstages - SDE_STAGE_0;
-			sde_cfg->max_mixer_blendstages - SDE_STAGE_0;
 
 	for (i = 0; i < sde_cfg->sspp_count; i++) {
 		if (sde_cfg->sspp[i].sblk) {
@@ -5180,11 +5132,9 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg,
 		 * set sec-ui blocked SSPP feature flag based on blocked
 		 * xin-mask if sec-ui-misr feature is enabled;
 		 */
-		if (sde_cfg->sui_misr_supported
+		if (test_bit(SDE_FEATURE_SUI_MISR, sde_cfg->features) &&
-				&& (sde_cfg->sui_block_xin_mask
+		    (sde_cfg->sui_block_xin_mask & BIT(sde_cfg->sspp[i].xin_id)))
-					& BIT(sde_cfg->sspp[i].xin_id)))
+			set_bit(SDE_SSPP_BLOCK_SEC_UI, &sde_cfg->sspp[i].features);
-			set_bit(SDE_SSPP_BLOCK_SEC_UI,
-					&sde_cfg->sspp[i].features);
 	}
 
 	if (max_horz_deci)

msm/sde/sde_hw_catalog.h

@@ -617,6 +617,86 @@ enum {
 	SDE_UIDLE_MAX
 };
 
+/**
+ * MDSS features - For enabling target specific functionality in @sde_mdss_cfg "features" bitmap
+ * @SDE_FEATURE_CDP            Client driven prefetch supported
+ * @SDE_FEATURE_DIM_LAYER      Dim Layer supported
+ * @SDE_FEATURE_WB_UBWC        UBWC supported on Writeback
+ * @SDE_FEATURE_CWB            Concurrent Writeback supported
+ * @SDE_FEATURE_CWB_CROP       CWB Cropping supported
+ * @SDE_FEATURE_CWB_DITHER     CWB dither is supported
+ * @SDE_FEATURE_DEDICATED_CWB  Dedicated-CWB supported
+ * @SDE_FEATURE_IDLE_PC        Idle Power Collapse supported
+ * @SDE_FEATURE_3D_MERGE_RESET 3D merge reset supported
+ * @SDE_FEATURE_DECIMATION     Decimation supported
+ * @SDE_FEATURE_COMBINED_ALPHA Combined Alpha supported
+ * @SDE_FEATURE_BASE_LAYER     Base Layer supported
+ * @SDE_FEATURE_TOUCH_WAKEUP   Early wakeup with touch supported
+ * @SDE_FEATURE_SRC_SPLIT      Source split supported
+ * @SDE_FEATURE_CURSOR         Cursor supported
+ * @SDE_FEATURE_VIG_P010       P010 ViG pipe format supported
+ * @SDE_FEATURE_FP16           FP16 pipe format supported
+ * @SDE_FEATURE_HDR            High Dynamic Range supported
+ * @SDE_FEATURE_HDR_PLUS       HDR10+ supported
+ * @SDE_FEATURE_QSYNC          QSYNC supported
+ * @SDE_FEATURE_AVR_STEP       AVR Step supported
+ * @SDE_FEATURE_DEMURA         Demura supported
+ * @SDE_FEATURE_HW_VSYNC_TS    HW timestamp supported
+ * @SDE_FEATURE_MULTIRECT_ERROR            Multirect Error supported
+ * @SDE_FEATURE_DELAY_PRG_FETCH            Delay programmable fetch supported
+ * @SDE_FEATURE_VBIF_DISABLE_SHAREABLE     VBIF disable inner/outer shareable required
+ * @SDE_FEATURE_INLINE_DISABLE_CONST_CLR   Inline rotation disable constant color required
+ * @SDE_FEATURE_INLINE_SKIP_THRESHOLD      Skip inline rotation threshold
+ * @SDE_FEATURE_DITHER_LUMA_MODE           Dither LUMA mode supported
+ * @SDE_FEATURE_RC_LM_FLUSH_OVERRIDE       RC LM flush override supported
+ * @SDE_FEATURE_SYSCACHE       System cache supported
+ * @SDE_FEATURE_SUI_MISR       SecureUI MISR supported
+ * @SDE_FEATURE_SUI_BLENDSTAGE SecureUI Blendstage supported
+ * @SDE_FEATURE_SUI_NS_ALLOWED SecureUI allowed to access non-secure context banks
+ * @SDE_FEATURE_TRUSTED_VM     Trusted VM supported
+ * @SDE_FEATURE_UBWC_STATS     UBWC statistics supported
+ * @SDE_FEATURE_MAX:             MAX features value
+ */
+enum sde_mdss_features {
+	SDE_FEATURE_CDP,
+	SDE_FEATURE_DIM_LAYER,
+	SDE_FEATURE_WB_UBWC,
+	SDE_FEATURE_CWB,
+	SDE_FEATURE_CWB_CROP,
+	SDE_FEATURE_CWB_DITHER,
+	SDE_FEATURE_DEDICATED_CWB,
+	SDE_FEATURE_IDLE_PC,
+	SDE_FEATURE_3D_MERGE_RESET,
+	SDE_FEATURE_DECIMATION,
+	SDE_FEATURE_COMBINED_ALPHA,
+	SDE_FEATURE_BASE_LAYER,
+	SDE_FEATURE_TOUCH_WAKEUP,
+	SDE_FEATURE_SRC_SPLIT,
+	SDE_FEATURE_CURSOR,
+	SDE_FEATURE_VIG_P010,
+	SDE_FEATURE_FP16,
+	SDE_FEATURE_HDR,
+	SDE_FEATURE_HDR_PLUS,
+	SDE_FEATURE_QSYNC,
+	SDE_FEATURE_AVR_STEP,
+	SDE_FEATURE_DEMURA,
+	SDE_FEATURE_HW_VSYNC_TS,
+	SDE_FEATURE_MULTIRECT_ERROR,
+	SDE_FEATURE_DELAY_PRG_FETCH,
+	SDE_FEATURE_VBIF_DISABLE_SHAREABLE,
+	SDE_FEATURE_INLINE_DISABLE_CONST_CLR,
+	SDE_FEATURE_INLINE_SKIP_THRESHOLD,
+	SDE_FEATURE_DITHER_LUMA_MODE,
+	SDE_FEATURE_RC_LM_FLUSH_OVERRIDE,
+	SDE_FEATURE_SYSCACHE,
+	SDE_FEATURE_SUI_MISR,
+	SDE_FEATURE_SUI_BLENDSTAGE,
+	SDE_FEATURE_SUI_NS_ALLOWED,
+	SDE_FEATURE_TRUSTED_VM,
+	SDE_FEATURE_UBWC_STATS,
+	SDE_FEATURE_MAX
+};
+
 /**
  * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE
  * @name:              string name for debug purposes
@@ -1475,252 +1555,198 @@ struct sde_perf_cfg {
  * struct sde_mdss_cfg - information of MDSS HW
  * This is the main catalog data structure representing
  * this HW version. Contains number of instances,
- * register offsets, capabilities of the all MDSS HW sub-blocks.
+ * register offsets, capabilities of all the MDSS HW sub-blocks.
  *
- * @trusted_vm_env	set to true, if the driver is executing in
+ * @hwversion           MDSS HW version
- *			the trusted VM. false, otherwise.
- * @max_trusted_vm_displays	maximum number of concurrent trusted
- *				vm displays supported.
- * @tvm_reg_count		number of sub-driver register ranges that need to be included
- *						for trusted vm for accepting the resources
- * @tvm_reg				array of sub-driver register ranges entries that need to be
- *						included
- * @max_sspp_linewidth max source pipe line width support.
- * @vig_sspp_linewidth max vig source pipe line width support.
- * @scaling_linewidth max vig source pipe linewidth for scaling usecases
- * @max_mixer_width    max layer mixer line width support.
- * @max_dsc_width      max dsc line width support.
- * @max_mixer_blendstages max layer mixer blend stages or
- *                       supported z order
- * @max_wb_linewidth   max writeback line width support.
- * @max_wb_linewidth_linear   max writeback line width for linear formats.
- * @max_display_width   maximum display width support.
- * @max_display_height  maximum display height support.
-
- * @min_display_width   minimum display width support.
- * @min_display_height  minimum display height support.
- * @csc_type           csc or csc_10bit support.
- * @smart_dma_rev      Supported version of SmartDMA feature.
- * @ctl_rev            supported version of control path.
- * @has_src_split      source split feature status
- * @has_cdp            Client driven prefetch feature status
- * @has_wb_ubwc        UBWC feature supported on WB
- * @has_cwb_crop       CWB cropping is supported
- * @has_cwb_support    indicates if device supports primary capture through CWB
- * @has_dedicated_cwb_support    indicates if device supports dedicated path for CWB capture
- * @has_cwb_dither     indicates if device supports cwb dither feature
- * @cwb_blk_off        CWB offset address
- * @cwb_blk_stride     offset between each CWB blk
  * @ubwc_version        UBWC feature version (0x0 for not supported)
- * @ubwc_bw_calc_version indicate how UBWC BW has to be calculated
+ * @ubwc_bw_calc_version        indicates how UBWC BW has to be calculated
- * @skip_inline_rot_thresh    Skip inline rotation threshold
+ * @qseed_sw_lib_rev    qseed SW library version
- * @has_idle_pc        indicate if idle power collapse feature is supported
+ * @qseed_hw_version    qseed HW block version
- * @allowed_dsc_reservation_switch  intf to which dsc reservation switch is supported
+ * @smart_dma_rev       smartDMA block version
- * @wakeup_with_touch  indicate early wake up display with input touch event
+ * @ctl_rev             control path block version
- * @has_hdr            HDR feature support
- * @has_hdr_plus       HDR10+ feature support
- * @dma_formats        Supported formats for dma pipe
- * @cursor_formats     Supported formats for cursor pipe
- * @vig_formats        Supported formats for vig pipe
- * @wb_formats         Supported formats for wb
- * @virt_vig_formats   Supported formats for virtual vig pipe
- * @vbif_qos_nlvl      number of vbif QoS priority level
  * @ts_prefill_rev      prefill traffic shaper feature revision
  * @true_inline_rot_rev inline rotator feature revision
- * @macrotile_mode     UBWC parameter for macro tile channel distribution
+ * @mdss_count          number of valid MDSS HW blocks
- * @pipe_order_type    indicate if it is required to specify pipe order
+ * @mdss                array of pointers to MDSS HW blocks
- * @sspp_multirect_error flag to indicate whether ubwc and meta error by rect is supported
+ * @mdss_hw_block_size  max offset of MDSS_HW block (0 offset), used for debug
- * @delay_prg_fetch_start indicates if throttling the fetch start is required
+ * @mdp_count           number of valid MDP HW blocks
- * @has_qsync	       Supports qsync feature
+ * @mdp                 array of pointers to MDP HW blocks
- * @has_3d_merge_reset Supports 3D merge reset
+ * @ctl_count           number of valid CTL blocks available
- * @has_decimation     Supports decimation
+ * @ctl                 array of pointers to CTL blocks
- * @has_trusted_vm_support	     Supported HW sharing with trusted VM
+ * @sspp_count          number of valid SSPP blocks available
- * @has_avr_step       Supports AVR with vsync alignment to a set step rate
+ * @sspp                array of pointers to SSPP blocks
- * @rc_lm_flush_override        Support Rounded Corner using layer mixer flush
+ * @mixer_count         number of valid LM blocks available
- * @has_mixer_combined_alpha     Mixer has single register for FG & BG alpha
+ * @mixer               array of pointers to LM blocks
- * @vbif_disable_inner_outer_shareable     VBIF requires disabling shareables
+ * @dspp_top            pointer to common DSPP_TOP block
- * @inline_disable_const_clr     Disable constant color during inline rotate
+ * @dspp_count          number of valid DSPP blocks available
- * @dither_luma_mode_support   Enables dither luma mode
+ * @dspp                array of pointers to DSPP blocks
- * @has_base_layer     Supports staging layer as base layer
+ * @ds_count            number of valid dest scaler blocks available
- * @demura_supported   Demura pipe support flag(~0x00 - Not supported)
+ * @ds                  array of pointers to DS blocks
- * @qseed_sw_lib_rev	qseed sw library type supporting the qseed hw
+ * @pingpong_count      number of valid pingpong blocks available
- * @qseed_hw_version   qseed hw version of the target
+ * @pingpong            array of pointers to pingpong blocks
- * @sc_cfg: system cache configuration
+ * @dsc_count           number of valid DSC blocks available
- * @syscache_supported  Flag to indicate if sys cache support is enabled
+ * @dsc                 array of pointers to DSC blocks
- * @uidle_cfg		Settings for uidle feature
+ * @vdc_count           number of valid VDC blocks available
- * @sui_misr_supported  indicate if secure-ui-misr is supported
+ * @vdc                 array of pointers to VDC blocks
- * @sui_block_xin_mask  mask of all the xin-clients to be blocked during
+ * @cdm_count           number of valid chroma-down modules available
- *                         secure-ui when secure-ui-misr feature is supported
+ * @cdm                 array of pointers to CDM blocks
- * @sec_sid_mask_count  number of SID masks
+ * @intf_count          number of valid INTF blocks available
- * @sec_sid_mask        SID masks used during the scm_call for transition
+ * @intf                array of pointers to INTF blocks
- *                         between secure/non-secure sessions
+ * @wb_count            number of valid writeback blocks available
- * @sui_ns_allowed      flag to indicate non-secure context banks are allowed
+ * @wb                  array of pointers to WB blocks
- *                         during secure-ui session
+ * @vbif_count          number of valid VBIF blocks available
- * @sui_supported_blendstage  secure-ui supported blendstage
+ * @vbif                array of pointers to VBIF blocks
- * @has_sui_blendstage  flag to indicate secure-ui has a blendstage restriction
+ * @merge_3d_count      number of valid merge 3d blocks available
- * @has_cursor    indicates if hardware cursor is supported
+ * @merge_3d            array of pointers to merge 3d blocks
- * @has_vig_p010  indicates if vig pipe supports p010 format
+ * @qdss_count          number of valid QDSS blocks available
- * @has_fp16      indicates if FP16 format is supported on SSPP pipes
+ * @qdss                array of pointers to QDSS blocks
- * @has_precise_vsync_ts  indicates if HW has vsyc timestamp logging capability
+ * @cwb_blk_off         CWB offset address
- * @has_ubwc_stats: indicates if ubwc stats feature is supported
+ * @cwb_blk_stride      offset between each CWB blk
- * @mdss_hw_block_size  Max offset of MDSS_HW block (0 offset), used for debug
- * @inline_rot_formats formats supported by the inline rotator feature
- * @irq_offset_list     list of sde_intr_irq_offsets to initialize irq table
- * @rc_count	number of rounded corner hardware instances
- * @demura_count number of demura hardware instances
  * @dcwb_count          number of dcwb hardware instances
+ * @reg_dma_count       number of valid reg dma blocks available
+ * @dma_cfg             pointer to config containing reg dma blocks
+ * @ad_count            number of AD4 hardware instances
+ * @ltm_count           number of LTM hardware instances
+ * @rc_count            number of rounded corner hardware instances
+ * @spr_count           number of SPR hardware instances
+ * @demura_count        number of demura hardware instances
+ * @demura_supported    indicates which SSPP/RECT combinations support demura
+ * @trusted_vm_env      true if the driver is executing in the trusted VM
+ * @tvm_reg_count	number of sub-driver register ranges that need to be included
+ *					for trusted vm for accepting the resources
+ * @tvm_reg		array of sub-driver register range entries that need to be included
+ * @max_trusted_vm_displays     maximum number of concurrent trusted VM displays supported
+ * @sui_block_xin_mask  mask of xin-clients to block during secure-ui when SUI MISR is supported
+ * @sec_sid_mask_count  number of SID masks
+ * @sec_sid_mask        SID masks used during the scm_call for secure/non-secure transitions
+ * @sui_supported_blendstage    secure-ui supported blendstage
+ * @max_display_width   minimum display width
+ * @max_display_height  minimum display height
+ * @min_display_width   maximum display width
+ * @min_display_height  maximum display height
+ * @max_sspp_linewidth  max source pipe line width
+ * @vig_sspp_linewidth  max vig source pipe line width support
+ * @scaling_linewidth   max vig source pipe linewidth for scaling usecases
+ * @max_wb_linewidth    max writeback line width
+ * @max_wb_linewidth_linear     max writeback line width for linear formats
+ * @max_dsc_width       max dsc line width
+ * @max_mixer_width     max layer mixer line width
+ * @max_mixer_blendstages       max layer mixer blend stages (z orders)
+ * @vbif_qos_nlvl       number of vbif QoS priority levels
+ * @macrotile_mode      UBWC parameter for macro tile channel distribution
+ * @pipe_order_type     indicates if it is required to specify pipe order
+ * @csc_type            csc or csc_10bit support
+ * @allowed_dsc_reservation_switch      intf to which dsc reservation switch is supported
+ * @sc_cfg              system cache configuration
+ * @perf                performance control settings
+ * @uidle_cfg           settings for uidle feature
+ * @irq_offset_list     list of sde_intr_irq_offsets to initialize irq table
+ * @features            bitmap of supported SDE_FEATUREs
+ * @dma_formats         supported formats for dma pipe
+ * @cursor_formats      supported formats for cursor pipe
+ * @vig_formats         supported formats for vig pipe
+ * @wb_formats          supported formats for wb
+ * @virt_vig_formats    supported formats for virtual vig pipe
+ * @inline_rot_formats  supported formats for inline rotation
+ * @inline_rot_restricted_formats       restricted formats for inline rotation
  */
 struct sde_mdss_cfg {
+	/* Versions */
 	u32 hwversion;
-	bool trusted_vm_env;
-	u32 max_trusted_vm_displays;
-	u32 tvm_reg_count;
-	struct resource tvm_reg[MAX_REG_SIZE_ENTRIES];
-
-	u32 max_sspp_linewidth;
-	u32 vig_sspp_linewidth;
-	u32 scaling_linewidth;
-	u32 max_mixer_width;
-	u32 max_dsc_width;
-	u32 max_mixer_blendstages;
-	u32 max_wb_linewidth;
-	u32 max_wb_linewidth_linear;
-
-	u32 max_display_width;
-	u32 max_display_height;
-	u32 min_display_width;
-	u32 min_display_height;
-
-	u32 csc_type;
-	u32 smart_dma_rev;
-	u32 ctl_rev;
-	bool has_src_split;
-	bool has_cdp;
-	bool has_dim_layer;
-	bool has_wb_ubwc;
-	bool has_cwb_crop;
-	bool has_cwb_support;
-	bool has_dedicated_cwb_support;
-	bool has_cwb_dither;
-	u32 cwb_blk_off;
-	u32 cwb_blk_stride;
 	u32 ubwc_version;
 	u32 ubwc_bw_calc_version;
-	bool skip_inline_rot_threshold;
-	bool has_idle_pc;
-	u32 allowed_dsc_reservation_switch;
-	bool wakeup_with_touch;
-	u32 vbif_qos_nlvl;
-	u32 ts_prefill_rev;
-	u32 true_inline_rot_rev;
-	u32 macrotile_mode;
-	u32 pipe_order_type;
-	bool sspp_multirect_error;
-	bool delay_prg_fetch_start;
-	bool has_qsync;
-	bool has_3d_merge_reset;
-	bool has_decimation;
-	bool has_mixer_combined_alpha;
-	bool vbif_disable_inner_outer_shareable;
-	bool inline_disable_const_clr;
-	bool dither_luma_mode_support;
-	bool has_base_layer;
-	bool has_demura;
-	bool has_trusted_vm_support;
-	bool has_avr_step;
-	bool rc_lm_flush_override;
-	u32 demura_supported[SSPP_MAX][2];
 	u32 qseed_sw_lib_rev;
 	u32 qseed_hw_version;
+	u32 smart_dma_rev;
+	u32 ctl_rev;
+	u32 ts_prefill_rev;
+	u32 true_inline_rot_rev;
 
-	struct sde_sc_cfg sc_cfg[SDE_SYS_CACHE_MAX];
+	/* HW Blocks */
-	bool syscache_supported;
-
-	bool sui_misr_supported;
-	u32 sui_block_xin_mask;
-
-	u32 sec_sid_mask_count;
-	u32 sec_sid_mask[MAX_BLOCKS];
-	u32 sui_ns_allowed;
-	u32 sui_supported_blendstage;
-	bool has_sui_blendstage;
-
-	bool has_hdr;
-	bool has_hdr_plus;
-	bool has_cursor;
-	bool has_vig_p010;
-	bool has_fp16;
-	bool has_precise_vsync_ts;
-	bool has_ubwc_stats;
-
-	u32 mdss_hw_block_size;
 	u32 mdss_count;
 	struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
-
+	u32 mdss_hw_block_size;
 	u32 mdp_count;
 	struct sde_mdp_cfg mdp[MAX_BLOCKS];
-
-	/* uidle is a singleton */
-	struct sde_uidle_cfg uidle_cfg;
-
 	u32 ctl_count;
 	struct sde_ctl_cfg ctl[MAX_BLOCKS];
-
 	u32 sspp_count;
 	struct sde_sspp_cfg sspp[MAX_BLOCKS];
-
 	u32 mixer_count;
 	struct sde_lm_cfg mixer[MAX_BLOCKS];
-
 	struct sde_dspp_top_cfg dspp_top;
-
 	u32 dspp_count;
 	struct sde_dspp_cfg dspp[MAX_BLOCKS];
-
 	u32 ds_count;
 	struct sde_ds_cfg ds[MAX_BLOCKS];
-
 	u32 pingpong_count;
 	struct sde_pingpong_cfg pingpong[MAX_BLOCKS];
-
 	u32 dsc_count;
 	struct sde_dsc_cfg dsc[MAX_BLOCKS];
-
 	u32 vdc_count;
 	struct sde_vdc_cfg vdc[MAX_BLOCKS];
-
 	u32 cdm_count;
 	struct sde_cdm_cfg cdm[MAX_BLOCKS];
-
 	u32 intf_count;
 	struct sde_intf_cfg intf[MAX_BLOCKS];
-
 	u32 wb_count;
 	struct sde_wb_cfg wb[MAX_BLOCKS];
-
 	u32 vbif_count;
 	struct sde_vbif_cfg vbif[MAX_BLOCKS];
+	u32 merge_3d_count;
+	struct sde_merge_3d_cfg merge_3d[MAX_BLOCKS];
+	u32 qdss_count;
+	struct sde_qdss_cfg qdss[MAX_BLOCKS];
+	u32 cwb_blk_off;
+	u32 cwb_blk_stride;
+	u32 dcwb_count;
 
 	u32 reg_dma_count;
 	struct sde_reg_dma_cfg dma_cfg;
-
 	u32 ad_count;
 	u32 ltm_count;
 	u32 rc_count;
 	u32 spr_count;
 	u32 demura_count;
+	u32 demura_supported[SSPP_MAX][2];
 
-	u32 merge_3d_count;
+	/* Secure & Trusted UI */
-	struct sde_merge_3d_cfg merge_3d[MAX_BLOCKS];
+	bool trusted_vm_env;
+	u32 tvm_reg_count;
+	struct resource tvm_reg[MAX_REG_SIZE_ENTRIES];
+	u32 max_trusted_vm_displays;
+	u32 sui_block_xin_mask;
+	u32 sec_sid_mask_count;
+	u32 sec_sid_mask[MAX_BLOCKS];
+	u32 sui_supported_blendstage;
 
-	u32 qdss_count;
+	/* Limits */
-	struct sde_qdss_cfg qdss[MAX_BLOCKS];
+	u32 max_display_width;
-
+	u32 max_display_height;
-	u32 dcwb_count;
+	u32 min_display_width;
-
+	u32 min_display_height;
-	/* Add additional block data structures here */
+	u32 max_sspp_linewidth;
+	u32 vig_sspp_linewidth;
+	u32 scaling_linewidth;
+	u32 max_wb_linewidth;
+	u32 max_wb_linewidth_linear;
+	u32 max_dsc_width;
+	u32 max_mixer_width;
+	u32 max_mixer_blendstages;
 
+	/* Configs */
+	u32 vbif_qos_nlvl;
+	u32 macrotile_mode;
+	u32 pipe_order_type;
+	u32 csc_type;
+	u32 allowed_dsc_reservation_switch;
+	struct sde_sc_cfg sc_cfg[SDE_SYS_CACHE_MAX];
 	struct sde_perf_cfg perf;
+	struct sde_uidle_cfg uidle_cfg;
+	struct list_head irq_offset_list;
+	DECLARE_BITMAP(features, SDE_FEATURE_MAX);
+
+	/* Supported Pixel Format Lists */
 	struct sde_format_extended *dma_formats;
 	struct sde_format_extended *cursor_formats;
 	struct sde_format_extended *vig_formats;
@@ -1728,8 +1754,6 @@ struct sde_mdss_cfg {
 	struct sde_format_extended *virt_vig_formats;
 	struct sde_format_extended *inline_rot_formats;
 	struct sde_format_extended *inline_rot_restricted_formats;
-
-	struct list_head irq_offset_list;
 };
 
 struct sde_mdss_hw_cfg_handler {

msm/sde/sde_kms.c

@@ -4759,7 +4759,7 @@ static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
 	 * timestamp as the DRM hooks for vblank timestamp/counters would be set
 	 * based on the feature
 	 */
-	if (sde_kms->catalog->has_precise_vsync_ts)
+	if (test_bit(SDE_FEATURE_HW_VSYNC_TS, sde_kms->catalog->features))
 		dev->vblank_disable_immediate = true;
 
 	/*

msm/sde/sde_kms.h

@@ -398,16 +398,16 @@ static inline bool sde_kms_is_secure_session_inprogress(struct sde_kms *sde_kms)
 {
 	bool ret = false;
 
-	if (!sde_kms)
+	if (!sde_kms || !sde_kms->catalog)
 		return false;
 
 	mutex_lock(&sde_kms->secure_transition_lock);
-	if (((sde_kms->catalog->sui_ns_allowed) &&
+	if (((test_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_kms->catalog->features)) &&
 	     (sde_kms->smmu_state.secure_level == SDE_DRM_SEC_ONLY) &&
 	     ((sde_kms->smmu_state.state == DETACHED_SEC) ||
 	      (sde_kms->smmu_state.state == DETACH_SEC_REQ) ||
-				(sde_kms->smmu_state.state == ATTACH_SEC_REQ)))
+	      (sde_kms->smmu_state.state == ATTACH_SEC_REQ))) ||
-		|| (((sde_kms->smmu_state.state == DETACHED) ||
+	    (((sde_kms->smmu_state.state == DETACHED) ||
 	      (sde_kms->smmu_state.state == DETACH_ALL_REQ) ||
 	      (sde_kms->smmu_state.state == ATTACH_ALL_REQ))))
 		ret = true;
@@ -429,7 +429,7 @@ static inline bool sde_kms_is_vbif_operation_allowed(struct sde_kms *sde_kms)
 	if (!sde_kms)
 		return false;
 
-	if (!sde_kms->catalog->sui_misr_supported)
+	if (!test_bit(SDE_FEATURE_SUI_MISR, sde_kms->catalog->features))
 		return true;
 
 	return !sde_kms_is_secure_session_inprogress(sde_kms);
@@ -446,7 +446,7 @@ static inline bool sde_kms_is_cp_operation_allowed(struct sde_kms *sde_kms)
 	if (!sde_kms || !sde_kms->catalog)
 		return false;
 
-	if (sde_kms->catalog->sui_ns_allowed)
+	if (test_bit(SDE_FEATURE_SUI_NS_ALLOWED, sde_kms->catalog->features))
 		return true;
 
 	return !sde_kms_is_secure_session_inprogress(sde_kms);

msm/sde/sde_plane.c

@@ -3716,7 +3716,7 @@ static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
 	sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
 
 	index = (master_plane_id == 0) ? 0 : 1;
-	if (catalog->has_demura &&
+	if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
 	    catalog->demura_supported[psde->pipe][index] != ~0x0)
 		sde_kms_info_add_keyint(info, "demura_block", index);
 
@@ -3816,7 +3816,7 @@ static void _sde_plane_install_properties(struct drm_plane *plane,
 		if (catalog->mixer_count &&
 				catalog->mixer[0].sblk->maxblendstages) {
 			zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
-			if (catalog->has_base_layer &&
+			if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
 					(zpos_max > SDE_STAGE_MAX - 1))
 				zpos_max = SDE_STAGE_MAX - 1;
 			else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)

msm/sde/sde_rm.c

@@ -2209,7 +2209,7 @@ static int _sde_rm_populate_requirements(
 	 */
 	if ((!RM_RQ_CWB(reqs) || !RM_RQ_DCWB(reqs))
 				&& sde_crtc_state_in_clone_mode(enc, crtc_state)) {
-		if (cfg->has_dedicated_cwb_support)
+		if (test_bit(SDE_FEATURE_DEDICATED_CWB, cfg->features))
 			reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_DCWB);
 		else
 			reqs->top_ctrl |= BIT(SDE_RM_TOPCTL_CWB);

msm/sde/sde_wb.c

@@ -465,7 +465,8 @@ int sde_wb_connector_set_info_blob(struct drm_connector *connector,
 		}
 
 		sde_kms = to_sde_kms(priv->kms);
-		sde_kms_info_add_keyint(info, "has_cwb_dither", sde_kms->catalog->has_cwb_dither);
+		sde_kms_info_add_keyint(info, "has_cwb_dither", test_bit(SDE_FEATURE_CWB_DITHER,
+				sde_kms->catalog->features));
 	} else {
 		SDE_ERROR("invalid params %pK\n", wb_dev->drm_dev);
 		return -EINVAL;
@@ -507,7 +508,7 @@ static void sde_wb_connector_install_dither_property(struct sde_wb_device *wb_de
 	sde_kms = to_sde_kms(priv->kms);
 	catalog = sde_kms->catalog;
 
-	if (!catalog->has_cwb_dither)
+	if (!test_bit(SDE_FEATURE_CWB_DITHER, catalog->features))
 		return;
 
 	version = SDE_COLOR_PROCESS_MAJOR(