msm: camera: csiphy: update the csiphy driver for v2 device

Move the flag which decides whether to program the common
registers for csiphy for all the phy devices to dtsi file.
Common registers sequence should not be programmed for all
the Csiphys during stream on for SM8450 v2 device.

CRs-Fixed: 3020245
Change-Id: I91e6bb786868c1aae165c97751663593e46b8c5b
Signed-off-by: Jigar Agrawal <[email protected]>

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -1211,7 +1211,7 @@ void cam_csiphy_shutdown(struct csiphy_device *csiphy_dev)
 			cam_csiphy_reset_phyconfig_param(csiphy_dev, i);
 		}
 
-		if (csiphy_reg->prgm_cmn_reg_across_csiphy) {
+		if (csiphy_dev->prgm_cmn_reg_across_csiphy) {
 			mutex_lock(&active_csiphy_cnt_mutex);
 			active_csiphy_hw_cnt--;
 			mutex_unlock(&active_csiphy_cnt_mutex);
@@ -1884,7 +1884,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 
 		csiphy_dev->csiphy_info[offset].csiphy_cpas_cp_reg_mask = 0x0;
 
-		if (csiphy_reg->prgm_cmn_reg_across_csiphy) {
+		if (csiphy_dev->prgm_cmn_reg_across_csiphy) {
 			mutex_lock(&active_csiphy_cnt_mutex);
 			active_csiphy_hw_cnt--;
 			mutex_unlock(&active_csiphy_cnt_mutex);
@@ -2121,7 +2121,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			goto cpas_stop;
 		}
 
-		if (csiphy_reg->prgm_cmn_reg_across_csiphy) {
+		if (csiphy_dev->prgm_cmn_reg_across_csiphy) {
 			cam_csiphy_prgm_cmn_data(csiphy_dev, false);
 
 			mutex_lock(&active_csiphy_cnt_mutex);
@@ -2229,7 +2229,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 	return rc;
 
 hw_cnt_decrement:
-	if (csiphy_reg->prgm_cmn_reg_across_csiphy) {
+	if (csiphy_dev->prgm_cmn_reg_across_csiphy) {
 		mutex_lock(&active_csiphy_cnt_mutex);
 		active_csiphy_hw_cnt--;
 		mutex_unlock(&active_csiphy_cnt_mutex);

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -151,7 +151,6 @@ struct csiphy_reg_parms_t {
 	uint32_t csiphy_cpas_cp_3ph_offset;
 	uint32_t csiphy_2ph_clock_lane;
 	uint32_t csiphy_2ph_combo_ck_ln;
-	uint32_t prgm_cmn_reg_across_csiphy;
 	struct cam_csiphy_aon_sel_params_t *aon_sel_params;
 };
 
@@ -312,6 +311,7 @@ struct csiphy_work_queue {
  * @csiphy_cpas_cp_reg_mask    : Secure csiphy lane mask
  * @ops                        : KMD operations
  * @crm_cb                     : Callback API pointers
+ * @prgm_cmn_reg_across_csiphy : Flag to decide if com settings need to be programmed for all PHYs
  * @enable_irq_status_reg_dump : Debugfs flag to enable hw IRQ status register dump
  * @en_lane_status_reg_dump    : Debugfs flag to enable cphy/dphy lane status dump
  * @en_full_phy_reg_dump       : Debugfs flag to enable the dump for all the Phy registers
@@ -346,6 +346,7 @@ struct csiphy_device {
 					CSIPHY_MAX_INSTANCES_PER_PHY];
 	struct cam_req_mgr_kmd_ops     ops;
 	struct cam_req_mgr_crm_cb     *crm_cb;
+	bool                           prgm_cmn_reg_across_csiphy;
 	bool                           enable_irq_status_reg_dump;
 	bool                           en_lane_status_reg_dump;
 	bool                           en_full_phy_reg_dump;

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -255,6 +255,7 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 {
 	int32_t   rc = 0, i = 0;
 	uint32_t  clk_cnt = 0;
+	uint32_t   is_regulator_enable_sync;
 	char      *csi_3p_clk_name = "csi_phy_3p_clk";
 	char      *csi_3p_clk_src_name = "csiphy_3p_clk_src";
 	struct cam_hw_soc_info   *soc_info;
@@ -267,6 +268,15 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 		return  rc;
 	}
 
+	rc = of_property_read_u32(soc_info->dev->of_node, "rgltr-enable-sync",
+		&is_regulator_enable_sync);
+	if (rc) {
+		rc = 0;
+		is_regulator_enable_sync = 0;
+	}
+
+	csiphy_dev->prgm_cmn_reg_across_csiphy = (bool) is_regulator_enable_sync;
+
 	if (of_device_is_compatible(soc_info->dev->of_node,
 		"qcom,csiphy-v1.0")) {
 		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_0_reg;

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h

@@ -23,7 +23,6 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = {
 	.csiphy_2ph_3ph_config_array_size = 0,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
-	.prgm_cmn_reg_across_csiphy = 1,
 	.aon_sel_params = NULL,
 };
 

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -37,7 +37,6 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 	.csiphy_2ph_combo_ck_ln = 0x10,
 	.csiphy_interrupt_status_size = 11,
 	.aon_sel_params = &aon_cam_select_params,
-	.prgm_cmn_reg_across_csiphy = 1,
 };
 
 struct csiphy_reg_t csiphy_common_reg_2_1_0[] = {