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-/*
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- * Copyright (c) 2015-2016,2018 The Linux Foundation. All rights reserved.
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- *
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- * Permission to use, copy, modify, and/or distribute this software for
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- * any purpose with or without fee is hereby granted, provided that the
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- * above copyright notice and this permission notice appear in all
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- * copies.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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- * PERFORMANCE OF THIS SOFTWARE.
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- */
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-
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-#include "qdf_module.h"
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-
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-#if defined(IPQ4019_HEADERS_DEF)
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-#define AR900B 1
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-
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-#define WLAN_HEADERS 1
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-#include "common_drv.h"
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-#include "IPQ4019/soc_addrs.h"
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-#include "IPQ4019/extra/hw/apb_map.h"
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-#ifdef WLAN_HEADERS
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-#include "IPQ4019/extra/hw/wifi_top_reg_map.h"
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-#include "IPQ4019/hw/rtc_soc_reg.h"
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-#endif
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-#include "IPQ4019/hw/ce_wrapper_reg_csr.h"
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-
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-#include "IPQ4019/extra/hw/soc_core_reg.h"
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-#include "IPQ4019/extra/hw/ce_reg_csr.h"
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-#include <IPQ4019/hw/interface/rx_location_info.h>
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-#include <IPQ4019/hw/interface/rx_pkt_end.h>
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-#include <IPQ4019/hw/interface/rx_phy_ppdu_end.h>
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-#include <IPQ4019/hw/interface/rx_timing_offset.h>
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-#include <IPQ4019/hw/interface/rx_location_info.h>
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-#include <IPQ4019/hw/tlv/rx_ppdu_start.h>
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-#include <IPQ4019/hw/tlv/rx_ppdu_end.h>
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-#include <IPQ4019/hw/tlv/rx_mpdu_start.h>
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-#include <IPQ4019/hw/tlv/rx_mpdu_end.h>
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-#include <IPQ4019/hw/tlv/rx_msdu_start.h>
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-#include <IPQ4019/hw/tlv/rx_msdu_end.h>
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-#include <IPQ4019/hw/tlv/rx_attention.h>
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-#include <IPQ4019/hw/tlv/rx_frag_info.h>
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-#include <IPQ4019/hw/datastruct/msdu_link_ext.h>
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-
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-/* Base address is defined in pcie_local_reg.h. Macros which access the
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- * registers include the base address in their definition.
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- */
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-
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-#define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS)
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-#define DRAM_BASE_ADDRESS TARG_DRAM_START
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-
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-/* Backwards compatibility -- TBDXXX */
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-
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-#define MISSING 0
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-
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-#define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB
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-#define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK
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-#define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK
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-#define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK
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-#define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS
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-#define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS
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-#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS
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-#define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS
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-#define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK
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-#define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS
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-#define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS
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-#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
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-#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
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-#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
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-#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
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-#define GPIO_PIN0_OFFSET MISSING
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-#define GPIO_PIN1_OFFSET MISSING
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-#define GPIO_PIN0_CONFIG_MASK MISSING
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-#define GPIO_PIN1_CONFIG_MASK MISSING
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-#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
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-#define LOCAL_SCRATCH_OFFSET 0x18
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-#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
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-#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
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-#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
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-#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
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-/*TBD:dakota Check if these can be removed for dakota */
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-#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
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-#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
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-#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
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-#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
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-#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
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-#define MBOX_BASE_ADDRESS MISSING
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-#define INT_STATUS_ENABLE_ERROR_LSB MISSING
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-#define INT_STATUS_ENABLE_ERROR_MASK MISSING
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-#define INT_STATUS_ENABLE_CPU_LSB MISSING
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-#define INT_STATUS_ENABLE_CPU_MASK MISSING
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-#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
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-#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
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-#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
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-#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
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-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
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-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
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-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
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-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
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-#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
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-#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
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-#define INT_STATUS_ENABLE_ADDRESS MISSING
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-#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
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-#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
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-#define HOST_INT_STATUS_ADDRESS MISSING
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-#define CPU_INT_STATUS_ADDRESS MISSING
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-#define ERROR_INT_STATUS_ADDRESS MISSING
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-#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
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-#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
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-#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
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-#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
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-#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
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-#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
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-#define COUNT_DEC_ADDRESS MISSING
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-#define HOST_INT_STATUS_CPU_MASK MISSING
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-#define HOST_INT_STATUS_CPU_LSB MISSING
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-#define HOST_INT_STATUS_ERROR_MASK MISSING
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-#define HOST_INT_STATUS_ERROR_LSB MISSING
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-#define HOST_INT_STATUS_COUNTER_MASK MISSING
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-#define HOST_INT_STATUS_COUNTER_LSB MISSING
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-#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
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-#define WINDOW_DATA_ADDRESS MISSING
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-#define WINDOW_READ_ADDR_ADDRESS MISSING
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-#define WINDOW_WRITE_ADDR_ADDRESS MISSING
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-/* MAC Descriptor */
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-#define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2)
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-/* GPIO Register */
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-#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
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-#define GPIO_PIN0_CONFIG_LSB MISSING
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-#define GPIO_PIN0_PAD_PULL_LSB MISSING
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-#define GPIO_PIN0_PAD_PULL_MASK MISSING
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-/* SI reg */
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-#define SI_CONFIG_ERR_INT_MASK MISSING
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-#define SI_CONFIG_ERR_INT_LSB MISSING
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-/* CE descriptor */
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-#define CE_SRC_DESC_SIZE_DWORD 2
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-#define CE_DEST_DESC_SIZE_DWORD 2
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-#define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0
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-#define CE_SRC_DESC_INFO_OFFSET_DWORD 1
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-#define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0
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-#define CE_DEST_DESC_INFO_OFFSET_DWORD 1
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-#if _BYTE_ORDER == _BIG_ENDIAN
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-#define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000
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-#define CE_SRC_DESC_INFO_NBYTES_SHIFT 16
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-#define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000
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-#define CE_SRC_DESC_INFO_GATHER_SHIFT 15
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-#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000
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-#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14
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-#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000
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-#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13
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-#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000
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-#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12
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-#define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF
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-#define CE_SRC_DESC_INFO_META_DATA_SHIFT 0
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-#else
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-#define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF
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-#define CE_SRC_DESC_INFO_NBYTES_SHIFT 0
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-#define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000
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-#define CE_SRC_DESC_INFO_GATHER_SHIFT 16
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-#define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000
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-#define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17
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-#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000
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-#define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18
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-#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000
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-#define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19
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-#define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000
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-#define CE_SRC_DESC_INFO_META_DATA_SHIFT 20
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-#endif
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-#if _BYTE_ORDER == _BIG_ENDIAN
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-#define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000
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-#define CE_DEST_DESC_INFO_NBYTES_SHIFT 16
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-#define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000
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-#define CE_DEST_DESC_INFO_GATHER_SHIFT 15
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-#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000
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-#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14
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-#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000
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-#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13
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-#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000
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-#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12
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-#define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF
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-#define CE_DEST_DESC_INFO_META_DATA_SHIFT 0
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-#else
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-#define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF
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-#define CE_DEST_DESC_INFO_NBYTES_SHIFT 0
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-#define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000
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-#define CE_DEST_DESC_INFO_GATHER_SHIFT 16
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-#define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000
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-#define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17
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-#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000
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-#define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18
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-#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000
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-#define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19
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-#define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000
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-#define CE_DEST_DESC_INFO_META_DATA_SHIFT 20
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-#endif
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-
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-#define MY_TARGET_DEF IPQ4019_TARGETdef
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-#define MY_HOST_DEF IPQ4019_HOSTdef
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-#define MY_CEREG_DEF IPQ4019_CE_TARGETdef
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-#define MY_TARGET_BOARD_DATA_SZ IPQ4019_BOARD_DATA_SZ
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-#define MY_TARGET_BOARD_EXT_DATA_SZ IPQ4019_BOARD_EXT_DATA_SZ
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-#include "targetdef.h"
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-#include "hostdef.h"
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-qdf_export_symbol(IPQ4019_CE_TARGETdef);
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-#else
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-#include "common_drv.h"
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-#include "targetdef.h"
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-#include "hostdef.h"
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-struct targetdef_s *IPQ4019_TARGETdef;
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-struct hostdef_s *IPQ4019_HOSTdef;
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-#endif /* IPQ4019_HEADERS_DEF */
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-qdf_export_symbol(IPQ4019_TARGETdef);
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-qdf_export_symbol(IPQ4019_HOSTdef);
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Naveen S