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qcacmn: Add cfg command to enable umac reset skeleton debug

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Add cfg command to enable umac reset skeleton debug, which
when enabled will skip post reset procedure handling.

Change-Id: Ieca393e6292660bb3ada40408fd6e71ac78d0a1f
CRs-Fixed: 3296960
This commit is contained in:
Pavankumar Nandeshwar
2022-09-21 07:05:16 -07:00
committed by Madan Koyyalamudi
parent 238555b44c
commit 7dee89e9ec
3 changed files with 57 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
dp/inc/cdp_txrx_cmn_struct.h
View File

@@ -1288,6 +1288,7 @@ enum cdp_pdev_param_type {
* @cdp_psoc_param_vdev_stats_hw_offload: Configure HW vdev stats offload
* @cdp_pdev_param_undecoded_metadata_enable: Undecoded metadata capture enable
* @cdp_vdev_param_traffic_end_ind: Traffic end indication enable/disable
* @cdp_skel_enable : Enable/Disable skeleton code for Umac reset debug
*/
typedef union cdp_config_param_t {
/* peer params */
@@ -1374,6 +1375,7 @@ typedef union cdp_config_param_t {
bool cdp_sawf_enabled;
bool cdp_drop_3addr_mcast;
bool cdp_vdev_param_traffic_end_ind;
bool cdp_umac_rst_skel;
} cdp_config_param_type;
/**
@@ -1510,6 +1512,7 @@ enum cdp_vdev_param_type {
* @CDP_CFG_PEER_EXT_STATS: Peer extended stats mode.
* @CDP_IPA_ENABLE : set IPA enable mode.
* @CDP_CFG_VDEV_STATS_HW_OFFLOAD: HW Vdev stats config
* @CDP_UMAC_RST_SKEL_ENABLE: Enable Umac reset skeleton code for debug
*/
enum cdp_psoc_param_type {
CDP_ENABLE_RATE_STATS,
@@ -1519,6 +1522,7 @@ enum cdp_psoc_param_type {
CDP_IPA_ENABLE,
CDP_CFG_VDEV_STATS_HW_OFFLOAD,
CDP_SAWF_ENABLE,
CDP_UMAC_RST_SKEL_ENABLE,
};
#define TXRX_FW_STATS_TXSTATS 1

44
dp/wifi3.0/dp_main.c
View File

@@ -10063,6 +10063,42 @@ static void dp_txrx_stats_help(void)
dp_info(" 37 -- Host SRNG usage watermark stats");
}
#ifdef DP_UMAC_HW_RESET_SUPPORT
/**
* dp_umac_rst_skel_enable_update(): Update skel dbg flag for umac reset
* @soc: dp soc handle
* @en: ebable/disable
*
* Return: void
*/
static void dp_umac_rst_skel_enable_update(struct dp_soc *soc, bool en)
{
soc->umac_reset_ctx.skel_enable = en;
dp_cdp_debug("UMAC HW reset debug skelton code enabled :%u",
soc->umac_reset_ctx.skel_enable);
}
/**
* dp_umac_rst_skel_enable_get(): Get skel dbg flag for umac reset
* @soc: dp soc handle
*
* Return: enable/disable flag
*/
static bool dp_umac_rst_skel_enable_get(struct dp_soc *soc)
{
return soc->umac_reset_ctx.skel_enable;
}
#else
static void dp_umac_rst_skel_enable_update(struct dp_soc *soc, bool en)
{
}
static bool dp_umac_rst_skel_enable_get(struct dp_soc *soc)
{
return false;
}
#endif
/**
* dp_print_host_stats()- Function to print the stats aggregated at host
* @vdev_handle: DP_VDEV handle
@@ -10953,6 +10989,9 @@ dp_set_psoc_param(struct cdp_soc_t *cdp_soc,
case CDP_SAWF_ENABLE:
wlan_cfg_set_sawf_config(wlan_cfg_ctx, val.cdp_sawf_enabled);
break;
case CDP_UMAC_RST_SKEL_ENABLE:
dp_umac_rst_skel_enable_update(soc, val.cdp_umac_rst_skel);
break;
default:
break;
}
@@ -10986,6 +11025,9 @@ static QDF_STATUS dp_get_psoc_param(struct cdp_soc_t *cdp_soc,
val->cdp_psoc_param_vdev_stats_hw_offload =
wlan_cfg_get_vdev_stats_hw_offload_config(soc->wlan_cfg_ctx);
break;
case CDP_UMAC_RST_SKEL_ENABLE:
val->cdp_umac_rst_skel = dp_umac_rst_skel_enable_get(soc);
break;
default:
dp_warn("Invalid param");
break;
@@ -13426,6 +13468,7 @@ static QDF_STATUS dp_umac_reset_handle_pre_reset(struct dp_soc *soc)
*/
static QDF_STATUS dp_umac_reset_handle_post_reset(struct dp_soc *soc)
{
if (!soc->umac_reset_ctx.skel_enable) {
qdf_nbuf_t *nbuf_list = &soc->umac_reset_ctx.nbuf_list;
dp_set_umac_regs(soc);
@@ -13439,6 +13482,7 @@ static QDF_STATUS dp_umac_reset_handle_post_reset(struct dp_soc *soc)
dp_tx_desc_pool_cleanup(soc, nbuf_list);
dp_reset_tid_q_setup(soc);
}
return dp_umac_reset_notify_action_completion(soc,
UMAC_RESET_ACTION_DO_POST_RESET_START);

2
dp/wifi3.0/dp_umac_reset.h
View File

@@ -136,6 +136,7 @@ struct umac_reset_rx_actions {
* @rx_actions: callbacks for handling UMAC reset actions
* @intr_ctx_bkp: DP Interrupts ring masks backup
* @nbuf_list: skb list for delayed free
* @skel_enable: Enable skeleton code for umac reset
*/
struct dp_soc_umac_reset_ctx {
qdf_dma_addr_t shmem_paddr_unaligned;
@@ -149,6 +150,7 @@ struct dp_soc_umac_reset_ctx {
struct umac_reset_rx_actions rx_actions;
struct dp_intr_bkp *intr_ctx_bkp;
qdf_nbuf_t nbuf_list;
bool skel_enable;
};
/**