Merge "disp: msm: dsi: set source to xo while turning off PLL"
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@@ -719,6 +719,7 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev,
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struct dsi_link_lp_clk_info *lp_link = &ctrl->clk_info.lp_link_clks;
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struct dsi_link_hs_clk_info *hs_link = &ctrl->clk_info.hs_link_clks;
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struct dsi_clk_link_set *rcg = &ctrl->clk_info.rcg_clks;
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struct dsi_clk_link_set *xo = &ctrl->clk_info.xo_clk;
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core->mdp_core_clk = devm_clk_get(&pdev->dev, "mdp_core_clk");
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if (IS_ERR(core->mdp_core_clk)) {
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@@ -792,6 +793,14 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev,
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goto fail;
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}
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xo->byte_clk = devm_clk_get(&pdev->dev, "xo");
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if (IS_ERR(xo->byte_clk)) {
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xo->byte_clk = NULL;
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DSI_CTRL_DEBUG(ctrl, "failed to get xo clk, rc=%d\n", rc);
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}
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xo->pixel_clk = xo->byte_clk;
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return 0;
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fail:
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dsi_ctrl_clocks_deinit(ctrl);
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@@ -119,6 +119,7 @@ struct dsi_ctrl_power_info {
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* output of the PLL is set as parent for these root
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* clocks. These clocks are specific to controller
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* instance.
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* @xo_clk: XO clocks used to park the DSI PLL before turning off.
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* @mux_clks: Mux clocks used for Dynamic refresh feature.
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* @ext_clks: External byte/pixel clocks from the MMSS block. These
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* clocks are set as parent to rcg clocks.
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@@ -131,6 +132,7 @@ struct dsi_ctrl_clk_info {
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struct dsi_link_hs_clk_info hs_link_clks;
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struct dsi_link_lp_clk_info lp_link_clks;
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struct dsi_clk_link_set rcg_clks;
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struct dsi_clk_link_set xo_clk;
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/* Clocks set by DSI Manager */
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struct dsi_clk_link_set mux_clks;
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@@ -2647,6 +2647,52 @@ error:
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return rc;
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}
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static int dsi_display_set_clk_src(struct dsi_display *display, bool set_xo)
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{
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int rc = 0;
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int i;
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struct dsi_display_ctrl *m_ctrl, *ctrl;
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struct dsi_ctrl_clk_info *info;
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if (display->trusted_vm_env)
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return 0;
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/*
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* In case of split DSI usecases, the clock for master controller should
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* be enabled before the other controller. Master controller in the
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* clock context refers to the controller that sources the clock. While turning off the
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* clocks, the source is set to xo.
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*/
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m_ctrl = &display->ctrl[display->clk_master_idx];
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info = &m_ctrl->ctrl->clk_info;
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if (!set_xo)
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rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &display->clock_info.pll_clks);
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else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
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rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, &info->xo_clk);
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if (rc) {
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DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc);
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return rc;
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}
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/* Set source for the rest of the controllers */
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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if (!ctrl->ctrl || (ctrl == m_ctrl))
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continue;
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info = &ctrl->ctrl->clk_info;
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if (!set_xo)
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rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &display->clock_info.pll_clks);
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else if ((info->xo_clk.byte_clk) && (info->xo_clk.pixel_clk))
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rc = dsi_ctrl_set_clock_source(ctrl->ctrl, &info->xo_clk);
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if (rc) {
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DSI_ERR("[%s] failed to set source clocks, rc=%d\n", display->name, rc);
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return rc;
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}
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}
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return 0;
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}
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int dsi_display_phy_pll_toggle(void *priv, bool prepare)
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{
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int rc = 0;
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@@ -2658,6 +2704,8 @@ int dsi_display_phy_pll_toggle(void *priv, bool prepare)
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return -EINVAL;
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}
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rc = dsi_display_set_clk_src(display, !prepare);
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m_ctrl = &display->ctrl[display->clk_master_idx];
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if (!m_ctrl->phy) {
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DSI_ERR("[%s] PHY not found\n", display->name);
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@@ -2703,44 +2751,6 @@ int dsi_display_phy_configure(void *priv, bool commit)
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return rc;
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}
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static int dsi_display_set_clk_src(struct dsi_display *display)
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{
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int rc = 0;
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int i;
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struct dsi_display_ctrl *m_ctrl, *ctrl;
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/*
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* In case of split DSI usecases, the clock for master controller should
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* be enabled before the other controller. Master controller in the
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* clock context refers to the controller that sources the clock.
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*/
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m_ctrl = &display->ctrl[display->clk_master_idx];
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rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
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&display->clock_info.pll_clks);
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if (rc) {
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DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n",
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display->name, rc);
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return rc;
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}
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/* Turn on rest of the controllers */
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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if (!ctrl->ctrl || (ctrl == m_ctrl))
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continue;
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rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
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&display->clock_info.pll_clks);
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if (rc) {
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DSI_ERR("[%s] failed to set source clocks, rc=%d\n",
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display->name, rc);
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return rc;
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}
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}
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return 0;
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}
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static int dsi_display_phy_reset_config(struct dsi_display *display,
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bool enable)
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{
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@@ -7257,16 +7267,6 @@ static int dsi_display_pre_switch(struct dsi_display *display)
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goto error_ctrl_clk_off;
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}
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if (!display->trusted_vm_env) {
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rc = dsi_display_set_clk_src(display);
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if (rc) {
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DSI_ERR(
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"[%s] failed to set DSI link clock source, rc=%d\n",
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display->name, rc);
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goto error_ctrl_deinit;
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}
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}
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rc = dsi_display_clk_ctrl(display->dsi_clk_handle,
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DSI_LINK_CLK, DSI_CLK_ON);
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if (rc) {
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@@ -7666,16 +7666,6 @@ int dsi_display_prepare(struct dsi_display *display)
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}
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}
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if (!display->trusted_vm_env) {
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rc = dsi_display_set_clk_src(display);
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if (rc) {
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DSI_ERR(
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"[%s] failed to set DSI link clock source, rc=%d\n",
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display->name, rc);
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goto error_phy_disable;
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}
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}
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rc = dsi_display_ctrl_init(display);
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if (rc) {
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DSI_ERR("[%s] failed to setup DSI controller, rc=%d\n",
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