qcacld-3.0: Add different PLD vote for latency sensitive case

Any connection in 11g/a is very latency sensitive and
we need to vote for a higher DDR frequency than in
the other phy modes.

Identify the number of latency sensitive connections
in STA mode and vote for higher DDR frequency for the
latency sensitive cases.

Change-Id: I2ce20b2b40213bde52211eae659c9673c6e0d305
CRs-fixed: 2695045

core/pld/inc/pld_common.h

@@ -76,6 +76,7 @@ enum pld_bus_type {
  * @PLD_BUS_WIDTH_MEDIUM: vote for medium bus bandwidth
  * @PLD_BUS_WIDTH_HIGH: vote for high bus bandwidth
  * @PLD_BUS_WIDTH_VERY_HIGH: vote for very high bus bandwidth
+ * @PLD_BUS_WIDTH_LOW_LATENCY: vote for low latency bus bandwidth
  */
 enum pld_bus_width_type {
 	PLD_BUS_WIDTH_NONE,
@@ -84,6 +85,7 @@ enum pld_bus_width_type {
 	PLD_BUS_WIDTH_MEDIUM,
 	PLD_BUS_WIDTH_HIGH,
 	PLD_BUS_WIDTH_VERY_HIGH,
+	PLD_BUS_WIDTH_LOW_LATENCY,
 };
 
 #define PLD_MAX_FILE_NAME NAME_MAX