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Merge "disp: msm: dsi: add support to set continuous clock through phy"

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qctecmdr
2020-10-19 16:18:30 -07:00
committed by Gerrit - the friendly Code Review server
parent b267a4e5a2 ee90425ea7
commit 7d1acf4361
1 changed files with 13 additions and 1 deletions
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14
msm/dsi/dsi_display.c
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@@ -1071,7 +1071,19 @@ static void _dsi_display_continuous_clk_ctrl(struct dsi_display *display,
display_for_each_ctrl(i, display) { display_for_each_ctrl(i, display) {
ctrl = &display->ctrl[i]; ctrl = &display->ctrl[i];
dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
/*
* For phy ver 4.0 chipsets, configure DSI controller and
* DSI PHY to force clk lane to HS mode always whereas
* for other phy ver chipsets, configure DSI controller only.
*/
if (ctrl->phy->hw.ops.set_continuous_clk) {
dsi_ctrl_hs_req_sel(ctrl->ctrl, true);
dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
dsi_phy_set_continuous_clk(ctrl->phy, enable);
} else {
dsi_ctrl_set_continuous_clk(ctrl->ctrl, enable);
}
} }
} }