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qcacmn: Add support for beryllium on WIN

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Add support for split between lithium and beryllium
HAL files.
Add Wkk TLV support.

Change-Id: I7135e4061a4c3605d76c70c33320cbd533ea0c62
This commit is contained in:
Chaithanya Garrepalli
2021-08-12 17:12:24 +05:30
committed by Madan Koyyalamudi
parent 6b09fa3913
commit 7ccb73b31f
19 changed files with 765 additions and 508 deletions
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33
hal/wifi3.0/be/hal_be_generic_api.c
View File

@@ -22,7 +22,6 @@
#include "hal_be_reo.h" #include "hal_be_reo.h"
#include "hal_tx.h" //HAL_SET_FLD #include "hal_tx.h" //HAL_SET_FLD
#include "hal_be_rx.h" //HAL_RX_BUF_RBM_GET #include "hal_be_rx.h" //HAL_RX_BUF_RBM_GET
#include "hal_be_rx_tlv.h"
#if defined(QDF_BIG_ENDIAN_MACHINE) #if defined(QDF_BIG_ENDIAN_MACHINE)
/** /**
@@ -825,6 +824,34 @@ void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
} }
qdf_export_symbol(hal_cookie_conversion_reg_cfg_be); qdf_export_symbol(hal_cookie_conversion_reg_cfg_be);
/**
* hal_rx_msdu_reo_dst_ind_get: Gets the REO
* destination ring ID from the msdu desc info
*
* @msdu_link_desc : Opaque cookie pointer used by HAL to get to
* the current descriptor
*
* Return: dst_ind (REO destination ring ID)
*/
static inline
uint32_t hal_rx_msdu_reo_dst_ind_get_be(hal_soc_handle_t hal_soc_hdl,
void *msdu_link_desc)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
struct rx_msdu_details *msdu_details;
struct rx_msdu_desc_info *msdu_desc_info;
struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
uint32_t dst_ind;
msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
/* The first msdu in the link should exsist */
msdu_desc_info = hal_rx_msdu_ext_desc_info_get_ptr(&msdu_details[0],
hal_soc);
dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
return dst_ind;
}
/** /**
* hal_hw_txrx_default_ops_attach_be() - Attach the default hal ops for * hal_hw_txrx_default_ops_attach_be() - Attach the default hal ops for
* beryllium chipsets. * beryllium chipsets.
@@ -843,6 +870,7 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
hal_get_reo_reg_base_offset_be; hal_get_reo_reg_base_offset_be;
hal_soc->ops->hal_setup_link_idle_list = hal_soc->ops->hal_setup_link_idle_list =
hal_setup_link_idle_list_generic_be; hal_setup_link_idle_list_generic_be;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_be;
hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_be; hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_be;
hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_be; hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_be;
@@ -863,8 +891,11 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_be; hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_be;
hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_be; hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_be;
hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_be; hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_be;
hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_be; hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_be;
hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_be; hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_be;
hal_soc->ops->hal_reo_status_update = hal_reo_status_update_be; hal_soc->ops->hal_reo_status_update = hal_reo_status_update_be;
hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_be; hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_be;
hal_soc->ops->hal_rx_msdu_reo_dst_ind_get =
hal_rx_msdu_reo_dst_ind_get_be;
} }

2
hal/wifi3.0/be/hal_be_generic_api.h
View File

@@ -22,6 +22,8 @@
#include <hal_be_hw_headers.h> #include <hal_be_hw_headers.h>
#include "hal_be_tx.h" #include "hal_be_tx.h"
#include "hal_be_reo.h" #include "hal_be_reo.h"
#include <hal_api_mon.h>
#include <hal_generic_api.h>
/** /**
* hal_tx_comp_get_status() - TQM Release reason * hal_tx_comp_get_status() - TQM Release reason

309
hal/wifi3.0/be/hal_be_rx_tlv.h
View File

@@ -28,10 +28,7 @@
#define HAL_RX_BE_PKT_HDR_TLV_LEN 112 #define HAL_RX_BE_PKT_HDR_TLV_LEN 112
#ifdef CONFIG_WORD_BASED_TLV #ifndef CONFIG_WORD_BASED_TLV
typedef struct rx_mpdu_start hal_rx_mpdu_start_t;
typedef struct rx_msdu_end hal_rx_msdu_end_t;
#else
typedef struct rx_mpdu_start hal_rx_mpdu_start_t; typedef struct rx_mpdu_start hal_rx_mpdu_start_t;
typedef struct rx_msdu_end hal_rx_msdu_end_t; typedef struct rx_msdu_end hal_rx_msdu_end_t;
#endif #endif
@@ -78,25 +75,24 @@ struct rx_pkt_tlvs {
#define HAL_RX_MPDU_START(_rx_pkt_tlv) \ #define HAL_RX_MPDU_START(_rx_pkt_tlv) \
(((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \ (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \
rx_mpdu_start.rx_mpdu_info_details) rx_mpdu_start.rx_mpdu_info_details)
#else
#else /* CONFIG_WORD_BASED_TLV */
#define HAL_RX_MSDU_END(_rx_pkt_tlv) \ #define HAL_RX_MSDU_END(_rx_pkt_tlv) \
(((struct rx_pkt_tlvs *)_rx_pkt_tlv)->msdu_end_tlv.rx_msdu_end) (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->msdu_end_tlv.rx_msdu_end)
#define HAL_RX_MPDU_START(_rx_pkt_tlv) \ #define HAL_RX_MPDU_START(_rx_pkt_tlv) \
(((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \ (((struct rx_pkt_tlvs *)_rx_pkt_tlv)->mpdu_start_tlv. \
rx_mpdu_start.rx_mpdu_info_details) rx_mpdu_start)
#endif /* CONFIG_WORD_BASED_TLV */ #endif /* CONFIG_WORD_BASED_TLV */
#define HAL_RX_TLV_MSDU_DONE_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_MSDU_DONE_GET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done
#define HAL_RX_TLV_DECAP_FROMAT_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_DECAP_FORMAT_GET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).decap_format HAL_RX_MSDU_END(_rx_pkt_tlv).decap_format
#ifdef RECEIVE_OFFLOAD
#define HAL_RX_TLV_GET_TCP_PURE_ACK(_rx_pkt_tlv) \ #define HAL_RX_TLV_GET_TCP_PURE_ACK(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_only_ack HAL_RX_MSDU_END(_rx_pkt_tlv).tcp_only_ack
@@ -114,6 +110,7 @@ struct rx_pkt_tlvs {
#define HAL_RX_TLV_GET_TCP_OFFSET(_rx_pkt_tlv) \ #define HAL_RX_TLV_GET_TCP_OFFSET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).l4_offset HAL_RX_MSDU_END(_rx_pkt_tlv).l4_offset
#endif /* RECEIVE_OFFLOAD */
#define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(_rx_pkt_tlv) \ #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).flow_id_toeplitz HAL_RX_MSDU_END(_rx_pkt_tlv).flow_id_toeplitz
@@ -184,9 +181,15 @@ struct rx_pkt_tlvs {
#define HAL_RX_TLV_IS_MCAST_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_IS_MCAST_GET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).mcast_bcast HAL_RX_MSDU_END(_rx_pkt_tlv).mcast_bcast
#ifndef CONFIG_WORD_BASED_TLV
#define HAL_RX_TLV_FIRST_MPDU_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_FIRST_MPDU_GET(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).first_mpdu HAL_RX_MPDU_START(_rx_pkt_tlv).first_mpdu
#else
#define HAL_RX_TLV_FIRST_MPDU_GET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).first_mpdu
#endif
#ifdef RECEIVE_OFFLOAD
/** /**
* LRO information needed from the TLVs * LRO information needed from the TLVs
*/ */
@@ -201,6 +204,13 @@ struct rx_pkt_tlvs {
#define HAL_RX_TLV_GET_TCP_WIN(_rx_pkt_tlv) \ #define HAL_RX_TLV_GET_TCP_WIN(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).window_size HAL_RX_MSDU_END(_rx_pkt_tlv).window_size
#endif
#define HAL_RX_GET_FILTER_CATEGORY(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).rxpcu_mpdu_filter_in_category
#define HAL_RX_GET_PPDU_ID(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).phy_ppdu_id
#define HAL_RX_TLV_PEER_META_DATA_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_PEER_META_DATA_GET(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).peer_meta_data HAL_RX_MPDU_START(_rx_pkt_tlv).peer_meta_data
@@ -208,6 +218,9 @@ struct rx_pkt_tlvs {
#define HAL_RX_TLV_AMPDU_FLAG_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_AMPDU_FLAG_GET(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).ampdu_flag HAL_RX_MPDU_START(_rx_pkt_tlv).ampdu_flag
#define HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).sw_frame_group_id
#define HAL_RX_TLV_KEYID_OCTET_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_KEYID_OCTET_GET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).key_id_octet HAL_RX_MSDU_END(_rx_pkt_tlv).key_id_octet
@@ -313,9 +326,6 @@ struct rx_pkt_tlvs {
#define HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_pkt_tlv) \ #define HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_sequence_control_valid HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_sequence_control_valid
#define HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).sw_frame_group_id
#define HAL_RX_TLV_MPDU_QOS_CONTROL_VALID_GET(_rx_pkt_tlv) \ #define HAL_RX_TLV_MPDU_QOS_CONTROL_VALID_GET(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_qos_control_valid HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_qos_control_valid
@@ -325,12 +335,6 @@ struct rx_pkt_tlvs {
#define HAL_RX_GET_TO_DS_FLAG(_rx_pkt_tlv) \ #define HAL_RX_GET_TO_DS_FLAG(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).to_ds HAL_RX_MPDU_START(_rx_pkt_tlv).to_ds
#define HAL_RX_GET_FILTER_CATEGORY(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).rxpcu_mpdu_filter_in_category
#define HAL_RX_GET_PPDU_ID(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).phy_ppdu_id
#define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_pkt_tlv) \ #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_field HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_frame_control_field
@@ -373,13 +377,19 @@ struct rx_pkt_tlvs {
#define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(_rx_pkt_tlv) \ #define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).cumulative_ip_length HAL_RX_MSDU_END(_rx_pkt_tlv).cumulative_ip_length
#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_pkt_tlv) \
HAL_RX_MPDU_START(_rx_pkt_tlv).mpdu_qos_control_valid
#define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_pkt_tlv) \
HAL_RX_MSDU_END(_rx_pkt_tlv).sa_sw_peer_id
static inline static inline
uint32_t hal_rx_tlv_decap_format_get_be(void *hw_desc_addr) uint32_t hal_rx_tlv_decap_format_get_be(void *hw_desc_addr)
{ {
struct rx_pkt_tlvs *rx_pkt_tlvs = struct rx_pkt_tlvs *rx_pkt_tlvs =
(struct rx_pkt_tlvs *)hw_desc_addr; (struct rx_pkt_tlvs *)hw_desc_addr;
return rx_pkt_tlvs->msdu_end_tlv.rx_msdu_end.decap_format; return HAL_RX_TLV_DECAP_FORMAT_GET(rx_pkt_tlvs);
} }
static inline uint32_t hal_rx_tlv_msdu_done_get_be(uint8_t *buf) static inline uint32_t hal_rx_tlv_msdu_done_get_be(uint8_t *buf)
@@ -391,7 +401,7 @@ static inline uint32_t hal_rx_tlv_msdu_done_get_be(uint8_t *buf)
* hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention
* @buf: pointer to rx_pkt_tlvs * @buf: pointer to rx_pkt_tlvs
* *
* reutm: uint32_t(first_msdu) * return: uint32_t(first_msdu)
*/ */
static inline uint32_t hal_rx_tlv_first_mpdu_get_be(uint8_t *buf) static inline uint32_t hal_rx_tlv_first_mpdu_get_be(uint8_t *buf)
{ {
@@ -400,20 +410,6 @@ static inline uint32_t hal_rx_tlv_first_mpdu_get_be(uint8_t *buf)
return HAL_RX_TLV_FIRST_MPDU_GET(rx_pkt_tlvs); return HAL_RX_TLV_FIRST_MPDU_GET(rx_pkt_tlvs);
} }
/*
* hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
* from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* Return: phy_ppdu_id
*/
static inline uint16_t hal_rx_tlv_phy_ppdu_id_get_be(uint8_t *buf)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs);
}
/* /*
* hal_rx_msdu_cce_match_get(): get CCE match bit * hal_rx_msdu_cce_match_get(): get CCE match bit
* from rx attention * from rx attention
@@ -427,6 +423,52 @@ static inline bool hal_rx_msdu_cce_match_get_be(uint8_t *buf)
return HAL_RX_TLV_CCE_MATCH_GET(rx_pkt_tlvs); return HAL_RX_TLV_CCE_MATCH_GET(rx_pkt_tlvs);
} }
/*
* hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
* from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* Return: phy_ppdu_id
*/
static inline uint16_t hal_rx_attn_phy_ppdu_id_get_be(uint8_t *buf)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint16_t phy_ppdu_id;
phy_ppdu_id = HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs);
return phy_ppdu_id;
}
/*
* hal_rx_tlv_phy_ppdu_id_get(): get phy_ppdu_id value
* from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* Return: phy_ppdu_id
*/
static inline uint16_t hal_rx_tlv_phy_ppdu_id_get_be(uint8_t *buf)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs);
}
/*
* hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv
*
* @buf: rx_tlv_hdr of the received packet
* @peer_mdata: peer meta data to be set.
* Return: void
*/
static inline void
hal_rx_mpdu_peer_meta_data_set_be(uint8_t *buf, uint32_t peer_mdata)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
HAL_RX_TLV_PEER_META_DATA_GET(rx_pkt_tlvs) = peer_mdata;
}
/* /*
* Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
*/ */
@@ -452,22 +494,7 @@ static inline bool hal_rx_mpdu_info_ampdu_flag_get_be(uint8_t *buf)
return !!HAL_RX_TLV_AMPDU_FLAG_GET(rx_pkt_tlvs); return !!HAL_RX_TLV_AMPDU_FLAG_GET(rx_pkt_tlvs);
} }
/* /**
* @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv
*
* @ buf: rx_tlv_hdr of the received packet
* @ peer_mdata: peer meta data to be set.
* @ Return: void
*/
static inline void
hal_rx_mpdu_peer_meta_data_set_be(uint8_t *buf, uint32_t peer_mdata)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
HAL_RX_TLV_PEER_META_DATA_GET(rx_pkt_tlvs) = peer_mdata;
}
/**
* hal_rx_tlv_msdu_len_get(): API to get the MSDU length * hal_rx_tlv_msdu_len_get(): API to get the MSDU length
* from rx_msdu_start TLV * from rx_msdu_start TLV
* *
@@ -556,28 +583,6 @@ static inline uint32_t hal_rx_tlv_rate_mcs_get_be(uint8_t *buf)
return rate_mcs; return rate_mcs;
} }
/*
* hal_rx_tlv_msdu_get_is_decrypted(): API to get the decrypt status of the
* packet from rx_attention
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(decryt status)
*/
static inline uint32_t hal_rx_tlv_msdu_get_is_decrypted_be(uint8_t *buf)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint32_t is_decrypt = 0;
uint32_t decrypt_status;
decrypt_status = HAL_RX_TLV_DECRYPT_STATUS_GET(rx_pkt_tlvs);
if (!decrypt_status)
is_decrypt = 1;
return is_decrypt;
}
/* /*
* Get key index from RX_MSDU_END * Get key index from RX_MSDU_END
*/ */
@@ -589,7 +594,7 @@ static inline uint32_t hal_rx_tlv_msdu_get_is_decrypted_be(uint8_t *buf)
* Return: uint32_t(key id) * Return: uint32_t(key id)
*/ */
static inline uint32_t hal_rx_msdu_get_keyid_be(uint8_t *buf) static inline uint8_t hal_rx_msdu_get_keyid_be(uint8_t *buf)
{ {
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint32_t keyid_octet; uint32_t keyid_octet;
@@ -1247,23 +1252,6 @@ static inline uint8_t hal_rx_get_mpdu_sequence_control_valid_be(uint8_t *buf)
return HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_pkt_tlvs); return HAL_RX_TLV_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_pkt_tlvs);
} }
/**
* hal_rx_is_unicast_be: check packet is unicast frame or not.
*
* @ buf: pointer to rx pkt TLV.
*
* Return: true on unicast.
*/
static inline bool hal_rx_is_unicast_be(uint8_t *buf)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint32_t grp_id;
grp_id = HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(rx_pkt_tlvs);
return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
}
/** /**
* hal_rx_tid_get_be: get tid based on qos control valid. * hal_rx_tid_get_be: get tid based on qos control valid.
* @hal_soc_hdl: hal_soc handle * @hal_soc_hdl: hal_soc handle
@@ -1284,22 +1272,6 @@ static inline uint32_t hal_rx_tid_get_be(hal_soc_handle_t hal_soc_hdl,
return HAL_RX_NON_QOS_TID; return HAL_RX_NON_QOS_TID;
} }
/**
* hal_rx_hw_desc_get_ppduid_get_be(): retrieve ppdu id
* @rx_tlv_hdr: start address of rx_pkt_tlvs
* @rxdma_dst_ring_desc: Rx HW descriptor
*
* Return: ppdu id
*/
static inline uint32_t
hal_rx_hw_desc_get_ppduid_get_be(void *rx_tlv_hdr, void *rxdma_dst_ring_desc)
{
struct rx_pkt_tlvs *rx_pkt_tlvs =
(struct rx_pkt_tlvs *)rx_tlv_hdr;
return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs);
}
static inline static inline
uint8_t hal_rx_get_fc_valid_be(uint8_t *buf) uint8_t hal_rx_get_fc_valid_be(uint8_t *buf)
{ {
@@ -1322,6 +1294,22 @@ static inline uint8_t hal_rx_get_mac_addr2_valid_be(uint8_t *buf)
return HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_pkt_tlvs); return HAL_RX_TLV_MPDU_MAC_ADDR_AD2_VALID_GET(rx_pkt_tlvs);
} }
/**
* hal_rx_is_unicast_be: check packet is unicast frame or not.
*
* @ buf: pointer to rx pkt TLV.
* Return: true on unicast.
*/
static inline bool hal_rx_is_unicast_be(uint8_t *buf)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint32_t grp_id;
grp_id = HAL_RX_TLV_SW_FRAME_GROUP_ID_GET(rx_pkt_tlvs);
return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
}
static inline uint8_t hal_rx_get_filter_category_be(uint8_t *buf) static inline uint8_t hal_rx_get_filter_category_be(uint8_t *buf)
{ {
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
@@ -1329,6 +1317,22 @@ static inline uint8_t hal_rx_get_filter_category_be(uint8_t *buf)
return HAL_RX_GET_FILTER_CATEGORY(rx_pkt_tlvs); return HAL_RX_GET_FILTER_CATEGORY(rx_pkt_tlvs);
} }
/**
* hal_rx_hw_desc_get_ppduid_get_be(): retrieve ppdu id
* @rx_tlv_hdr: start address of rx_pkt_tlvs
* @rxdma_dst_ring_desc: Rx HW descriptor
*
* Return: ppdu id
*/
static inline uint32_t
hal_rx_hw_desc_get_ppduid_get_be(void *rx_tlv_hdr, void *rxdma_dst_ring_desc)
{
struct rx_pkt_tlvs *rx_pkt_tlvs =
(struct rx_pkt_tlvs *)rx_tlv_hdr;
return HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs);
}
static inline uint32_t static inline uint32_t
hal_rx_get_ppdu_id_be(uint8_t *buf) hal_rx_get_ppdu_id_be(uint8_t *buf)
{ {
@@ -1477,6 +1481,7 @@ uint16_t hal_rx_get_rx_sequence_be(uint8_t *buf)
return HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs); return HAL_RX_MPDU_SEQUENCE_NUMBER_GET(rx_pkt_tlvs);
} }
#ifdef RECEIVE_OFFLOAD
/** /**
* hal_rx_get_fisa_cumulative_l4_checksum_be() - Retrieve cumulative * hal_rx_get_fisa_cumulative_l4_checksum_be() - Retrieve cumulative
* checksum * checksum
@@ -1520,6 +1525,7 @@ bool hal_rx_get_udp_proto_be(uint8_t *buf)
return HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs); return HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs);
} }
#endif
/** /**
* hal_rx_get_flow_agg_continuation_be() - retrieve flow agg * hal_rx_get_flow_agg_continuation_be() - retrieve flow agg
@@ -1611,6 +1617,7 @@ static inline uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); return RX_PKT_TLV_OFFSET(pkt_hdr_tlv);
} }
#ifdef RECEIVE_OFFLOAD
static inline int static inline int
hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv, hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv,
struct hal_offload_info *offload_info) struct hal_offload_info *offload_info)
@@ -1634,23 +1641,32 @@ hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv,
return 0; return 0;
} }
/* static inline int hal_rx_get_proto_params_be(uint8_t *buf, void *proto_params)
* hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
* from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* Return: phy_ppdu_id
*/
static inline uint16_t hal_rx_attn_phy_ppdu_id_get_be(uint8_t *buf)
{ {
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint16_t phy_ppdu_id; struct hal_proto_params *param =
(struct hal_proto_params *)proto_params;
phy_ppdu_id = HAL_RX_TLV_PHY_PPDU_ID_GET(rx_pkt_tlvs); param->tcp_proto = HAL_RX_TLV_GET_IP_OFFSET(rx_pkt_tlvs);
param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs);
param->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_pkt_tlvs);
return phy_ppdu_id; return 0;
} }
static inline int hal_rx_get_l3_l4_offsets_be(uint8_t *buf,
uint32_t *l3_hdr_offset,
uint32_t *l4_hdr_offset)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
*l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(rx_pkt_tlvs);
*l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_pkt_tlvs);
return 0;
}
#endif
/** /**
* hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length
* from rx_msdu_start TLV * from rx_msdu_start TLV
@@ -1663,7 +1679,6 @@ static inline uint32_t hal_rx_msdu_start_msdu_len_get_be(uint8_t *buf)
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint32_t msdu_len; uint32_t msdu_len;
// msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
msdu_len = HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs); msdu_len = HAL_RX_TLV_MSDU_LEN_GET(rx_pkt_tlvs);
return msdu_len; return msdu_len;
@@ -1686,18 +1701,6 @@ static inline uint16_t hal_rx_get_frame_ctrl_field_be(uint8_t *buf)
return frame_ctrl; return frame_ctrl;
} }
static inline int hal_rx_get_proto_params_be(uint8_t *buf, void *proto_params)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct hal_proto_params *param = (struct hal_proto_params *)proto_params;
param->tcp_proto = HAL_RX_TLV_GET_IP_OFFSET(rx_pkt_tlvs);
param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(rx_pkt_tlvs);
param->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_pkt_tlvs);
return 0;
}
/* /*
* hal_rx_tlv_get_is_decrypted_be(): API to get the decrypt status of the * hal_rx_tlv_get_is_decrypted_be(): API to get the decrypt status of the
* packet from msdu_end * packet from msdu_end
@@ -1719,18 +1722,6 @@ static inline uint32_t hal_rx_tlv_get_is_decrypted_be(uint8_t *buf)
return is_decrypt; return is_decrypt;
} }
static inline int hal_rx_get_l3_l4_offsets_be(uint8_t *buf,
uint32_t *l3_hdr_offset,
uint32_t *l4_hdr_offset)
{
struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
*l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(rx_pkt_tlvs);
*l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_pkt_tlvs);
return 0;
}
//TODO - Currently going with NO-PKT-HDR, need to add pkt hdr tlv and check //TODO - Currently going with NO-PKT-HDR, need to add pkt hdr tlv and check
static inline uint8_t *hal_rx_pkt_hdr_get_be(uint8_t *buf) static inline uint8_t *hal_rx_pkt_hdr_get_be(uint8_t *buf)
{ {
@@ -1860,4 +1851,36 @@ hal_rx_msdu_start_msdu_len_set_be(uint8_t *buf, uint32_t len)
HAL_RX_TLV_MSDU_LEN_GET(buf) = len; HAL_RX_TLV_MSDU_LEN_GET(buf) = len;
} }
/**
* hal_rx_mpdu_start_mpdu_qos_control_valid_get_be():
* Retrieve qos control valid bit from the tlv.
* @buf: pointer to rx pkt TLV.
*
* Return: qos control value.
*/
static inline uint32_t
hal_rx_mpdu_start_mpdu_qos_control_valid_get_be(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(pkt_tlvs);
}
/**
* hal_rx_msdu_end_sa_sw_peer_id_get_be(): API to get the
* sa_sw_peer_id from rx_msdu_end TLV
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: sa_sw_peer_id index
*/
static inline uint32_t
hal_rx_msdu_end_sa_sw_peer_id_get_be(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
hal_rx_msdu_end_t *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
}
#endif /* _HAL_BE_RX_TLV_H_ */ #endif /* _HAL_BE_RX_TLV_H_ */

1
hal/wifi3.0/hal_generic_api.h
View File

@@ -19,6 +19,7 @@
#define _HAL_GENERIC_API_H_ #define _HAL_GENERIC_API_H_
#include <hal_rx.h> #include <hal_rx.h>
#include "hal_api_mon.h"
/** /**
* hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value * hal_get_radiotap_he_gi_ltf() - Convert HE ltf and GI value

218
hal/wifi3.0/hal_internal.h
View File

@@ -152,97 +152,137 @@ enum hal_srng_ring_id {
HAL_SRNG_REO2SW7 = 7, HAL_SRNG_REO2SW7 = 7,
HAL_SRNG_REO2SW8 = 8, HAL_SRNG_REO2SW8 = 8,
HAL_SRNG_REO2TCL = 9, HAL_SRNG_REO2TCL = 9,
HAL_SRNG_SW2REO = 10, HAL_SRNG_REO2PPE = 10,
HAL_SRNG_SW2REO1 = 11, /* 11-15 unused */
HAL_SRNG_REO_CMD = 12, HAL_SRNG_SW2REO = 16,
HAL_SRNG_REO_STATUS = 13, HAL_SRNG_SW2REO1 = 17,
/* 14-15 unused */ HAL_SRNG_SW2REO2 = 18,
HAL_SRNG_SW2TCL1 = 16, HAL_SRNG_SW2REO3 = 19,
HAL_SRNG_SW2TCL2 = 17, HAL_SRNG_REO_CMD = 20,
HAL_SRNG_SW2TCL3 = 18, HAL_SRNG_REO_STATUS = 21,
HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ /* 22-23 unused */
HAL_SRNG_SW2TCL5 = 20, HAL_SRNG_SW2TCL1 = 24,
/* 20-23 unused */ HAL_SRNG_SW2TCL2 = 25,
HAL_SRNG_SW2TCL_CMD = 24, HAL_SRNG_SW2TCL3 = 26,
HAL_SRNG_TCL_STATUS = 25, HAL_SRNG_SW2TCL4 = 27,
/* 26-31 unused */ HAL_SRNG_SW2TCL5 = 28,
HAL_SRNG_CE_0_SRC = 32, HAL_SRNG_SW2TCL6 = 29,
HAL_SRNG_CE_1_SRC = 33, HAL_SRNG_PPE2TCL1 = 30,
HAL_SRNG_CE_2_SRC = 34, /* 31-39 unused */
HAL_SRNG_CE_3_SRC = 35, HAL_SRNG_SW2TCL_CMD = 40,
HAL_SRNG_CE_4_SRC = 36, HAL_SRNG_TCL_STATUS = 41,
HAL_SRNG_CE_5_SRC = 37, HAL_SRNG_SW2TCL_CREDIT = 42,
HAL_SRNG_CE_6_SRC = 38, /* 43-63 unused */
HAL_SRNG_CE_7_SRC = 39, HAL_SRNG_CE_0_SRC = 64,
HAL_SRNG_CE_8_SRC = 40, HAL_SRNG_CE_1_SRC = 65,
HAL_SRNG_CE_9_SRC = 41, HAL_SRNG_CE_2_SRC = 66,
HAL_SRNG_CE_10_SRC = 42, HAL_SRNG_CE_3_SRC = 67,
HAL_SRNG_CE_11_SRC = 43, HAL_SRNG_CE_4_SRC = 68,
/* 44-55 unused */ HAL_SRNG_CE_5_SRC = 69,
HAL_SRNG_CE_0_DST = 56, HAL_SRNG_CE_6_SRC = 70,
HAL_SRNG_CE_1_DST = 57, HAL_SRNG_CE_7_SRC = 71,
HAL_SRNG_CE_2_DST = 58, HAL_SRNG_CE_8_SRC = 72,
HAL_SRNG_CE_3_DST = 59, HAL_SRNG_CE_9_SRC = 73,
HAL_SRNG_CE_4_DST = 60, HAL_SRNG_CE_10_SRC = 74,
HAL_SRNG_CE_5_DST = 61, HAL_SRNG_CE_11_SRC = 75,
HAL_SRNG_CE_6_DST = 62, HAL_SRNG_CE_12_SRC = 76,
HAL_SRNG_CE_7_DST = 63, HAL_SRNG_CE_13_SRC = 77,
HAL_SRNG_CE_8_DST = 64, HAL_SRNG_CE_14_SRC = 78,
HAL_SRNG_CE_9_DST = 65, HAL_SRNG_CE_15_SRC = 79,
HAL_SRNG_CE_10_DST = 66, /* 80 */
HAL_SRNG_CE_11_DST = 67, HAL_SRNG_CE_0_DST = 81,
/* 68-79 unused */ HAL_SRNG_CE_1_DST = 82,
HAL_SRNG_CE_0_DST_STATUS = 80, HAL_SRNG_CE_2_DST = 83,
HAL_SRNG_CE_1_DST_STATUS = 81, HAL_SRNG_CE_3_DST = 84,
HAL_SRNG_CE_2_DST_STATUS = 82, HAL_SRNG_CE_4_DST = 85,
HAL_SRNG_CE_3_DST_STATUS = 83, HAL_SRNG_CE_5_DST = 86,
HAL_SRNG_CE_4_DST_STATUS = 84, HAL_SRNG_CE_6_DST = 87,
HAL_SRNG_CE_5_DST_STATUS = 85, HAL_SRNG_CE_7_DST = 89,
HAL_SRNG_CE_6_DST_STATUS = 86, HAL_SRNG_CE_8_DST = 90,
HAL_SRNG_CE_7_DST_STATUS = 87, HAL_SRNG_CE_9_DST = 91,
HAL_SRNG_CE_8_DST_STATUS = 88, HAL_SRNG_CE_10_DST = 92,
HAL_SRNG_CE_9_DST_STATUS = 89, HAL_SRNG_CE_11_DST = 93,
HAL_SRNG_CE_10_DST_STATUS = 90, HAL_SRNG_CE_12_DST = 94,
HAL_SRNG_CE_11_DST_STATUS = 91, HAL_SRNG_CE_13_DST = 95,
/* 92-103 unused */ HAL_SRNG_CE_14_DST = 96,
HAL_SRNG_WBM_IDLE_LINK = 104, HAL_SRNG_CE_15_DST = 97,
HAL_SRNG_WBM_SW_RELEASE = 105, /* 98-99 unused */
HAL_SRNG_WBM2SW0_RELEASE = 106, HAL_SRNG_CE_0_DST_STATUS = 100,
HAL_SRNG_WBM2SW1_RELEASE = 107, HAL_SRNG_CE_1_DST_STATUS = 101,
HAL_SRNG_WBM2SW2_RELEASE = 108, HAL_SRNG_CE_2_DST_STATUS = 102,
HAL_SRNG_WBM2SW3_RELEASE = 109, HAL_SRNG_CE_3_DST_STATUS = 103,
HAL_SRNG_WBM2SW4_RELEASE = 110, HAL_SRNG_CE_4_DST_STATUS = 104,
HAL_SRNG_WBM2SW5_RELEASE = 111, HAL_SRNG_CE_5_DST_STATUS = 105,
HAL_SRNG_WBM2SW6_RELEASE = 112, HAL_SRNG_CE_6_DST_STATUS = 106,
/* 113-127 unused */ HAL_SRNG_CE_7_DST_STATUS = 107,
HAL_SRNG_UMAC_ID_END = 127, HAL_SRNG_CE_8_DST_STATUS = 108,
HAL_SRNG_CE_9_DST_STATUS = 109,
HAL_SRNG_CE_10_DST_STATUS = 110,
HAL_SRNG_CE_11_DST_STATUS = 111,
HAL_SRNG_CE_12_DST_STATUS = 112,
HAL_SRNG_CE_13_DST_STATUS = 113,
HAL_SRNG_CE_14_DST_STATUS = 114,
HAL_SRNG_CE_15_DST_STATUS = 115,
/* 116-119 unused */
HAL_SRNG_WBM_IDLE_LINK = 120,
HAL_SRNG_WBM_SW_RELEASE = 121,
HAL_SRNG_WBM_SW1_RELEASE = 122,
HAL_SRNG_WBM_PPE_RELEASE = 123,
/* 124-127 unused */
HAL_SRNG_WBM2SW0_RELEASE = 128,
HAL_SRNG_WBM2SW1_RELEASE = 129,
HAL_SRNG_WBM2SW2_RELEASE = 130,
HAL_SRNG_WBM2SW3_RELEASE = 131,
HAL_SRNG_WBM2SW4_RELEASE = 132,
HAL_SRNG_WBM2SW5_RELEASE = 133,
HAL_SRNG_WBM2SW6_RELEASE = 134,
HAL_SRNG_WBM_ERROR_RELEASE = 135,
/* 136-158 unused */
HAL_SRNG_UMAC_ID_END = 159,
/* Common DMAC rings shared by all LMACs */
HAL_SRNG_SW2RXDMA_BUF0 = 160,
HAL_SRNG_SW2RXDMA_BUF1 = 161,
HAL_SRNG_SW2RXDMA_BUF2 = 162,
/* 163-167 unused */
HAL_SRNG_SW2RXMON_BUF0 = 168,
/* 169-175 unused */
HAL_SRNG_SW2TXMON_BUF0 = 176,
/* 177-183 unused */
HAL_SRNG_DMAC_CMN_ID_END = 183,
/* LMAC rings - The following set will be replicated for each LMAC */ /* LMAC rings - The following set will be replicated for each LMAC */
HAL_SRNG_LMAC1_ID_START = 128, HAL_SRNG_LMAC1_ID_START = 184,
HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START, HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
#ifdef IPA_OFFLOAD #ifdef IPA_OFFLOAD
HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1), HAL_SRNG_WMAC1_SW2RXDMA0_BUF1,
HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2), HAL_SRNG_WMAC1_SW2RXDMA0_BUF2,
HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1), HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
#else #else
HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1), HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
#endif #endif
HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1), HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1), HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF,
HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
(HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1), HAL_SRNG_WMAC1_RXDMA2SW0,
HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1), HAL_SRNG_WMAC1_RXDMA2SW1,
HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1), HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1,
HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1), HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
#ifdef WLAN_FEATURE_CIF_CFR #ifdef WLAN_FEATURE_CIF_CFR
HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), HAL_SRNG_WIFI_POS_SRC_DMA_RING,
HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1), HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
#else #else
HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1), HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
#endif #endif
/* -142 unused */ HAL_SRNG_WMAC1_TXMON2SW0,
HAL_SRNG_LMAC1_ID_END = 143 HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_WMAC1_TXMON2SW0 + 3),
}; };
#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
#define HAL_MAX_LMACS 3
#define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
#define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
#define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS)
/* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */ /* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
enum hal_ring_type { enum hal_ring_type {
REO_DST = 0, REO_DST = 0,
@@ -269,6 +309,11 @@ enum hal_ring_type {
#ifdef WLAN_FEATURE_CIF_CFR #ifdef WLAN_FEATURE_CIF_CFR
WIFI_POS_SRC, WIFI_POS_SRC,
#endif #endif
PPE2TCL,
PPE_RELEASE,
TX_MONITOR_BUF,
TX_MONITOR_DST,
SW2RXDMA_NEW,
MAX_RING_TYPES MAX_RING_TYPES
}; };
@@ -310,13 +355,6 @@ enum SRNG_REGISTERS {
SRNG_REGISTER_MAX, SRNG_REGISTER_MAX,
}; };
#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
#define HAL_MAX_LMACS 3
#define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
#define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
#define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS)
enum hal_srng_dir { enum hal_srng_dir {
HAL_SRNG_SRC_RING, HAL_SRNG_SRC_RING,
HAL_SRNG_DST_RING HAL_SRNG_DST_RING
@@ -1127,6 +1165,8 @@ struct hal_soc {
list_shadow_reg_config[MAX_GENERIC_SHADOW_REG]; list_shadow_reg_config[MAX_GENERIC_SHADOW_REG];
int num_generic_shadow_regs_configured; int num_generic_shadow_regs_configured;
#endif #endif
/* flag to indicate cmn dmac rings in berryllium */
bool dmac_cmn_src_rxbuf_ring;
}; };
#if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \ #if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
@@ -1152,7 +1192,7 @@ void hal_qca6390_attach(struct hal_soc *hal_soc);
void hal_qca6290_attach(struct hal_soc *hal_soc); void hal_qca6290_attach(struct hal_soc *hal_soc);
void hal_qca8074_attach(struct hal_soc *hal_soc); void hal_qca8074_attach(struct hal_soc *hal_soc);
void hal_wcn7850_attach(struct hal_soc *hal_soc); void hal_wcn7850_attach(struct hal_soc *hal_soc);
void hal_qcn9224_attach(struct hal_soc *hal_soc);
/* /*
* hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
* dp_hal_soc handle type * dp_hal_soc handle type

43
hal/wifi3.0/hal_srng.c
View File

@@ -42,6 +42,9 @@ void hal_qca6490_attach(struct hal_soc *hal);
#ifdef QCA_WIFI_QCN9000 #ifdef QCA_WIFI_QCN9000
void hal_qcn9000_attach(struct hal_soc *hal); void hal_qcn9000_attach(struct hal_soc *hal);
#endif #endif
#ifdef QCA_WIFI_QCN9224
void hal_qcn9224_attach(struct hal_soc *hal);
#endif
#ifdef QCA_WIFI_QCN6122 #ifdef QCA_WIFI_QCN6122
void hal_qcn6122_attach(struct hal_soc *hal); void hal_qcn6122_attach(struct hal_soc *hal);
#endif #endif
@@ -121,9 +124,15 @@ static int hal_get_srng_ring_id(struct hal_soc *hal, int ring_type,
return -EINVAL; return -EINVAL;
} }
if (ring_config->lmac_ring) { /*
ring_id = ring_config->start_ring_id + ring_num + * For BE, dmac_cmn_src_rxbuf_ring is set. If this is set
(mac_id * HAL_MAX_RINGS_PER_LMAC); * and ring is dst and also lmac ring then provide ring id per lmac
*/
if (ring_config->lmac_ring &&
(!hal->dmac_cmn_src_rxbuf_ring ||
ring_config->ring_dir == HAL_SRNG_DST_RING)) {
ring_id = (ring_config->start_ring_id + ring_num +
(mac_id * HAL_MAX_RINGS_PER_LMAC));
} else { } else {
ring_id = ring_config->start_ring_id + ring_num; ring_id = ring_config->start_ring_id + ring_num;
} }
@@ -137,6 +146,7 @@ static struct hal_srng *hal_get_srng(struct hal_soc *hal, int ring_id)
return &(hal->srng_list[ring_id]); return &(hal->srng_list[ring_id]);
} }
#ifndef SHADOW_REG_CONFIG_DISABLED
#define HP_OFFSET_IN_REG_START 1 #define HP_OFFSET_IN_REG_START 1
#define OFFSET_FROM_HP_TO_TP 4 #define OFFSET_FROM_HP_TO_TP 4
static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc, static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc,
@@ -170,6 +180,7 @@ static void hal_update_srng_hp_tp_address(struct hal_soc *hal_soc,
} }
} }
#endif
#ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE #ifdef GENERIC_SHADOW_REGISTER_ACCESS_ENABLE
void hal_set_one_target_reg_config(struct hal_soc *hal, void hal_set_one_target_reg_config(struct hal_soc *hal,
@@ -246,6 +257,8 @@ QDF_STATUS hal_construct_shadow_regs(void *hal_soc)
qdf_export_symbol(hal_construct_shadow_regs); qdf_export_symbol(hal_construct_shadow_regs);
#endif #endif
#ifndef SHADOW_REG_CONFIG_DISABLED
QDF_STATUS hal_set_one_shadow_config(void *hal_soc, QDF_STATUS hal_set_one_shadow_config(void *hal_soc,
int ring_type, int ring_type,
int ring_num) int ring_num)
@@ -313,6 +326,22 @@ QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
} }
qdf_export_symbol(hal_construct_srng_shadow_regs); qdf_export_symbol(hal_construct_srng_shadow_regs);
#else
QDF_STATUS hal_construct_srng_shadow_regs(void *hal_soc)
{
return QDF_STATUS_SUCCESS;
}
qdf_export_symbol(hal_construct_srng_shadow_regs);
QDF_STATUS hal_set_one_shadow_config(void *hal_soc, int ring_type,
int ring_num)
{
return QDF_STATUS_SUCCESS;
}
qdf_export_symbol(hal_set_one_shadow_config);
#endif
void hal_get_shadow_config(void *hal_soc, void hal_get_shadow_config(void *hal_soc,
struct pld_shadow_reg_v2_cfg **shadow_config, struct pld_shadow_reg_v2_cfg **shadow_config,
@@ -327,7 +356,6 @@ void hal_get_shadow_config(void *hal_soc,
qdf_export_symbol(hal_get_shadow_config); qdf_export_symbol(hal_get_shadow_config);
static bool hal_validate_shadow_register(struct hal_soc *hal, static bool hal_validate_shadow_register(struct hal_soc *hal,
uint32_t *destination, uint32_t *destination,
uint32_t *shadow_address) uint32_t *shadow_address)
@@ -453,6 +481,13 @@ static void hal_target_based_configure(struct hal_soc *hal)
hal->static_window_map = true; hal->static_window_map = true;
hal_qca5018_attach(hal); hal_qca5018_attach(hal);
break; break;
#endif
#ifdef QCA_WIFI_QCN9224
case TARGET_TYPE_QCN9224:
hal->use_register_windowing = true;
hal->static_window_map = true;
hal_qcn9224_attach(hal);
break;
#endif #endif
default: default:
break; break;

58
hal/wifi3.0/li/hal_li_generic_api.c
View File

@@ -269,45 +269,6 @@ static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset,
return 0; return 0;
} }
/**
* hal_rx_mpdu_end_mic_err_get_li(): API to get the MIC ERR
* from rx_mpdu_end TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(mic_err)
*/
static inline uint32_t hal_rx_mpdu_end_mic_err_get_li(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_mpdu_end *mpdu_end =
&pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
uint32_t mic_err;
mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
return mic_err;
}
/*
* hal_rx_msdu_start_get_pkt_type_li(): API to get the pkt type
* from rx_msdu_start
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(pkt type)
*/
static inline uint32_t hal_rx_msdu_start_get_pkt_type_li(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t pkt_type;
pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
return pkt_type;
}
/** /**
* hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV
* @buf: rx tlv address * @buf: rx tlv address
@@ -350,25 +311,6 @@ static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf)
} }
#endif #endif
/*
* hal_rx_msdu_start_bw_get_li(): API to get the Bandwidth
* Interval from rx_msdu_start
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(bw)
*/
static inline uint32_t hal_rx_bw_bw_get_li(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t bw;
bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
return bw;
}
/** /**
* hal_rx_priv_info_set_in_tlv_li(): Save the private info to * hal_rx_priv_info_set_in_tlv_li(): Save the private info to
* the reserved bytes of rx_tlv_hdr * the reserved bytes of rx_tlv_hdr

140
hal/wifi3.0/li/hal_li_rx.h
View File

@@ -389,24 +389,6 @@ static inline void hal_rx_mon_dest_get_buffer_info_from_tlv(
RX_ATTENTION_1_FIRST_MPDU_MASK, \ RX_ATTENTION_1_FIRST_MPDU_MASK, \
RX_ATTENTION_1_FIRST_MPDU_LSB)) RX_ATTENTION_1_FIRST_MPDU_LSB))
/*
* hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* reutm: uint32_t(first_msdu)
*/
static inline uint32_t
hal_rx_attn_first_mpdu_get(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint32_t first_mpdu;
first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
return first_mpdu;
}
#define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \
@@ -672,50 +654,12 @@ hal_rx_msdu_start_toeplitz_get(uint8_t *buf)
RX_MSDU_START_5_SGI_OFFSET)), \ RX_MSDU_START_5_SGI_OFFSET)), \
RX_MSDU_START_5_SGI_MASK, \ RX_MSDU_START_5_SGI_MASK, \
RX_MSDU_START_5_SGI_LSB)) RX_MSDU_START_5_SGI_LSB))
/**
* hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd
* Interval from rx_msdu_start TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(sgi)
*/
static inline uint32_t
hal_rx_msdu_start_sgi_get(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t sgi;
sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
return sgi;
}
#define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_RATE_MCS_OFFSET)), \ RX_MSDU_START_5_RATE_MCS_OFFSET)), \
RX_MSDU_START_5_RATE_MCS_MASK, \ RX_MSDU_START_5_RATE_MCS_MASK, \
RX_MSDU_START_5_RATE_MCS_LSB)) RX_MSDU_START_5_RATE_MCS_LSB))
/**
* hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate
* from rx_msdu_start TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(rate_mcs)
*/
static inline uint32_t
hal_rx_msdu_start_rate_mcs_get(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t rate_mcs;
rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
return rate_mcs;
}
#define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
@@ -723,30 +667,6 @@ hal_rx_msdu_start_rate_mcs_get(uint8_t *buf)
RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
/*
* hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the
* packet from rx_attention
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(decryt status)
*/
static inline uint32_t
hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint32_t is_decrypt = 0;
uint32_t decrypt_status;
decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
if (!decrypt_status)
is_decrypt = 1;
return is_decrypt;
}
/* /*
* Get key index from RX_MSDU_END * Get key index from RX_MSDU_END
*/ */
@@ -787,27 +707,6 @@ hal_rx_msdu_start_get_rssi(uint8_t *buf)
RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
/*
* hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel
* from rx_msdu_start
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(frequency)
*/
static inline uint32_t
hal_rx_msdu_start_get_freq(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t freq;
freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
return freq;
}
#define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
@@ -836,51 +735,12 @@ hal_rx_msdu_start_get_freq(uint8_t *buf)
RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
/**
* hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR
* from rx_mpdu_end TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(decrypt_err)
*/
static inline uint32_t
hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_mpdu_end *mpdu_end =
&pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
uint32_t decrypt_err;
decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
return decrypt_err;
}
#define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
/**
* hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR
* from rx_mpdu_end TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(mic_err)
*/
static inline uint32_t
hal_rx_mpdu_end_mic_err_get(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_mpdu_end *mpdu_end =
&pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
uint32_t mic_err;
mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
return mic_err;
}
/******************************************************************************* /*******************************************************************************
* RX REO ERROR APIS * RX REO ERROR APIS

6
hal/wifi3.0/qca5018/hal_5018.c
View File

@@ -2238,6 +2238,12 @@ struct hal_hw_srng_config hw_srng_table_5018[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

6
hal/wifi3.0/qca6290/hal_6290.c
View File

@@ -1619,6 +1619,12 @@ struct hal_hw_srng_config hw_srng_table_6290[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

6
hal/wifi3.0/qca6390/hal_6390.c
View File

@@ -1687,6 +1687,12 @@ struct hal_hw_srng_config hw_srng_table_6390[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

6
hal/wifi3.0/qca6490/hal_6490.c
View File

@@ -2277,6 +2277,12 @@ struct hal_hw_srng_config hw_srng_table_6490[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

6
hal/wifi3.0/qca6750/hal_6750.c
View File

@@ -2431,6 +2431,12 @@ struct hal_hw_srng_config hw_srng_table_6750[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

6
hal/wifi3.0/qca8074v1/hal_8074v1.c
View File

@@ -1802,6 +1802,12 @@ struct hal_hw_srng_config hw_srng_table_8074[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

6
hal/wifi3.0/qca8074v2/hal_8074v2.c
View File

@@ -1805,6 +1805,12 @@ struct hal_hw_srng_config hw_srng_table_8074v2[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };

6
hal/wifi3.0/qcn6122/hal_qcn6122.c
View File

@@ -2304,6 +2304,12 @@ struct hal_hw_srng_config hw_srng_table_6122[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

6
hal/wifi3.0/qcn9000/hal_9000.c
View File

@@ -2339,6 +2339,12 @@ struct hal_hw_srng_config hw_srng_table_9000[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**

408
hal/wifi3.0/qcn9224/hal_9224.c
View File

@@ -132,10 +132,280 @@
(UMAC_WINDOW_ADDRESS_9224 << 12) | \ (UMAC_WINDOW_ADDRESS_9224 << 12) | \
WINDOW_ENABLE_BIT) WINDOW_ENABLE_BIT)
/* For Berryllium sw2rxdma ring size increased to 20 bits */
#define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
#ifdef CONFIG_WORD_BASED_TLV
struct rx_msdu_end_compact_qca9224 {
uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
sw_frame_group_id : 7, // [8:2]
reserved_0 : 7, // [15:9]
phy_ppdu_id : 16; // [31:16]
uint32_t ip_hdr_chksum : 16, // [15:0]
reported_mpdu_length : 14, // [29:16]
reserved_1a : 2; // [31:30]
uint32_t key_id_octet : 8, // [7:0]
cce_super_rule : 6, // [13:8]
cce_classify_not_done_truncate : 1, // [14:14]
cce_classify_not_done_cce_dis : 1, // [15:15]
cumulative_l3_checksum : 16; // [31:16]
uint32_t rule_indication_31_0 : 32; // [31:0]
uint32_t rule_indication_63_32 : 32; // [31:0]
uint32_t da_offset : 6, // [5:0]
sa_offset : 6, // [11:6]
da_offset_valid : 1, // [12:12]
sa_offset_valid : 1, // [13:13]
reserved_5a : 2, // [15:14]
l3_type : 16; // [31:16]
uint32_t ipv6_options_crc : 32; // [31:0]
uint32_t tcp_seq_number : 32; // [31:0]
uint32_t tcp_ack_number : 32; // [31:0]
uint32_t tcp_flag : 9, // [8:0]
lro_eligible : 1, // [9:9]
reserved_9a : 6, // [15:10]
window_size : 16; // [31:16]
uint32_t tcp_udp_chksum : 16, // [15:0]
sa_idx_timeout : 1, // [16:16]
da_idx_timeout : 1, // [17:17]
msdu_limit_error : 1, // [18:18]
flow_idx_timeout : 1, // [19:19]
flow_idx_invalid : 1, // [20:20]
wifi_parser_error : 1, // [21:21]
amsdu_parser_error : 1, // [22:22]
sa_is_valid : 1, // [23:23]
da_is_valid : 1, // [24:24]
da_is_mcbc : 1, // [25:25]
l3_header_padding : 2, // [27:26]
first_msdu : 1, // [28:28]
last_msdu : 1, // [29:29]
tcp_udp_chksum_fail_copy : 1, // [30:30]
ip_chksum_fail_copy : 1; // [31:31]
uint32_t sa_idx : 16, // [15:0]
da_idx_or_sw_peer_id : 16; // [31:16]
uint32_t msdu_drop : 1, // [0:0]
reo_destination_indication : 5, // [5:1]
flow_idx : 20, // [25:6]
use_ppe : 1, // [26:26]
reserved_12a : 5; // [31:27]
uint32_t fse_metadata : 32; // [31:0]
uint32_t cce_metadata : 16, // [15:0]
sa_sw_peer_id : 16; // [31:16]
uint32_t aggregation_count : 8, // [7:0]
flow_aggregation_continuation : 1, // [8:8]
fisa_timeout : 1, // [9:9]
reserved_15a : 22; // [31:10]
uint32_t cumulative_l4_checksum : 16, // [15:0]
cumulative_ip_length : 16; // [31:16]
uint32_t reserved_17a : 6, // [5:0]
service_code : 9, // [14:6]
priority_valid : 1, // [15:15]
intra_bss : 1, // [16:16]
dest_chip_id : 2, // [18:17]
multicast_echo : 1, // [19:19]
wds_learning_event : 1, // [20:20]
wds_roaming_event : 1, // [21:21]
wds_keep_alive_event : 1, // [22:22]
reserved_17b : 9; // [31:23]
uint32_t msdu_length : 14, // [13:0]
stbc : 1, // [14:14]
ipsec_esp : 1, // [15:15]
l3_offset : 7, // [22:16]
ipsec_ah : 1, // [23:23]
l4_offset : 8; // [31:24]
uint32_t msdu_number : 8, // [7:0]
decap_format : 2, // [9:8]
ipv4_proto : 1, // [10:10]
ipv6_proto : 1, // [11:11]
tcp_proto : 1, // [12:12]
udp_proto : 1, // [13:13]
ip_frag : 1, // [14:14]
tcp_only_ack : 1, // [15:15]
da_is_bcast_mcast : 1, // [16:16]
toeplitz_hash_sel : 2, // [18:17]
ip_fixed_header_valid : 1, // [19:19]
ip_extn_header_valid : 1, // [20:20]
tcp_udp_header_valid : 1, // [21:21]
mesh_control_present : 1, // [22:22]
ldpc : 1, // [23:23]
ip4_protocol_ip6_next_header : 8; // [31:24]
uint32_t toeplitz_hash_2_or_4 : 32; // [31:0]
uint32_t flow_id_toeplitz : 32; // [31:0]
uint32_t user_rssi : 8, // [7:0]
pkt_type : 4, // [11:8]
sgi : 2, // [13:12]
rate_mcs : 4, // [17:14]
receive_bandwidth : 3, // [20:18]
reception_type : 3, // [23:21]
mimo_ss_bitmap : 8; // [31:24]
uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0]
uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0]
uint32_t sw_phy_meta_data : 32; // [31:0]
uint32_t vlan_ctag_ci : 16, // [15:0]
vlan_stag_ci : 16; // [31:16]
uint32_t reserved_27a : 32; // [31:0]
uint32_t reserved_28a : 32; // [31:0]
uint32_t reserved_29a : 32; // [31:0]
uint32_t first_mpdu : 1, // [0:0]
reserved_30a : 1, // [1:1]
mcast_bcast : 1, // [2:2]
ast_index_not_found : 1, // [3:3]
ast_index_timeout : 1, // [4:4]
power_mgmt : 1, // [5:5]
non_qos : 1, // [6:6]
null_data : 1, // [7:7]
mgmt_type : 1, // [8:8]
ctrl_type : 1, // [9:9]
more_data : 1, // [10:10]
eosp : 1, // [11:11]
a_msdu_error : 1, // [12:12]
fragment_flag : 1, // [13:13]
order : 1, // [14:14]
cce_match : 1, // [15:15]
overflow_err : 1, // [16:16]
msdu_length_err : 1, // [17:17]
tcp_udp_chksum_fail : 1, // [18:18]
ip_chksum_fail : 1, // [19:19]
sa_idx_invalid : 1, // [20:20]
da_idx_invalid : 1, // [21:21]
reserved_30b : 1, // [22:22]
rx_in_tx_decrypt_byp : 1, // [23:23]
encrypt_required : 1, // [24:24]
directed : 1, // [25:25]
buffer_fragment : 1, // [26:26]
mpdu_length_err : 1, // [27:27]
tkip_mic_err : 1, // [28:28]
decrypt_err : 1, // [29:29]
unencrypted_frame_err : 1, // [30:30]
fcs_err : 1; // [31:31]
uint32_t reserved_31a : 10, // [9:0]
decrypt_status_code : 3, // [12:10]
rx_bitmap_not_updated : 1, // [13:13]
reserved_31b : 17, // [30:14]
msdu_done : 1; // [31:31]
};
struct rx_mpdu_start_compact_qca9224 {
struct rxpt_classify_info rxpt_classify_info_details;
uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0]
receive_queue_number : 16, // [23:8]
pre_delim_err_warning : 1, // [24:24]
first_delim_err : 1, // [25:25]
reserved_2a : 6; // [31:26]
uint32_t pn_31_0 : 32; // [31:0]
uint32_t pn_63_32 : 32; // [31:0]
uint32_t pn_95_64 : 32; // [31:0]
uint32_t pn_127_96 : 32; // [31:0]
uint32_t epd_en : 1, // [0:0]
all_frames_shall_be_encrypted : 1, // [1:1]
encrypt_type : 4, // [5:2]
wep_key_width_for_variable_key : 2, // [7:6]
mesh_sta : 2, // [9:8]
bssid_hit : 1, // [10:10]
bssid_number : 4, // [14:11]
tid : 4, // [18:15]
reserved_7a : 13; // [31:19]
uint32_t peer_meta_data : 32; // [31:0]
uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0]
sw_frame_group_id : 7, // [8:2]
ndp_frame : 1, // [9:9]
phy_err : 1, // [10:10]
phy_err_during_mpdu_header : 1, // [11:11]
protocol_version_err : 1, // [12:12]
ast_based_lookup_valid : 1, // [13:13]
ranging : 1, // [14:14]
reserved_9a : 1, // [15:15]
phy_ppdu_id : 16; // [31:16]
uint32_t ast_index : 16, // [15:0]
sw_peer_id : 16; // [31:16]
uint32_t mpdu_frame_control_valid : 1, // [0:0]
mpdu_duration_valid : 1, // [1:1]
mac_addr_ad1_valid : 1, // [2:2]
mac_addr_ad2_valid : 1, // [3:3]
mac_addr_ad3_valid : 1, // [4:4]
mac_addr_ad4_valid : 1, // [5:5]
mpdu_sequence_control_valid : 1, // [6:6]
mpdu_qos_control_valid : 1, // [7:7]
mpdu_ht_control_valid : 1, // [8:8]
frame_encryption_info_valid : 1, // [9:9]
mpdu_fragment_number : 4, // [13:10]
more_fragment_flag : 1, // [14:14]
reserved_11a : 1, // [15:15]
fr_ds : 1, // [16:16]
to_ds : 1, // [17:17]
encrypted : 1, // [18:18]
mpdu_retry : 1, // [19:19]
mpdu_sequence_number : 12; // [31:20]
uint32_t key_id_octet : 8, // [7:0]
new_peer_entry : 1, // [8:8]
decrypt_needed : 1, // [9:9]
decap_type : 2, // [11:10]
rx_insert_vlan_c_tag_padding : 1, // [12:12]
rx_insert_vlan_s_tag_padding : 1, // [13:13]
strip_vlan_c_tag_decap : 1, // [14:14]
strip_vlan_s_tag_decap : 1, // [15:15]
pre_delim_count : 12, // [27:16]
ampdu_flag : 1, // [28:28]
bar_frame : 1, // [29:29]
raw_mpdu : 1, // [30:30]
reserved_12 : 1; // [31:31]
uint32_t mpdu_length : 14, // [13:0]
first_mpdu : 1, // [14:14]
mcast_bcast : 1, // [15:15]
ast_index_not_found : 1, // [16:16]
ast_index_timeout : 1, // [17:17]
power_mgmt : 1, // [18:18]
non_qos : 1, // [19:19]
null_data : 1, // [20:20]
mgmt_type : 1, // [21:21]
ctrl_type : 1, // [22:22]
more_data : 1, // [23:23]
eosp : 1, // [24:24]
fragment_flag : 1, // [25:25]
order : 1, // [26:26]
u_apsd_trigger : 1, // [27:27]
encrypt_required : 1, // [28:28]
directed : 1, // [29:29]
amsdu_present : 1, // [30:30]
reserved_13 : 1; // [31:31]
uint32_t mpdu_frame_control_field : 16, // [15:0]
mpdu_duration_field : 16; // [31:16]
uint32_t mac_addr_ad1_31_0 : 32; // [31:0]
uint32_t mac_addr_ad1_47_32 : 16, // [15:0]
mac_addr_ad2_15_0 : 16; // [31:16]
uint32_t mac_addr_ad2_47_16 : 32; // [31:0]
uint32_t mac_addr_ad3_31_0 : 32; // [31:0]
uint32_t mac_addr_ad3_47_32 : 16, // [15:0]
mpdu_sequence_control_field : 16; // [31:16]
uint32_t mac_addr_ad4_31_0 : 32; // [31:0]
uint32_t mac_addr_ad4_47_32 : 16, // [15:0]
mpdu_qos_control_field : 16; // [31:16]
uint32_t mpdu_ht_control_field : 32; // [31:0]
uint32_t vdev_id : 8, // [7:0]
service_code : 9, // [16:8]
priority_valid : 1, // [17:17]
src_info : 12, // [29:18]
reserved_23a : 1, // [30:30]
multi_link_addr_ad1_ad2_valid : 1; // [31:31]
uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0]
uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0]
multi_link_addr_ad2_15_0 : 16; // [31:16]
uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0]
uint32_t reserved_27a : 32; // [31:0]
uint32_t reserved_28a : 32; // [31:0]
uint32_t reserved_29a : 32; // [31:0]
};
/* TLV struct for word based Tlv */
typedef struct rx_mpdu_start_compact_qca9224 hal_rx_mpdu_start_t;
typedef struct rx_msdu_end_compact_qca9224 hal_rx_msdu_end_t;
#endif /* CONFIG_WORD_BASED_TLV */
#include "hal_9224_rx.h" #include "hal_9224_rx.h"
#include <hal_be_generic_api.h>
#include "hal_9224_tx.h" #include "hal_9224_tx.h"
#include "hal_be_rx_tlv.h" #include "hal_be_rx_tlv.h"
#include <hal_be_generic_api.h>
#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
/** /**
@@ -295,9 +565,14 @@ void hal_rx_get_rtt_info_9224(void *rx_tlv, void *ppdu_info_hdl)
static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart, static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
uint8_t dbg_level) uint8_t dbg_level)
{ {
struct rx_mpdu_start_compact *mpdu_info = #ifdef CONFIG_WORD_BASED_TLV
(struct rx_mpdu_start_compact *)mpdustart; struct rx_mpdu_start_compact_qca9224 *mpdu_info =
(struct rx_mpdu_start_compact_qca9224 *)mpdustart;
#else
struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
struct rx_mpdu_info *mpdu_info =
(struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
#endif
QDF_TRACE(dbg_level, QDF_MODULE_ID_HAL, QDF_TRACE(dbg_level, QDF_MODULE_ID_HAL,
"rx_mpdu_start tlv (1/5) - " "rx_mpdu_start tlv (1/5) - "
"rx_reo_queue_desc_addr_39_32 :%x" "rx_reo_queue_desc_addr_39_32 :%x"
@@ -425,9 +700,13 @@ static inline void hal_rx_dump_mpdu_start_tlv_9224(void *mpdustart,
static void hal_rx_dump_msdu_end_tlv_9224(void *msduend, static void hal_rx_dump_msdu_end_tlv_9224(void *msduend,
uint8_t dbg_level) uint8_t dbg_level)
{ {
struct rx_msdu_end_compact *msdu_end = #ifdef CONFIG_WORD_BASED_TLV
(struct rx_msdu_end_compact *)msduend; struct rx_msdu_end_compact_qca9224 *msdu_end =
(struct rx_msdu_end_compact_qca9224 *)msduend;
#else
struct rx_msdu_end *msdu_end =
(struct rx_msdu_end *)msduend;
#endif
QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
"rx_msdu_end tlv - " "rx_msdu_end tlv - "
"key_id_octet: %d " "key_id_octet: %d "
@@ -920,19 +1199,34 @@ static inline void hal_rx_dump_pkt_hdr_tlv_9224(struct rx_pkt_tlvs *pkt_tlvs,
* *
* Return: void * Return: void
*/ */
#ifdef CONFIG_WORD_BASED_TLV
static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl, static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
uint8_t *buf, uint8_t dbg_level) uint8_t *buf, uint8_t dbg_level)
{ {
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end_compact *msdu_end = struct rx_msdu_end_compact_qca9224 *msdu_end =
&pkt_tlvs->msdu_end_tlv.rx_msdu_end; &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
struct rx_mpdu_start_compact *mpdu_start = struct rx_mpdu_start_compact_qca9224 *mpdu_start =
&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level); hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level);
hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level); hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level);
hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level); hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level);
} }
#else
static void hal_rx_dump_pkt_tlvs_9224(hal_soc_handle_t hal_soc_hdl,
uint8_t *buf, uint8_t dbg_level)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
struct rx_mpdu_start *mpdu_start =
&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
hal_rx_dump_msdu_end_tlv_9224(msdu_end, dbg_level);
hal_rx_dump_mpdu_start_tlv_9224(mpdu_start, dbg_level);
hal_rx_dump_pkt_hdr_tlv_9224(pkt_tlvs, dbg_level);
}
#endif
static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
{ {
@@ -940,7 +1234,6 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_be;
hal_soc->ops->hal_get_window_address = hal_get_window_address_9224; hal_soc->ops->hal_get_window_address = hal_get_window_address_9224;
/* tx */ /* tx */
@@ -966,12 +1259,8 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
/* rx */ /* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = NULL; hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
/* hal_rx_mon_hw_desc_get_mpdu_status_be;
* TODO:
* In below API, stbc is accessed but is not part of
* compact struct hal_rx_mon_hw_desc_get_mpdu_status_be;
*/
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224; hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9224;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_9224; hal_rx_proc_phyrx_other_receive_info_tlv_9224;
@@ -1012,7 +1301,7 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be; hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be; hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_tlv_l3_hdr_padding_get_be; hal_rx_tlv_l3_hdr_padding_get_be;
hal_soc->ops->hal_rx_encryption_info_valid = hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_be; hal_rx_encryption_info_valid_be;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be; hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
@@ -1036,15 +1325,10 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be; hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_be; hal_rx_get_mpdu_sequence_control_valid_be;
/* TODO: sw_frame_group_id not in compact struct */ hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
hal_soc->ops->hal_rx_is_unicast = NULL;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be; hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = NULL; hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
/* hal_rx_hw_desc_get_ppduid_get_be;
* TODO:
* Ppdu_id not present in compact, to be added for monitor mode
* hal_rx_hw_desc_get_ppduid_get_be;
*/
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_be; hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
@@ -1058,14 +1342,10 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be; hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be; hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_be; hal_rx_get_mac_addr2_valid_be;
hal_soc->ops->hal_rx_get_filter_category = NULL; hal_soc->ops->hal_rx_get_filter_category =
/* hal_rx_get_filter_category_be;
* TODO: hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
* Field not present in compact struct - hal_rx_get_filter_category_be;
*/
hal_soc->ops->hal_rx_get_ppdu_id = NULL;
/* TODO: Field not present in compact struct - hal_rx_get_ppdu_id_be; */
hal_soc->ops->hal_reo_config = hal_reo_config_9224; hal_soc->ops->hal_reo_config = hal_reo_config_9224;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be; hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
@@ -1110,51 +1390,30 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_compute_reo_remap_ix2_ix3_9224; hal_compute_reo_remap_ix2_ix3_9224;
hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_be; hal_rx_msdu_get_reo_destination_indication_be;
hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be; hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
hal_soc->ops->hal_rx_msdu_is_wlan_mcast = hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
hal_rx_msdu_is_wlan_mcast_generic_be; hal_rx_msdu_is_wlan_mcast_generic_be;
hal_soc->ops->hal_rx_tlv_decap_format_get = NULL; hal_soc->ops->hal_rx_tlv_decap_format_get =
/* hal_rx_tlv_decap_format_get_be;
* TODO: #ifdef RECEIVE_OFFLOAD
* Decap format not present in hal_soc->ops->hal_rx_tlv_get_offload_info =
* compact struct hal_rx_tlv_decap_format_get_be; hal_rx_tlv_get_offload_info_be;
*/ hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
hal_soc->ops->hal_rx_tlv_get_offload_info = NULL; hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
/* #endif
* TODO: hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
* Some fields not present in hal_rx_attn_phy_ppdu_id_get_be;
* compact struct - hal_rx_tlv_get_offload_info_be;
*/
hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = NULL;
/*
* TODO:
* No Phy ppdu id in compact hal_rx_attn_phy_ppdu_id_get_be;
*/
hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be; hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be;
hal_soc->ops->hal_rx_tlv_msdu_len_get = NULL; hal_soc->ops->hal_rx_tlv_msdu_len_get =
/* hal_rx_msdu_start_msdu_len_get_be;
* TODO:
* msdu_len is not present in compact
* struct hal_rx_msdu_start_msdu_len_get_be;
*/
hal_soc->ops->hal_rx_get_frame_ctrl_field = hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_frame_ctrl_field_be; hal_rx_get_frame_ctrl_field_be;
hal_soc->ops->hal_rx_get_proto_params = NULL;
/* TODO: Not present in compact struct - hal_rx_get_proto_params_be; */
hal_soc->ops->hal_rx_get_l3_l4_offsets = NULL;
/* TODO: Not present in compact struct - hal_rx_get_l3_l4_offsets_be;*/
hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be; hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = NULL; hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
/* hal_rx_mpdu_info_ampdu_flag_get_be;
* TODO: hal_soc->ops->hal_rx_tlv_msdu_len_set =
* Not present in compact struct - hal_rx_mpdu_info_ampdu_flag_get_be; hal_rx_msdu_start_msdu_len_set_be;
*/
hal_soc->ops->hal_rx_tlv_msdu_len_set = NULL;
/*
* TODO:
* Not present in compact struct - hal_rx_msdu_start_msdu_len_set_be;
*/
hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be; hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be; hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be; hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
@@ -1167,6 +1426,11 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_rx_tlv_get_is_decrypted_be; hal_rx_tlv_get_is_decrypted_be;
hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be; hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be; hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
hal_soc->ops->hal_rx_priv_info_set_in_tlv =
hal_rx_priv_info_set_in_tlv_be;
hal_soc->ops->hal_rx_priv_info_get_from_tlv =
hal_rx_priv_info_get_from_tlv_be;
hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
}; };
struct hal_hw_srng_config hw_srng_table_9224[] = { struct hal_hw_srng_config hw_srng_table_9224[] = {

7
hal/wifi3.0/wcn7850/hal_7850.c
View File

@@ -1291,7 +1291,6 @@ static void hal_hw_txrx_ops_attach_wcn7850(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_be;
hal_soc->ops->hal_get_window_address = hal_get_window_address_7850; hal_soc->ops->hal_get_window_address = hal_get_window_address_7850;
hal_soc->ops->hal_reo_set_err_dst_remap = hal_soc->ops->hal_reo_set_err_dst_remap =
hal_reo_set_err_dst_remap_7850; hal_reo_set_err_dst_remap_7850;
@@ -1915,6 +1914,12 @@ struct hal_hw_srng_config hw_srng_table_7850[] = {
.max_size = HAL_RXDMA_MAX_RING_SIZE, .max_size = HAL_RXDMA_MAX_RING_SIZE,
}, },
#endif #endif
{ /* REO2PPE */ 0},
{ /* PPE2TCL */ 0},
{ /* PPE_RELEASE */ 0},
{ /* TX_MONITOR_BUF */ 0},
{ /* TX_MONITOR_DST */ 0},
{ /* SW2RXDMA_NEW */ 0},
}; };
/** /**