qcacmn: Add support for beryllium on WIN

Add support for split between lithium and beryllium
HAL files.
Add Wkk TLV support.

Change-Id: I7135e4061a4c3605d76c70c33320cbd533ea0c62
This commit is contained in:
Chaithanya Garrepalli
2021-08-12 17:12:24 +05:30
committed by Madan Koyyalamudi
parent 6b09fa3913
commit 7ccb73b31f
19 changed files with 765 additions and 508 deletions

View File

@@ -152,97 +152,137 @@ enum hal_srng_ring_id {
HAL_SRNG_REO2SW7 = 7,
HAL_SRNG_REO2SW8 = 8,
HAL_SRNG_REO2TCL = 9,
HAL_SRNG_SW2REO = 10,
HAL_SRNG_SW2REO1 = 11,
HAL_SRNG_REO_CMD = 12,
HAL_SRNG_REO_STATUS = 13,
/* 14-15 unused */
HAL_SRNG_SW2TCL1 = 16,
HAL_SRNG_SW2TCL2 = 17,
HAL_SRNG_SW2TCL3 = 18,
HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */
HAL_SRNG_SW2TCL5 = 20,
/* 20-23 unused */
HAL_SRNG_SW2TCL_CMD = 24,
HAL_SRNG_TCL_STATUS = 25,
/* 26-31 unused */
HAL_SRNG_CE_0_SRC = 32,
HAL_SRNG_CE_1_SRC = 33,
HAL_SRNG_CE_2_SRC = 34,
HAL_SRNG_CE_3_SRC = 35,
HAL_SRNG_CE_4_SRC = 36,
HAL_SRNG_CE_5_SRC = 37,
HAL_SRNG_CE_6_SRC = 38,
HAL_SRNG_CE_7_SRC = 39,
HAL_SRNG_CE_8_SRC = 40,
HAL_SRNG_CE_9_SRC = 41,
HAL_SRNG_CE_10_SRC = 42,
HAL_SRNG_CE_11_SRC = 43,
/* 44-55 unused */
HAL_SRNG_CE_0_DST = 56,
HAL_SRNG_CE_1_DST = 57,
HAL_SRNG_CE_2_DST = 58,
HAL_SRNG_CE_3_DST = 59,
HAL_SRNG_CE_4_DST = 60,
HAL_SRNG_CE_5_DST = 61,
HAL_SRNG_CE_6_DST = 62,
HAL_SRNG_CE_7_DST = 63,
HAL_SRNG_CE_8_DST = 64,
HAL_SRNG_CE_9_DST = 65,
HAL_SRNG_CE_10_DST = 66,
HAL_SRNG_CE_11_DST = 67,
/* 68-79 unused */
HAL_SRNG_CE_0_DST_STATUS = 80,
HAL_SRNG_CE_1_DST_STATUS = 81,
HAL_SRNG_CE_2_DST_STATUS = 82,
HAL_SRNG_CE_3_DST_STATUS = 83,
HAL_SRNG_CE_4_DST_STATUS = 84,
HAL_SRNG_CE_5_DST_STATUS = 85,
HAL_SRNG_CE_6_DST_STATUS = 86,
HAL_SRNG_CE_7_DST_STATUS = 87,
HAL_SRNG_CE_8_DST_STATUS = 88,
HAL_SRNG_CE_9_DST_STATUS = 89,
HAL_SRNG_CE_10_DST_STATUS = 90,
HAL_SRNG_CE_11_DST_STATUS = 91,
/* 92-103 unused */
HAL_SRNG_WBM_IDLE_LINK = 104,
HAL_SRNG_WBM_SW_RELEASE = 105,
HAL_SRNG_WBM2SW0_RELEASE = 106,
HAL_SRNG_WBM2SW1_RELEASE = 107,
HAL_SRNG_WBM2SW2_RELEASE = 108,
HAL_SRNG_WBM2SW3_RELEASE = 109,
HAL_SRNG_WBM2SW4_RELEASE = 110,
HAL_SRNG_WBM2SW5_RELEASE = 111,
HAL_SRNG_WBM2SW6_RELEASE = 112,
/* 113-127 unused */
HAL_SRNG_UMAC_ID_END = 127,
HAL_SRNG_REO2PPE = 10,
/* 11-15 unused */
HAL_SRNG_SW2REO = 16,
HAL_SRNG_SW2REO1 = 17,
HAL_SRNG_SW2REO2 = 18,
HAL_SRNG_SW2REO3 = 19,
HAL_SRNG_REO_CMD = 20,
HAL_SRNG_REO_STATUS = 21,
/* 22-23 unused */
HAL_SRNG_SW2TCL1 = 24,
HAL_SRNG_SW2TCL2 = 25,
HAL_SRNG_SW2TCL3 = 26,
HAL_SRNG_SW2TCL4 = 27,
HAL_SRNG_SW2TCL5 = 28,
HAL_SRNG_SW2TCL6 = 29,
HAL_SRNG_PPE2TCL1 = 30,
/* 31-39 unused */
HAL_SRNG_SW2TCL_CMD = 40,
HAL_SRNG_TCL_STATUS = 41,
HAL_SRNG_SW2TCL_CREDIT = 42,
/* 43-63 unused */
HAL_SRNG_CE_0_SRC = 64,
HAL_SRNG_CE_1_SRC = 65,
HAL_SRNG_CE_2_SRC = 66,
HAL_SRNG_CE_3_SRC = 67,
HAL_SRNG_CE_4_SRC = 68,
HAL_SRNG_CE_5_SRC = 69,
HAL_SRNG_CE_6_SRC = 70,
HAL_SRNG_CE_7_SRC = 71,
HAL_SRNG_CE_8_SRC = 72,
HAL_SRNG_CE_9_SRC = 73,
HAL_SRNG_CE_10_SRC = 74,
HAL_SRNG_CE_11_SRC = 75,
HAL_SRNG_CE_12_SRC = 76,
HAL_SRNG_CE_13_SRC = 77,
HAL_SRNG_CE_14_SRC = 78,
HAL_SRNG_CE_15_SRC = 79,
/* 80 */
HAL_SRNG_CE_0_DST = 81,
HAL_SRNG_CE_1_DST = 82,
HAL_SRNG_CE_2_DST = 83,
HAL_SRNG_CE_3_DST = 84,
HAL_SRNG_CE_4_DST = 85,
HAL_SRNG_CE_5_DST = 86,
HAL_SRNG_CE_6_DST = 87,
HAL_SRNG_CE_7_DST = 89,
HAL_SRNG_CE_8_DST = 90,
HAL_SRNG_CE_9_DST = 91,
HAL_SRNG_CE_10_DST = 92,
HAL_SRNG_CE_11_DST = 93,
HAL_SRNG_CE_12_DST = 94,
HAL_SRNG_CE_13_DST = 95,
HAL_SRNG_CE_14_DST = 96,
HAL_SRNG_CE_15_DST = 97,
/* 98-99 unused */
HAL_SRNG_CE_0_DST_STATUS = 100,
HAL_SRNG_CE_1_DST_STATUS = 101,
HAL_SRNG_CE_2_DST_STATUS = 102,
HAL_SRNG_CE_3_DST_STATUS = 103,
HAL_SRNG_CE_4_DST_STATUS = 104,
HAL_SRNG_CE_5_DST_STATUS = 105,
HAL_SRNG_CE_6_DST_STATUS = 106,
HAL_SRNG_CE_7_DST_STATUS = 107,
HAL_SRNG_CE_8_DST_STATUS = 108,
HAL_SRNG_CE_9_DST_STATUS = 109,
HAL_SRNG_CE_10_DST_STATUS = 110,
HAL_SRNG_CE_11_DST_STATUS = 111,
HAL_SRNG_CE_12_DST_STATUS = 112,
HAL_SRNG_CE_13_DST_STATUS = 113,
HAL_SRNG_CE_14_DST_STATUS = 114,
HAL_SRNG_CE_15_DST_STATUS = 115,
/* 116-119 unused */
HAL_SRNG_WBM_IDLE_LINK = 120,
HAL_SRNG_WBM_SW_RELEASE = 121,
HAL_SRNG_WBM_SW1_RELEASE = 122,
HAL_SRNG_WBM_PPE_RELEASE = 123,
/* 124-127 unused */
HAL_SRNG_WBM2SW0_RELEASE = 128,
HAL_SRNG_WBM2SW1_RELEASE = 129,
HAL_SRNG_WBM2SW2_RELEASE = 130,
HAL_SRNG_WBM2SW3_RELEASE = 131,
HAL_SRNG_WBM2SW4_RELEASE = 132,
HAL_SRNG_WBM2SW5_RELEASE = 133,
HAL_SRNG_WBM2SW6_RELEASE = 134,
HAL_SRNG_WBM_ERROR_RELEASE = 135,
/* 136-158 unused */
HAL_SRNG_UMAC_ID_END = 159,
/* Common DMAC rings shared by all LMACs */
HAL_SRNG_SW2RXDMA_BUF0 = 160,
HAL_SRNG_SW2RXDMA_BUF1 = 161,
HAL_SRNG_SW2RXDMA_BUF2 = 162,
/* 163-167 unused */
HAL_SRNG_SW2RXMON_BUF0 = 168,
/* 169-175 unused */
HAL_SRNG_SW2TXMON_BUF0 = 176,
/* 177-183 unused */
HAL_SRNG_DMAC_CMN_ID_END = 183,
/* LMAC rings - The following set will be replicated for each LMAC */
HAL_SRNG_LMAC1_ID_START = 128,
HAL_SRNG_LMAC1_ID_START = 184,
HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 = HAL_SRNG_LMAC1_ID_START,
#ifdef IPA_OFFLOAD
HAL_SRNG_WMAC1_SW2RXDMA0_BUF1 = (HAL_SRNG_LMAC1_ID_START + 1),
HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 = (HAL_SRNG_LMAC1_ID_START + 2),
HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF2 + 1),
HAL_SRNG_WMAC1_SW2RXDMA0_BUF1,
HAL_SRNG_WMAC1_SW2RXDMA0_BUF2,
HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
#else
HAL_SRNG_WMAC1_SW2RXDMA1_BUF = (HAL_SRNG_WMAC1_SW2RXDMA0_BUF0 + 1),
HAL_SRNG_WMAC1_SW2RXDMA1_BUF,
#endif
HAL_SRNG_WMAC1_SW2RXDMA2_BUF = (HAL_SRNG_WMAC1_SW2RXDMA1_BUF + 1),
HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF = (HAL_SRNG_WMAC1_SW2RXDMA2_BUF + 1),
HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF =
(HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF + 1),
HAL_SRNG_WMAC1_RXDMA2SW0 = (HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF + 1),
HAL_SRNG_WMAC1_RXDMA2SW1 = (HAL_SRNG_WMAC1_RXDMA2SW0 + 1),
HAL_SRNG_WMAC1_SW2RXDMA1_DESC = (HAL_SRNG_WMAC1_RXDMA2SW1 + 1),
HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
HAL_SRNG_WMAC1_SW2RXDMA0_STATBUF,
HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
HAL_SRNG_WMAC1_RXDMA2SW0,
HAL_SRNG_WMAC1_RXDMA2SW1,
HAL_SRNG_WMAC1_RXMON2SW0 = HAL_SRNG_WMAC1_RXDMA2SW1,
HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
#ifdef WLAN_FEATURE_CIF_CFR
HAL_SRNG_WIFI_POS_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WIFI_POS_SRC_DMA_RING + 1),
HAL_SRNG_WIFI_POS_SRC_DMA_RING,
HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
#else
HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING = (HAL_SRNG_WMAC1_SW2RXDMA1_DESC + 1),
HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
#endif
/* -142 unused */
HAL_SRNG_LMAC1_ID_END = 143
HAL_SRNG_WMAC1_TXMON2SW0,
HAL_SRNG_LMAC1_ID_END = (HAL_SRNG_WMAC1_TXMON2SW0 + 3),
};
#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
#define HAL_MAX_LMACS 3
#define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
#define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
#define HAL_SRNG_ID_MAX (HAL_SRNG_DMAC_CMN_ID_END + HAL_MAX_LMAC_RINGS)
/* SRNG type to be passed in APIs hal_srng_get_entrysize and hal_srng_setup */
enum hal_ring_type {
REO_DST = 0,
@@ -269,6 +309,11 @@ enum hal_ring_type {
#ifdef WLAN_FEATURE_CIF_CFR
WIFI_POS_SRC,
#endif
PPE2TCL,
PPE_RELEASE,
TX_MONITOR_BUF,
TX_MONITOR_DST,
SW2RXDMA_NEW,
MAX_RING_TYPES
};
@@ -310,13 +355,6 @@ enum SRNG_REGISTERS {
SRNG_REGISTER_MAX,
};
#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
#define HAL_MAX_LMACS 3
#define HAL_MAX_RINGS_PER_LMAC (HAL_SRNG_LMAC1_ID_END - HAL_SRNG_LMAC1_ID_START)
#define HAL_MAX_LMAC_RINGS (HAL_MAX_LMACS * HAL_MAX_RINGS_PER_LMAC)
#define HAL_SRNG_ID_MAX (HAL_SRNG_UMAC_ID_END + HAL_MAX_LMAC_RINGS)
enum hal_srng_dir {
HAL_SRNG_SRC_RING,
HAL_SRNG_DST_RING
@@ -1127,6 +1165,8 @@ struct hal_soc {
list_shadow_reg_config[MAX_GENERIC_SHADOW_REG];
int num_generic_shadow_regs_configured;
#endif
/* flag to indicate cmn dmac rings in berryllium */
bool dmac_cmn_src_rxbuf_ring;
};
#if defined(FEATURE_HAL_DELAYED_REG_WRITE) || \
@@ -1152,7 +1192,7 @@ void hal_qca6390_attach(struct hal_soc *hal_soc);
void hal_qca6290_attach(struct hal_soc *hal_soc);
void hal_qca8074_attach(struct hal_soc *hal_soc);
void hal_wcn7850_attach(struct hal_soc *hal_soc);
void hal_qcn9224_attach(struct hal_soc *hal_soc);
/*
* hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
* dp_hal_soc handle type