qcacmn: Add support for Genoa register definitions

Add support for Genoa register definitions.

Change-Id: I998549c4c19030cbe835882f356eeda3f776b7a0
CRs-Fixed: 2317215

hif/src/adrastea_reg_def.h

@@ -1809,6 +1809,7 @@
 /* end: Q6 iHelium emulation registers */
 
 #define ADRASTEA_BYPASS_QMI_TEMP_REGISTER    0x00032064
+#define GENOA_OFFSET			     0x800000
 
 struct targetdef_s adrastea_targetdef = {
 	.d_RTC_SOC_BASE_ADDRESS = ADRASTEA_RTC_SOC_BASE_ADDRESS,
@@ -2367,4 +2368,560 @@ struct host_shadow_regs_s adrastea_host_shadow_regs = {
 		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23
 };
 
+struct targetdef_s genoa_targetdef = {
+	.d_RTC_SOC_BASE_ADDRESS = ADRASTEA_RTC_SOC_BASE_ADDRESS,
+	.d_RTC_WMAC_BASE_ADDRESS = ADRASTEA_RTC_WMAC_BASE_ADDRESS,
+	.d_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
+	.d_WLAN_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
+	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
+	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
+	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
+	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
+	.d_CLOCK_CONTROL_OFFSET = ADRASTEA_CLOCK_CONTROL_OFFSET,
+	.d_CLOCK_CONTROL_SI0_CLK_MASK = ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK,
+	.d_RESET_CONTROL_OFFSET = ADRASTEA_SOC_RESET_CONTROL_OFFSET,
+	.d_RESET_CONTROL_MBOX_RST_MASK = ADRASTEA_RESET_CONTROL_MBOX_RST_MASK,
+	.d_RESET_CONTROL_SI0_RST_MASK = ADRASTEA_RESET_CONTROL_SI0_RST_MASK,
+	.d_WLAN_RESET_CONTROL_OFFSET = ADRASTEA_WLAN_RESET_CONTROL_OFFSET,
+	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
+	ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK,
+	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
+	ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK,
+	.d_GPIO_BASE_ADDRESS = ADRASTEA_GPIO_BASE_ADDRESS,
+	.d_GPIO_PIN0_OFFSET = ADRASTEA_GPIO_PIN0_OFFSET,
+	.d_GPIO_PIN1_OFFSET = ADRASTEA_GPIO_PIN1_OFFSET,
+	.d_GPIO_PIN0_CONFIG_MASK = ADRASTEA_GPIO_PIN0_CONFIG_MASK,
+	.d_GPIO_PIN1_CONFIG_MASK = ADRASTEA_GPIO_PIN1_CONFIG_MASK,
+	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB,
+	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK,
+	.d_SI_CONFIG_I2C_LSB = ADRASTEA_SI_CONFIG_I2C_LSB,
+	.d_SI_CONFIG_I2C_MASK = ADRASTEA_SI_CONFIG_I2C_MASK,
+	.d_SI_CONFIG_POS_SAMPLE_LSB = ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB,
+	.d_SI_CONFIG_POS_SAMPLE_MASK = ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK,
+	.d_SI_CONFIG_INACTIVE_CLK_LSB = ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB,
+	.d_SI_CONFIG_INACTIVE_CLK_MASK = ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK,
+	.d_SI_CONFIG_INACTIVE_DATA_LSB = ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB,
+	.d_SI_CONFIG_INACTIVE_DATA_MASK = ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK,
+	.d_SI_CONFIG_DIVIDER_LSB = ADRASTEA_SI_CONFIG_DIVIDER_LSB,
+	.d_SI_CONFIG_DIVIDER_MASK = ADRASTEA_SI_CONFIG_DIVIDER_MASK,
+	.d_SI_BASE_ADDRESS = ADRASTEA_SI_BASE_ADDRESS,
+	.d_SI_CONFIG_OFFSET = ADRASTEA_SI_CONFIG_OFFSET,
+	.d_SI_TX_DATA0_OFFSET = ADRASTEA_SI_TX_DATA0_OFFSET,
+	.d_SI_TX_DATA1_OFFSET = ADRASTEA_SI_TX_DATA1_OFFSET,
+	.d_SI_RX_DATA0_OFFSET = ADRASTEA_SI_RX_DATA0_OFFSET,
+	.d_SI_RX_DATA1_OFFSET = ADRASTEA_SI_RX_DATA1_OFFSET,
+	.d_SI_CS_OFFSET = ADRASTEA_SI_CS_OFFSET,
+	.d_SI_CS_DONE_ERR_MASK = ADRASTEA_SI_CS_DONE_ERR_MASK,
+	.d_SI_CS_DONE_INT_MASK = ADRASTEA_SI_CS_DONE_INT_MASK,
+	.d_SI_CS_START_LSB = ADRASTEA_SI_CS_START_LSB,
+	.d_SI_CS_START_MASK = ADRASTEA_SI_CS_START_MASK,
+	.d_SI_CS_RX_CNT_LSB = ADRASTEA_SI_CS_RX_CNT_LSB,
+	.d_SI_CS_RX_CNT_MASK = ADRASTEA_SI_CS_RX_CNT_MASK,
+	.d_SI_CS_TX_CNT_LSB = ADRASTEA_SI_CS_TX_CNT_LSB,
+	.d_SI_CS_TX_CNT_MASK = ADRASTEA_SI_CS_TX_CNT_MASK,
+	.d_BOARD_DATA_SZ = ADRASTEA_BOARD_DATA_SZ,
+	.d_BOARD_EXT_DATA_SZ = ADRASTEA_BOARD_EXT_DATA_SZ,
+	.d_MBOX_BASE_ADDRESS = ADRASTEA_MBOX_BASE_ADDRESS,
+	.d_LOCAL_SCRATCH_OFFSET = ADRASTEA_LOCAL_SCRATCH_OFFSET,
+	.d_CPU_CLOCK_OFFSET = ADRASTEA_CPU_CLOCK_OFFSET,
+	.d_LPO_CAL_OFFSET = ADRASTEA_LPO_CAL_OFFSET,
+	.d_GPIO_PIN10_OFFSET = ADRASTEA_GPIO_PIN10_OFFSET,
+	.d_GPIO_PIN11_OFFSET = ADRASTEA_GPIO_PIN11_OFFSET,
+	.d_GPIO_PIN12_OFFSET = ADRASTEA_GPIO_PIN12_OFFSET,
+	.d_GPIO_PIN13_OFFSET = ADRASTEA_GPIO_PIN13_OFFSET,
+	.d_CLOCK_GPIO_OFFSET = ADRASTEA_CLOCK_GPIO_OFFSET,
+	.d_CPU_CLOCK_STANDARD_LSB = ADRASTEA_CPU_CLOCK_STANDARD_LSB,
+	.d_CPU_CLOCK_STANDARD_MASK = ADRASTEA_CPU_CLOCK_STANDARD_MASK,
+	.d_LPO_CAL_ENABLE_LSB = ADRASTEA_LPO_CAL_ENABLE_LSB,
+	.d_LPO_CAL_ENABLE_MASK = ADRASTEA_LPO_CAL_ENABLE_MASK,
+	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
+	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
+		ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
+	.d_ANALOG_INTF_BASE_ADDRESS = ADRASTEA_ANALOG_INTF_BASE_ADDRESS,
+	.d_WLAN_MAC_BASE_ADDRESS = ADRASTEA_WLAN_MAC_BASE_ADDRESS,
+	.d_FW_INDICATOR_ADDRESS = ADRASTEA_FW_INDICATOR_ADDRESS,
+	.d_DRAM_BASE_ADDRESS = ADRASTEA_DRAM_BASE_ADDRESS,
+	.d_SOC_CORE_BASE_ADDRESS = ADRASTEA_SOC_CORE_BASE_ADDRESS,
+	.d_CORE_CTRL_ADDRESS = ADRASTEA_CORE_CTRL_ADDRESS,
+	.d_CE_COUNT = ADRASTEA_CE_COUNT,
+	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
+	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
+	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
+	.d_PCIE_INTR_ENABLE_ADDRESS = ADRASTEA_HOST_ENABLE_REGISTER,
+	.d_PCIE_INTR_CLR_ADDRESS = ADRASTEA_HOST_CLEAR_REGISTER,
+	.d_PCIE_INTR_FIRMWARE_MASK = ADRASTEA_PCIE_INTR_FIRMWARE_MASK,
+	.d_PCIE_INTR_CE_MASK_ALL = ADRASTEA_PCIE_INTR_CE_MASK_ALL,
+	.d_CORE_CTRL_CPU_INTR_MASK = ADRASTEA_CORE_CTRL_CPU_INTR_MASK,
+	.d_SR_WR_INDEX_ADDRESS = ADRASTEA_SR_WR_INDEX_OFFSET,
+	.d_DST_WATERMARK_ADDRESS = ADRASTEA_DST_WATERMARK_OFFSET,
+	/* htt_rx.c */
+	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
+	ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK,
+	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB,
+	.d_RX_MPDU_START_0_SEQ_NUM_MASK = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK,
+	.d_RX_MPDU_START_0_SEQ_NUM_LSB = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB,
+	.d_RX_MPDU_START_2_PN_47_32_LSB = ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB,
+	.d_RX_MPDU_START_2_PN_47_32_MASK =
+		ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK,
+	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
+		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
+	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
+		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
+	.d_RX_MSDU_END_4_LAST_MSDU_MASK = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK,
+	.d_RX_MSDU_END_4_LAST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB,
+	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
+		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK,
+	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
+		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB,
+	.d_RX_ATTENTION_0_FRAGMENT_MASK = ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK,
+	.d_RX_ATTENTION_0_FRAGMENT_LSB = ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB,
+	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
+		ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
+	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
+		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
+	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
+		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
+	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
+		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK,
+	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
+		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB,
+	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
+		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
+	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
+		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK,
+	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
+		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB,
+	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
+		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK,
+	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
+		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB,
+	.d_RX_ATTENTION_0_MORE_DATA_MASK =
+		ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK,
+	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
+		ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK,
+	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
+		ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
+
+	/* PLL start */
+	.d_EFUSE_OFFSET = ADRASTEA_EFUSE_OFFSET,
+	.d_EFUSE_XTAL_SEL_MSB = ADRASTEA_EFUSE_XTAL_SEL_MSB,
+	.d_EFUSE_XTAL_SEL_LSB = ADRASTEA_EFUSE_XTAL_SEL_LSB,
+	.d_EFUSE_XTAL_SEL_MASK = ADRASTEA_EFUSE_XTAL_SEL_MASK,
+	.d_BB_PLL_CONFIG_OFFSET = ADRASTEA_BB_PLL_CONFIG_OFFSET,
+	.d_BB_PLL_CONFIG_OUTDIV_MSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB,
+	.d_BB_PLL_CONFIG_OUTDIV_LSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB,
+	.d_BB_PLL_CONFIG_OUTDIV_MASK = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK,
+	.d_BB_PLL_CONFIG_FRAC_MSB = ADRASTEA_BB_PLL_CONFIG_FRAC_MSB,
+	.d_BB_PLL_CONFIG_FRAC_LSB = ADRASTEA_BB_PLL_CONFIG_FRAC_LSB,
+	.d_BB_PLL_CONFIG_FRAC_MASK = ADRASTEA_BB_PLL_CONFIG_FRAC_MASK,
+	.d_WLAN_PLL_SETTLE_TIME_MSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB,
+	.d_WLAN_PLL_SETTLE_TIME_LSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB,
+	.d_WLAN_PLL_SETTLE_TIME_MASK = ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK,
+	.d_WLAN_PLL_SETTLE_OFFSET = ADRASTEA_WLAN_PLL_SETTLE_OFFSET,
+	.d_WLAN_PLL_SETTLE_SW_MASK = ADRASTEA_WLAN_PLL_SETTLE_SW_MASK,
+	.d_WLAN_PLL_SETTLE_RSTMASK = ADRASTEA_WLAN_PLL_SETTLE_RSTMASK,
+	.d_WLAN_PLL_SETTLE_RESET = ADRASTEA_WLAN_PLL_SETTLE_RESET,
+	.d_WLAN_PLL_CONTROL_NOPWD_MSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB,
+	.d_WLAN_PLL_CONTROL_NOPWD_LSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB,
+	.d_WLAN_PLL_CONTROL_NOPWD_MASK = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK,
+	.d_WLAN_PLL_CONTROL_BYPASS_MSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB,
+	.d_WLAN_PLL_CONTROL_BYPASS_LSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB,
+	.d_WLAN_PLL_CONTROL_BYPASS_MASK = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK,
+	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
+		ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET,
+	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB,
+	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB,
+	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
+		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK,
+	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
+		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET,
+	.d_WLAN_PLL_CONTROL_REFDIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB,
+	.d_WLAN_PLL_CONTROL_REFDIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB,
+	.d_WLAN_PLL_CONTROL_REFDIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK,
+	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
+		ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET,
+	.d_WLAN_PLL_CONTROL_DIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB,
+	.d_WLAN_PLL_CONTROL_DIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB,
+	.d_WLAN_PLL_CONTROL_DIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK,
+	.d_WLAN_PLL_CONTROL_DIV_RESET = ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET,
+	.d_WLAN_PLL_CONTROL_OFFSET = ADRASTEA_WLAN_PLL_CONTROL_OFFSET,
+	.d_WLAN_PLL_CONTROL_SW_MASK = ADRASTEA_WLAN_PLL_CONTROL_SW_MASK,
+	.d_WLAN_PLL_CONTROL_RSTMASK = ADRASTEA_WLAN_PLL_CONTROL_RSTMASK,
+	.d_WLAN_PLL_CONTROL_RESET = ADRASTEA_WLAN_PLL_CONTROL_RESET,
+	.d_SOC_CORE_CLK_CTRL_OFFSET = ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET,
+	.d_SOC_CORE_CLK_CTRL_DIV_MSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB,
+	.d_SOC_CORE_CLK_CTRL_DIV_LSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB,
+	.d_SOC_CORE_CLK_CTRL_DIV_MASK = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK,
+	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
+		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
+	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
+		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
+	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
+		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
+	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
+		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
+	.d_RTC_SYNC_STATUS_OFFSET = ADRASTEA_RTC_SYNC_STATUS_OFFSET,
+	.d_SOC_CPU_CLOCK_OFFSET = ADRASTEA_SOC_CPU_CLOCK_OFFSET,
+	.d_SOC_CPU_CLOCK_STANDARD_MSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB,
+	.d_SOC_CPU_CLOCK_STANDARD_LSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB,
+	.d_SOC_CPU_CLOCK_STANDARD_MASK = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK,
+	/* PLL end */
+	.d_SOC_POWER_REG_OFFSET = ADRASTEA_SOC_POWER_REG_OFFSET,
+	.d_PCIE_INTR_CAUSE_ADDRESS = ADRASTEA_HOST_CAUSE_REGISTER,
+	.d_SOC_RESET_CONTROL_ADDRESS = ADRASTEA_SOC_RESET_CONTROL_ADDRESS,
+	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
+		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
+	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
+		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
+	.d_SOC_RESET_CONTROL_CE_RST_MASK =
+		ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK,
+	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
+		ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
+	.d_CPU_INTR_ADDRESS = ADRASTEA_CPU_INTR_ADDRESS,
+	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
+		ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS,
+	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
+		ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
+	/* chip id start */
+	.d_SOC_CHIP_ID_ADDRESS = ADRASTEA_SOC_CHIP_ID_ADDRESS,
+	.d_SOC_CHIP_ID_VERSION_MASK = ADRASTEA_SOC_CHIP_ID_VERSION_MASK,
+	.d_SOC_CHIP_ID_VERSION_LSB = ADRASTEA_SOC_CHIP_ID_VERSION_LSB,
+	.d_SOC_CHIP_ID_REVISION_MASK = ADRASTEA_SOC_CHIP_ID_REVISION_MASK,
+	.d_SOC_CHIP_ID_REVISION_LSB = ADRASTEA_SOC_CHIP_ID_REVISION_LSB,
+	/* chip id end */
+	.d_A_SOC_CORE_SCRATCH_0_ADDRESS = ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS,
+	.d_A_SOC_CORE_SPARE_0_REGISTER = ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER,
+	.d_PCIE_INTR_FIRMWARE_ROUTE_MASK =
+		ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK,
+	.d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 =
+		ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1,
+	.d_A_SOC_CORE_SPARE_1_REGISTER =
+		ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER,
+	.d_A_SOC_CORE_PCIE_INTR_CLR_GRP1 =
+		ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1,
+	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 =
+		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1,
+	.d_A_SOC_PCIE_PCIE_SCRATCH_0 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0,
+	.d_A_SOC_PCIE_PCIE_SCRATCH_1 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1,
+	.d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA =
+		ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA,
+	.d_A_SOC_PCIE_PCIE_SCRATCH_2 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2,
+	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK =
+		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK,
+	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET,
+	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
+	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
+	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
+		ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
+	.d_WLAN_DEBUG_CONTROL_OFFSET = ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET,
+	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
+		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB,
+	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
+		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB,
+	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
+		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK,
+	.d_WLAN_DEBUG_OUT_OFFSET = ADRASTEA_WLAN_DEBUG_OUT_OFFSET,
+	.d_WLAN_DEBUG_OUT_DATA_MSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB,
+	.d_WLAN_DEBUG_OUT_DATA_LSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB,
+	.d_WLAN_DEBUG_OUT_DATA_MASK = ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK,
+	.d_AMBA_DEBUG_BUS_OFFSET = ADRASTEA_AMBA_DEBUG_BUS_OFFSET,
+	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
+		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
+	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
+		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
+	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
+		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
+	.d_AMBA_DEBUG_BUS_SEL_MSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB,
+	.d_AMBA_DEBUG_BUS_SEL_LSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB,
+	.d_AMBA_DEBUG_BUS_SEL_MASK = ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK,
+
+#ifdef QCA_WIFI_3_0_ADRASTEA
+	.d_Q6_ENABLE_REGISTER_0 = ADRASTEA_Q6_ENABLE_REGISTER_0,
+	.d_Q6_ENABLE_REGISTER_1 = ADRASTEA_Q6_ENABLE_REGISTER_1,
+	.d_Q6_CAUSE_REGISTER_0 = ADRASTEA_Q6_CAUSE_REGISTER_0,
+	.d_Q6_CAUSE_REGISTER_1 = ADRASTEA_Q6_CAUSE_REGISTER_1,
+	.d_Q6_CLEAR_REGISTER_0 = ADRASTEA_Q6_CLEAR_REGISTER_0,
+	.d_Q6_CLEAR_REGISTER_1 = ADRASTEA_Q6_CLEAR_REGISTER_1,
+#endif
+
+#ifdef CONFIG_BYPASS_QMI
+	.d_BYPASS_QMI_TEMP_REGISTER = GENOA_OFFSET +
+				      ADRASTEA_BYPASS_QMI_TEMP_REGISTER,
+#endif
+};
+
+struct hostdef_s genoa_hostdef = {
+	.d_INT_STATUS_ENABLE_ERROR_LSB = ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB,
+	.d_INT_STATUS_ENABLE_ERROR_MASK = ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK,
+	.d_INT_STATUS_ENABLE_CPU_LSB = ADRASTEA_INT_STATUS_ENABLE_CPU_LSB,
+	.d_INT_STATUS_ENABLE_CPU_MASK = ADRASTEA_INT_STATUS_ENABLE_CPU_MASK,
+	.d_INT_STATUS_ENABLE_COUNTER_LSB =
+		ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB,
+	.d_INT_STATUS_ENABLE_COUNTER_MASK =
+		ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK,
+	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
+		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB,
+	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
+		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK,
+	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
+		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
+	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
+		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
+	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
+		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
+	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
+		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
+	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
+		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
+	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
+		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
+	.d_INT_STATUS_ENABLE_ADDRESS = ADRASTEA_INT_STATUS_ENABLE_ADDRESS,
+	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
+		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB,
+	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
+		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK,
+	.d_HOST_INT_STATUS_ADDRESS = ADRASTEA_HOST_INT_STATUS_ADDRESS,
+	.d_CPU_INT_STATUS_ADDRESS = ADRASTEA_CPU_INT_STATUS_ADDRESS,
+	.d_ERROR_INT_STATUS_ADDRESS = ADRASTEA_ERROR_INT_STATUS_ADDRESS,
+	.d_ERROR_INT_STATUS_WAKEUP_MASK = ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK,
+	.d_ERROR_INT_STATUS_WAKEUP_LSB = ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB,
+	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
+		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
+	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
+		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
+	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
+		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
+	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
+		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
+	.d_COUNT_DEC_ADDRESS = ADRASTEA_COUNT_DEC_ADDRESS,
+	.d_HOST_INT_STATUS_CPU_MASK = ADRASTEA_HOST_INT_STATUS_CPU_MASK,
+	.d_HOST_INT_STATUS_CPU_LSB = ADRASTEA_HOST_INT_STATUS_CPU_LSB,
+	.d_HOST_INT_STATUS_ERROR_MASK = ADRASTEA_HOST_INT_STATUS_ERROR_MASK,
+	.d_HOST_INT_STATUS_ERROR_LSB = ADRASTEA_HOST_INT_STATUS_ERROR_LSB,
+	.d_HOST_INT_STATUS_COUNTER_MASK = ADRASTEA_HOST_INT_STATUS_COUNTER_MASK,
+	.d_HOST_INT_STATUS_COUNTER_LSB = ADRASTEA_HOST_INT_STATUS_COUNTER_LSB,
+	.d_RX_LOOKAHEAD_VALID_ADDRESS = ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS,
+	.d_WINDOW_DATA_ADDRESS = ADRASTEA_WINDOW_DATA_ADDRESS,
+	.d_WINDOW_READ_ADDR_ADDRESS = ADRASTEA_WINDOW_READ_ADDR_ADDRESS,
+	.d_WINDOW_WRITE_ADDR_ADDRESS = ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS,
+	.d_SOC_GLOBAL_RESET_ADDRESS = ADRASTEA_SOC_GLOBAL_RESET_ADDRESS,
+	.d_RTC_STATE_ADDRESS = ADRASTEA_RTC_STATE_ADDRESS,
+	.d_RTC_STATE_COLD_RESET_MASK = ADRASTEA_RTC_STATE_COLD_RESET_MASK,
+	.d_PCIE_LOCAL_BASE_ADDRESS = ADRASTEA_PCIE_LOCAL_BASE_ADDRESS,
+	.d_PCIE_SOC_WAKE_RESET = ADRASTEA_PCIE_SOC_WAKE_RESET,
+	.d_PCIE_SOC_WAKE_ADDRESS = ADRASTEA_PCIE_SOC_WAKE_ADDRESS,
+	.d_PCIE_SOC_WAKE_V_MASK = ADRASTEA_PCIE_SOC_WAKE_V_MASK,
+	.d_RTC_STATE_V_MASK = ADRASTEA_RTC_STATE_V_MASK,
+	.d_RTC_STATE_V_LSB = ADRASTEA_RTC_STATE_V_LSB,
+	.d_FW_IND_EVENT_PENDING = ADRASTEA_FW_IND_EVENT_PENDING,
+	.d_FW_IND_INITIALIZED = ADRASTEA_FW_IND_INITIALIZED,
+	.d_FW_IND_HELPER = ADRASTEA_FW_IND_HELPER,
+	.d_RTC_STATE_V_ON = ADRASTEA_RTC_STATE_V_ON,
+#if defined(SDIO_3_0)
+	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
+		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_MASK,
+	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
+		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_LSB,
+#endif
+	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
+	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
+	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
+	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
+	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
+	.d_HOST_CE_COUNT = ADRASTEA_CE_COUNT,
+	.d_ENABLE_MSI = 0,
+	.d_MUX_ID_MASK = 0xf000,
+	.d_TRANSACTION_ID_MASK = 0x0fff,
+	.d_DESC_DATA_FLAG_MASK = 0x1FFFE3E0,
+	.d_A_SOC_PCIE_PCIE_BAR0_START = ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START,
+};
+
+struct ce_reg_def genoa_ce_targetdef = {
+	/* copy_engine.c  */
+	.d_DST_WR_INDEX_ADDRESS = ADRASTEA_DST_WR_INDEX_OFFSET,
+	.d_SRC_WATERMARK_ADDRESS = ADRASTEA_SRC_WATERMARK_OFFSET,
+	.d_SRC_WATERMARK_LOW_MASK = ADRASTEA_SRC_WATERMARK_LOW_MASK,
+	.d_SRC_WATERMARK_HIGH_MASK = ADRASTEA_SRC_WATERMARK_HIGH_MASK,
+	.d_DST_WATERMARK_LOW_MASK = ADRASTEA_DST_WATERMARK_LOW_MASK,
+	.d_DST_WATERMARK_HIGH_MASK = ADRASTEA_DST_WATERMARK_HIGH_MASK,
+	.d_CURRENT_SRRI_ADDRESS = ADRASTEA_CURRENT_SRRI_OFFSET,
+	.d_CURRENT_DRRI_ADDRESS = ADRASTEA_CURRENT_DRRI_OFFSET,
+	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
+		ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
+	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
+		ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
+	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
+		ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
+	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
+		ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
+	.d_HOST_IS_ADDRESS = ADRASTEA_HOST_IS_OFFSET,
+	.d_MISC_IS_ADDRESS = ADRASTEA_MISC_IS_OFFSET,
+	.d_HOST_IS_COPY_COMPLETE_MASK = ADRASTEA_HOST_IS_COPY_COMPLETE_MASK,
+	.d_CE_WRAPPER_BASE_ADDRESS = GENOA_OFFSET +
+				     ADRASTEA_CE_WRAPPER_BASE_ADDRESS,
+	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
+		GENOA_OFFSET +
+		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET,
+	.d_CE_DDR_ADDRESS_FOR_RRI_LOW =
+		GENOA_OFFSET + ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW,
+	.d_CE_DDR_ADDRESS_FOR_RRI_HIGH =
+		GENOA_OFFSET + ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH,
+	.d_HOST_IE_ADDRESS = ADRASTEA_HOST_IE_OFFSET,
+	.d_HOST_IE_COPY_COMPLETE_MASK = ADRASTEA_HOST_IE_COPY_COMPLETE_MASK,
+	.d_SR_BA_ADDRESS = ADRASTEA_SR_BA_OFFSET,
+	.d_SR_BA_ADDRESS_HIGH = ADRASTEA_SR_BA_HIGH_OFFSET,
+	.d_SR_SIZE_ADDRESS = ADRASTEA_SR_SIZE_OFFSET,
+	.d_CE_CTRL1_ADDRESS = ADRASTEA_CE_CTRL1_OFFSET,
+	.d_CE_CTRL1_DMAX_LENGTH_MASK = ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK,
+	.d_DR_BA_ADDRESS = ADRASTEA_DR_BA_OFFSET,
+	.d_DR_BA_ADDRESS_HIGH = ADRASTEA_DR_BA_HIGH_OFFSET,
+	.d_DR_SIZE_ADDRESS = ADRASTEA_DR_SIZE_OFFSET,
+	.d_CE_CMD_REGISTER = ADRASTEA_CE_CMD_REGISTER_OFFSET,
+	.d_CE_MSI_ADDRESS = MISSING_FOR_ADRASTEA,
+	.d_CE_MSI_ADDRESS_HIGH = MISSING_FOR_ADRASTEA,
+	.d_CE_MSI_DATA = MISSING_FOR_ADRASTEA,
+	.d_CE_MSI_ENABLE_BIT = MISSING_FOR_ADRASTEA,
+	.d_MISC_IE_ADDRESS = ADRASTEA_MISC_IE_OFFSET,
+	.d_MISC_IS_AXI_ERR_MASK = ADRASTEA_MISC_IS_AXI_ERR_MASK,
+	.d_MISC_IS_DST_ADDR_ERR_MASK = ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK,
+	.d_MISC_IS_SRC_LEN_ERR_MASK = ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK,
+	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK,
+	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
+		ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK,
+	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
+		ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK,
+	.d_SRC_WATERMARK_LOW_LSB = ADRASTEA_SRC_WATERMARK_LOW_LSB,
+	.d_SRC_WATERMARK_HIGH_LSB = ADRASTEA_SRC_WATERMARK_HIGH_LSB,
+	.d_DST_WATERMARK_LOW_LSB = ADRASTEA_DST_WATERMARK_LOW_LSB,
+	.d_DST_WATERMARK_HIGH_LSB = ADRASTEA_DST_WATERMARK_HIGH_LSB,
+	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
+		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
+	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
+		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
+	.d_CE_CTRL1_DMAX_LENGTH_LSB = ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB,
+	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
+		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
+	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
+		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
+	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
+		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
+	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
+		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
+	.d_CE_CTRL1_IDX_UPD_EN_MASK =
+	    ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M,
+	.d_CE_WRAPPER_DEBUG_OFFSET = ADRASTEA_CE_WRAPPER_DEBUG_OFFSET,
+	.d_CE_WRAPPER_DEBUG_SEL_MSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB,
+	.d_CE_WRAPPER_DEBUG_SEL_LSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB,
+	.d_CE_WRAPPER_DEBUG_SEL_MASK = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK,
+	.d_CE_DEBUG_OFFSET = ADRASTEA_CE_DEBUG_OFFSET,
+	.d_CE_DEBUG_SEL_MSB = ADRASTEA_CE_DEBUG_SEL_MSB,
+	.d_CE_DEBUG_SEL_LSB = ADRASTEA_CE_DEBUG_SEL_LSB,
+	.d_CE_DEBUG_SEL_MASK = ADRASTEA_CE_DEBUG_SEL_MASK,
+	.d_CE0_BASE_ADDRESS = GENOA_OFFSET + ADRASTEA_CE0_BASE_ADDRESS,
+	.d_CE1_BASE_ADDRESS = GENOA_OFFSET + ADRASTEA_CE1_BASE_ADDRESS,
+	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES =
+		MISSING_FOR_ADRASTEA,
+	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS =
+		MISSING_FOR_ADRASTEA,
+};
+
+struct host_shadow_regs_s genoa_host_shadow_regs = {
+	.d_A_LOCAL_SHADOW_REG_VALUE_0  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0,
+	.d_A_LOCAL_SHADOW_REG_VALUE_1  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1,
+	.d_A_LOCAL_SHADOW_REG_VALUE_2  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2,
+	.d_A_LOCAL_SHADOW_REG_VALUE_3  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3,
+	.d_A_LOCAL_SHADOW_REG_VALUE_4  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4,
+	.d_A_LOCAL_SHADOW_REG_VALUE_5  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5,
+	.d_A_LOCAL_SHADOW_REG_VALUE_6  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6,
+	.d_A_LOCAL_SHADOW_REG_VALUE_7  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7,
+	.d_A_LOCAL_SHADOW_REG_VALUE_8  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8,
+	.d_A_LOCAL_SHADOW_REG_VALUE_9  =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9,
+	.d_A_LOCAL_SHADOW_REG_VALUE_10 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10,
+	.d_A_LOCAL_SHADOW_REG_VALUE_11 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11,
+	.d_A_LOCAL_SHADOW_REG_VALUE_12 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12,
+	.d_A_LOCAL_SHADOW_REG_VALUE_13 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13,
+	.d_A_LOCAL_SHADOW_REG_VALUE_14 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14,
+	.d_A_LOCAL_SHADOW_REG_VALUE_15 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15,
+	.d_A_LOCAL_SHADOW_REG_VALUE_16 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16,
+	.d_A_LOCAL_SHADOW_REG_VALUE_17 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17,
+	.d_A_LOCAL_SHADOW_REG_VALUE_18 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18,
+	.d_A_LOCAL_SHADOW_REG_VALUE_19 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19,
+	.d_A_LOCAL_SHADOW_REG_VALUE_20 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20,
+	.d_A_LOCAL_SHADOW_REG_VALUE_21 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21,
+	.d_A_LOCAL_SHADOW_REG_VALUE_22 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22,
+	.d_A_LOCAL_SHADOW_REG_VALUE_23 =
+		GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_0  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_1  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_2  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_3  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_4  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_5  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_6  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_7  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_8  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_9  =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_10 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_11 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_12 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_13 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_14 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_15 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_16 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_17 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_18 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_19 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_20 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_21 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_22 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22,
+	.d_A_LOCAL_SHADOW_REG_ADDRESS_23 =
+		 GENOA_OFFSET + ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23
+};
+
 #endif /* ADRASTEA_REG_DEF_H */

hif/src/regtable.c

@@ -44,8 +44,8 @@ void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
 		scn->target_ce_def = &adrastea_ce_targetdef;
 		break;
 	case TARGET_TYPE_QCN7605:
-		scn->targetdef = &adrastea_targetdef;
-		scn->target_ce_def = &adrastea_ce_targetdef;
+		scn->targetdef = &genoa_targetdef;
+		scn->target_ce_def = &genoa_ce_targetdef;
 		break;
 #if defined(AR6002_HEADERS_DEF)
 	case TARGET_TYPE_AR6002:
@@ -144,8 +144,8 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
 		scn->host_shadow_regs = &adrastea_host_shadow_regs;
 		break;
 	case HIF_TYPE_QCN7605:
-		scn->hostdef = &adrastea_hostdef;
-		scn->host_shadow_regs = &adrastea_host_shadow_regs;
+		scn->hostdef = &genoa_hostdef;
+		scn->host_shadow_regs = &genoa_host_shadow_regs;
 		break;
 #if defined(AR6002_HEADERS_DEF)
 	case HIF_TYPE_AR6002: