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ubwcp: remove UBWC-P flush wait

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Found that we don't need a delay when waiting for the UBWC-P flush
to complete.

Removing the delay will improve the performance of the lock and
unlock calls.

Change-Id: I2fad03b6c3185e5c6fd95e7cac252d189c76b5f7
Signed-off-by: Liam Mark <quic_lmark@quicinc.com>
This commit is contained in:
Liam Mark
2023-06-28 09:30:05 -07:00
parent cda03c3582
commit 7c0fc2b70f
1 changed files with 24 additions and 37 deletions
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61
ubwcp/ubwcp_hw.c
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@@ -201,12 +201,33 @@ void ubwcp_hw_enable_range_check(void __iomem *base, u16 index)
} }
EXPORT_SYMBOL(ubwcp_hw_enable_range_check); EXPORT_SYMBOL(ubwcp_hw_enable_range_check);
int ubwcp_hw_flush(void __iomem *base)
{
u32 flush_complete = 0;
u32 count_no_delay = 1000;
u32 count_delay = 2000;
u32 count = count_no_delay + count_delay;
UBWCP_REG_WRITE(base, FLUSH_CONTROL, 0x3);
do {
if (count < count_delay)
udelay(1);
flush_complete = UBWCP_REG_READ(base, FLUSH_STATUS) & 0x1;
if (flush_complete) {
UBWCP_REG_WRITE(base, FLUSH_CONTROL, 0x0);
return 0;
}
} while (count--);
ERR("~~~~~ FLUSH FAILED ~~~~~");
return -1;
}
EXPORT_SYMBOL(ubwcp_hw_flush);
/* Disable range check with flush */ /* Disable range check with flush */
int ubwcp_hw_disable_range_check_with_flush(void __iomem *base, u16 index) int ubwcp_hw_disable_range_check_with_flush(void __iomem *base, u16 index)
{ {
u32 flush_complete = 0;
u32 count = 20;
u32 val; u32 val;
u16 ctrl_reg = index >> 5; u16 ctrl_reg = index >> 5;
@@ -226,19 +247,7 @@ int ubwcp_hw_disable_range_check_with_flush(void __iomem *base, u16 index)
//assert flush //assert flush
UBWCP_REG_WRITE(base, FLUSH_CONTROL, 0x3); UBWCP_REG_WRITE(base, FLUSH_CONTROL, 0x3);
//poll for flush done return ubwcp_hw_flush(base);
do {
flush_complete = UBWCP_REG_READ(base, FLUSH_STATUS) & 0x1;
if (flush_complete) {
//clear flush
UBWCP_REG_WRITE(base, FLUSH_CONTROL, 0x0);
return 0;
}
udelay(100);
} while (count--);
ERR("~~~~~ FLUSH FAILED ~~~~~");
return -1;
} }
EXPORT_SYMBOL(ubwcp_hw_disable_range_check_with_flush); EXPORT_SYMBOL(ubwcp_hw_disable_range_check_with_flush);
@@ -311,28 +320,6 @@ void ubwcp_hw_encoder_config(void __iomem *base)
UBWCP_REG_WRITE(base, ENCODER_CONFIG, 0x7); UBWCP_REG_WRITE(base, ENCODER_CONFIG, 0x7);
} }
int ubwcp_hw_flush(void __iomem *base)
{
u32 flush_complete = 0;
u32 count = 20;
UBWCP_REG_WRITE(base, FLUSH_CONTROL, 0x3);
do {
flush_complete = UBWCP_REG_READ(base, FLUSH_STATUS) & 0x1;
if (flush_complete) {
UBWCP_REG_WRITE(base, FLUSH_CONTROL, 0x0);
return 0;
}
udelay(100);
} while (count--);
ERR("~~~~~ FLUSH FAILED ~~~~~");
return -1;
}
EXPORT_SYMBOL(ubwcp_hw_flush);
void ubwcp_hw_power_vote_status(void __iomem *pwr_ctrl, u8 *vote, u8 *status) void ubwcp_hw_power_vote_status(void __iomem *pwr_ctrl, u8 *vote, u8 *status)
{ {
u32 reg; u32 reg;