Merge 41022800bcc1a029d1633540b7642c93891ef71d on remote branch

Change-Id: I0b533918eae5cd0b7d9eef89f3c18fe212120f8c

cnss2/main.c

@@ -3269,7 +3269,98 @@ int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
 		[CNSS_HOST_CE_HISTORY_MAX] = "hif_ce_history_max",
 		[CNSS_HOST_ONLY_FOR_CRIT_CE] = "hif_ce_only_for_crit",
 		[CNSS_HOST_HIF_EVENT_HISTORY] = "hif_event_history",
-		[CNSS_HOST_HIF_EVENT_HIST_MAX] = "hif_event_hist_max"
+		[CNSS_HOST_HIF_EVENT_HIST_MAX] = "hif_event_hist_max",
+		[CNSS_HOST_DP_WBM_DESC_REL] = "wbm_desc_rel_ring",
+		[CNSS_HOST_DP_WBM_DESC_REL_HANDLE] = "wbm_desc_rel_ring_handle",
+		[CNSS_HOST_DP_TCL_CMD] = "tcl_cmd_ring",
+		[CNSS_HOST_DP_TCL_CMD_HANDLE] = "tcl_cmd_ring_handle",
+		[CNSS_HOST_DP_TCL_STATUS] = "tcl_status_ring",
+		[CNSS_HOST_DP_TCL_STATUS_HANDLE] = "tcl_status_ring_handle",
+		[CNSS_HOST_DP_REO_REINJ] = "reo_reinject_ring",
+		[CNSS_HOST_DP_REO_REINJ_HANDLE] = "reo_reinject_ring_handle",
+		[CNSS_HOST_DP_RX_REL] = "rx_rel_ring",
+		[CNSS_HOST_DP_RX_REL_HANDLE] = "rx_rel_ring_handle",
+		[CNSS_HOST_DP_REO_EXP] = "reo_exception_ring",
+		[CNSS_HOST_DP_REO_EXP_HANDLE] = "reo_exception_ring_handle",
+		[CNSS_HOST_DP_REO_CMD] = "reo_cmd_ring",
+		[CNSS_HOST_DP_REO_CMD_HANDLE] = "reo_cmd_ring_handle",
+		[CNSS_HOST_DP_REO_STATUS] = "reo_status_ring",
+		[CNSS_HOST_DP_REO_STATUS_HANDLE] = "reo_status_ring_handle",
+		[CNSS_HOST_DP_TCL_DATA_0] = "tcl_data_ring_0",
+		[CNSS_HOST_DP_TCL_DATA_0_HANDLE] = "tcl_data_ring_0_handle",
+		[CNSS_HOST_DP_TX_COMP_0] = "tx_comp_ring_0",
+		[CNSS_HOST_DP_TX_COMP_0_HANDLE] = "tx_comp_ring_0_handle",
+		[CNSS_HOST_DP_TCL_DATA_1] = "tcl_data_ring_1",
+		[CNSS_HOST_DP_TCL_DATA_1_HANDLE] = "tcl_data_ring_1_handle",
+		[CNSS_HOST_DP_TX_COMP_1] = "tx_comp_ring_1",
+		[CNSS_HOST_DP_TX_COMP_1_HANDLE] = "tx_comp_ring_1_handle",
+		[CNSS_HOST_DP_TCL_DATA_2] = "tcl_data_ring_2",
+		[CNSS_HOST_DP_TCL_DATA_2_HANDLE] = "tcl_data_ring_2_handle",
+		[CNSS_HOST_DP_TX_COMP_2] = "tx_comp_ring_2",
+		[CNSS_HOST_DP_TX_COMP_2_HANDLE] = "tx_comp_ring_2_handle",
+		[CNSS_HOST_DP_REO_DST_0] = "reo_dest_ring_0",
+		[CNSS_HOST_DP_REO_DST_0_HANDLE] = "reo_dest_ring_0_handle",
+		[CNSS_HOST_DP_REO_DST_1] = "reo_dest_ring_1",
+		[CNSS_HOST_DP_REO_DST_1_HANDLE] = "reo_dest_ring_1_handle",
+		[CNSS_HOST_DP_REO_DST_2] = "reo_dest_ring_2",
+		[CNSS_HOST_DP_REO_DST_2_HANDLE] = "reo_dest_ring_2_handle",
+		[CNSS_HOST_DP_REO_DST_3] = "reo_dest_ring_3",
+		[CNSS_HOST_DP_REO_DST_3_HANDLE] = "reo_dest_ring_3_handle",
+		[CNSS_HOST_DP_REO_DST_4] = "reo_dest_ring_4",
+		[CNSS_HOST_DP_REO_DST_4_HANDLE] = "reo_dest_ring_4_handle",
+		[CNSS_HOST_DP_REO_DST_5] = "reo_dest_ring_5",
+		[CNSS_HOST_DP_REO_DST_5_HANDLE] = "reo_dest_ring_5_handle",
+		[CNSS_HOST_DP_REO_DST_6] = "reo_dest_ring_6",
+		[CNSS_HOST_DP_REO_DST_6_HANDLE] = "reo_dest_ring_6_handle",
+		[CNSS_HOST_DP_REO_DST_7] = "reo_dest_ring_7",
+		[CNSS_HOST_DP_REO_DST_7_HANDLE] = "reo_dest_ring_7_handle",
+		[CNSS_HOST_DP_PDEV_0] = "dp_pdev_0",
+		[CNSS_HOST_DP_WLAN_CFG_CTX] = "wlan_cfg_ctx",
+		[CNSS_HOST_DP_SOC] = "dp_soc",
+		[CNSS_HOST_HAL_RX_FST] = "hal_rx_fst",
+		[CNSS_HOST_DP_FISA] = "dp_fisa",
+		[CNSS_HOST_DP_FISA_HW_FSE_TABLE] = "dp_fisa_hw_fse_table",
+		[CNSS_HOST_DP_FISA_SW_FSE_TABLE] = "dp_fisa_sw_fse_table",
+		[CNSS_HOST_HIF] = "hif",
+		[CNSS_HOST_QDF_NBUF_HIST] = "qdf_nbuf_history",
+		[CNSS_HOST_TCL_WBM_MAP] = "tcl_wbm_map_array",
+		[CNSS_HOST_RX_MAC_BUF_RING_0] = "rx_mac_buf_ring_0",
+		[CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE] = "rx_mac_buf_ring_0_handle",
+		[CNSS_HOST_RX_MAC_BUF_RING_1] = "rx_mac_buf_ring_1",
+		[CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE] = "rx_mac_buf_ring_1_handle",
+		[CNSS_HOST_RX_REFILL_0] = "rx_refill_buf_ring_0",
+		[CNSS_HOST_RX_REFILL_0_HANDLE] = "rx_refill_buf_ring_0_handle",
+		[CNSS_HOST_CE_0] = "ce_0",
+		[CNSS_HOST_CE_0_SRC_RING] = "ce_0_src_ring",
+		[CNSS_HOST_CE_0_SRC_RING_CTX] = "ce_0_src_ring_ctx",
+		[CNSS_HOST_CE_1] = "ce_1",
+		[CNSS_HOST_CE_1_STATUS_RING] = "ce_1_status_ring",
+		[CNSS_HOST_CE_1_STATUS_RING_CTX] = "ce_1_status_ring_ctx",
+		[CNSS_HOST_CE_1_DEST_RING] = "ce_1_dest_ring",
+		[CNSS_HOST_CE_1_DEST_RING_CTX] = "ce_1_dest_ring_ctx",
+		[CNSS_HOST_CE_2] = "ce_2",
+		[CNSS_HOST_CE_2_STATUS_RING] = "ce_2_status_ring",
+		[CNSS_HOST_CE_2_STATUS_RING_CTX] = "ce_2_status_ring_ctx",
+		[CNSS_HOST_CE_2_DEST_RING] = "ce_2_dest_ring",
+		[CNSS_HOST_CE_2_DEST_RING_CTX] = "ce_2_dest_ring_ctx",
+		[CNSS_HOST_CE_3] = "ce_3",
+		[CNSS_HOST_CE_3_SRC_RING] = "ce_3_src_ring",
+		[CNSS_HOST_CE_3_SRC_RING_CTX] = "ce_3_src_ring_ctx",
+		[CNSS_HOST_CE_4] = "ce_4",
+		[CNSS_HOST_CE_4_SRC_RING] = "ce_4_src_ring",
+		[CNSS_HOST_CE_4_SRC_RING_CTX] = "ce_4_src_ring_ctx",
+		[CNSS_HOST_CE_5] = "ce_5",
+		[CNSS_HOST_CE_6] = "ce_6",
+		[CNSS_HOST_CE_7] = "ce_7",
+		[CNSS_HOST_CE_7_STATUS_RING] = "ce_7_status_ring",
+		[CNSS_HOST_CE_7_STATUS_RING_CTX] = "ce_7_status_ring_ctx",
+		[CNSS_HOST_CE_7_DEST_RING] = "ce_7_dest_ring",
+		[CNSS_HOST_CE_7_DEST_RING_CTX] = "ce_7_dest_ring_ctx",
+		[CNSS_HOST_CE_8] = "ce_8",
+		[CNSS_HOST_DP_TCL_DATA_3] = "tcl_data_ring_3",
+		[CNSS_HOST_DP_TCL_DATA_3_HANDLE] = "tcl_data_ring_3_handle",
+		[CNSS_HOST_DP_TX_COMP_3] = "tx_comp_ring_3",
+		[CNSS_HOST_DP_TX_COMP_3_HANDLE] = "tx_comp_ring_3_handle"
 	};
 	int i;
 	int ret = 0;
@@ -3296,6 +3387,14 @@ int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
 
 	INIT_LIST_HEAD(&head);
 	for (i = 0; i < num_entries_loaded; i++) {
+		/* If region name registered by driver is not present in
+		 * wlan_str. type for that entry will not be set, but entry will
+		 * be added. Which will result in entry type being 0. Currently
+		 * entry type 0 is for wlan_logs, which will result in parsing
+		 * issue for wlan_logs as parsing is done based upon type field.
+		 * So initialize type with -1(Invalid) to avoid such issues.
+		 */
+		meta_info.entry[i].type = -1;
 		seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
 		if (!seg) {
 			cnss_pr_err("Failed to alloc seg entry %d\n", i);
@@ -3307,8 +3406,7 @@ int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
 		seg->size = ssr_entry[i].buffer_size;
 
 		for (j = 0; j < CNSS_HOST_DUMP_TYPE_MAX; j++) {
-			if (strncmp(ssr_entry[i].region_name, wlan_str[j],
-				    strlen(wlan_str[j])) == 0) {
+			if (strcmp(ssr_entry[i].region_name, wlan_str[j]) == 0) {
 				meta_info.entry[i].type = j;
 			}
 		}

cnss2/main.h

@@ -279,7 +279,7 @@ enum cnss_fw_dump_type {
 };
 
 struct cnss_dump_entry {
-	u32 type;
+	int type;
 	u32 entry_start;
 	u32 entry_num;
 };

cnss2/niobe_consolidate_defconfig

@@ -0,0 +1,12 @@
+CONFIG_CNSS2=m
+CONFIG_CNSS_OUT_OF_TREE=y
+CONFIG_CNSS2_QMI=y
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_BUS_AUTO_SUSPEND=y
+CONFIG_CNSS2_SSR_DRIVER_DUMP=y
+CONFIG_CNSS_HW_SECURE_DISABLE=y
+CONFIG_CNSS_HW_SECURE_SMEM=y
+CONFIG_CNSS2_SMMU_DB_SUPPORT=y
+CONFIG_CNSS_PLAT_IPC_QMI_SVC=m
+CONFIG_WCNSS_MEM_PRE_ALLOC=m
+CONFIG_CNSS2_DEBUG=y

cnss2/niobe_gki_defconfig

@@ -0,0 +1,11 @@
+CONFIG_CNSS2=m
+CONFIG_CNSS_OUT_OF_TREE=y
+CONFIG_CNSS2_QMI=y
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_BUS_AUTO_SUSPEND=y
+CONFIG_CNSS2_SSR_DRIVER_DUMP=y
+CONFIG_CNSS_HW_SECURE_DISABLE=y
+CONFIG_CNSS_HW_SECURE_SMEM=y
+CONFIG_CNSS2_SMMU_DB_SUPPORT=y
+CONFIG_CNSS_PLAT_IPC_QMI_SVC=m
+CONFIG_WCNSS_MEM_PRE_ALLOC=m

cnss2/pci.c

@@ -82,6 +82,9 @@ static DEFINE_SPINLOCK(time_sync_lock);
 #define WLAON_PWR_CTRL_SHUTDOWN_DELAY_MIN_US	1000
 #define WLAON_PWR_CTRL_SHUTDOWN_DELAY_MAX_US	2000
 
+#define RDDM_LINK_RECOVERY_RETRY		20
+#define RDDM_LINK_RECOVERY_RETRY_DELAY_MS	20
+
 #define FORCE_WAKE_DELAY_MIN_US			4000
 #define FORCE_WAKE_DELAY_MAX_US			6000
 #define FORCE_WAKE_DELAY_TIMEOUT_US		60000
@@ -1492,46 +1495,6 @@ out:
 	return ret;
 }
 
-int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv)
-{
-	int ret;
-
-	switch (pci_priv->device_id) {
-	case QCA6390_DEVICE_ID:
-	case QCA6490_DEVICE_ID:
-	case KIWI_DEVICE_ID:
-	case MANGO_DEVICE_ID:
-	case PEACH_DEVICE_ID:
-		break;
-	default:
-		return -EOPNOTSUPP;
-	}
-
-	/* Always wait here to avoid missing WAKE assert for RDDM
-	 * before link recovery
-	 */
-	msleep(WAKE_EVENT_TIMEOUT);
-
-	ret = cnss_suspend_pci_link(pci_priv);
-	if (ret)
-		cnss_pr_err("Failed to suspend PCI link, err = %d\n", ret);
-
-	ret = cnss_resume_pci_link(pci_priv);
-	if (ret) {
-		cnss_pr_err("Failed to resume PCI link, err = %d\n", ret);
-		del_timer(&pci_priv->dev_rddm_timer);
-		return ret;
-	}
-
-	mod_timer(&pci_priv->dev_rddm_timer,
-		  jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT));
-
-	cnss_mhi_debug_reg_dump(pci_priv);
-	cnss_pci_soc_scratch_reg_dump(pci_priv);
-
-	return 0;
-}
-
 static void cnss_pci_update_link_event(struct cnss_pci_data *pci_priv,
 				       enum cnss_bus_event_type type,
 				       void *data)
@@ -1577,6 +1540,7 @@ void cnss_pci_handle_linkdown(struct cnss_pci_data *pci_priv)
 	cnss_pci_update_link_event(pci_priv, BUS_EVENT_PCI_LINK_DOWN, NULL);
 
 	cnss_fatal_err("PCI link down, schedule recovery\n");
+	reinit_completion(&pci_priv->wake_event_complete);
 	cnss_schedule_recovery(&pci_dev->dev, CNSS_REASON_LINK_DOWN);
 }
 
@@ -2893,6 +2857,7 @@ int cnss_pci_call_driver_remove(struct cnss_pci_data *pci_priv)
 
 	if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
 	    test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state)) {
+		complete(&plat_priv->rddm_complete);
 		pci_priv->driver_ops->shutdown(pci_priv->pci_dev);
 	} else if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state)) {
 		pci_priv->driver_ops->remove(pci_priv->pci_dev);
@@ -5731,6 +5696,70 @@ static void cnss_pci_mhi_reg_dump(struct cnss_pci_data *pci_priv)
 	cnss_pci_dump_shadow_reg(pci_priv);
 }
 
+int cnss_pci_recover_link_down(struct cnss_pci_data *pci_priv)
+{
+	int ret;
+	int retry = 0;
+	enum mhi_ee_type mhi_ee;
+
+	switch (pci_priv->device_id) {
+	case QCA6390_DEVICE_ID:
+	case QCA6490_DEVICE_ID:
+	case KIWI_DEVICE_ID:
+	case MANGO_DEVICE_ID:
+	case PEACH_DEVICE_ID:
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	/* Always wait here to avoid missing WAKE assert for RDDM
+	 * before link recovery
+	 */
+	ret = wait_for_completion_timeout(&pci_priv->wake_event_complete,
+					  msecs_to_jiffies(WAKE_EVENT_TIMEOUT));
+	if (!ret)
+		cnss_pr_err("Timeout waiting for wake event after link down\n");
+
+	ret = cnss_suspend_pci_link(pci_priv);
+	if (ret)
+		cnss_pr_err("Failed to suspend PCI link, err = %d\n", ret);
+
+	ret = cnss_resume_pci_link(pci_priv);
+	if (ret) {
+		cnss_pr_err("Failed to resume PCI link, err = %d\n", ret);
+		del_timer(&pci_priv->dev_rddm_timer);
+		return ret;
+	}
+
+retry:
+	/*
+	 * After PCIe link resumes, 20 to 400 ms delay is observerved
+	 * before device moves to RDDM.
+	 */
+	msleep(RDDM_LINK_RECOVERY_RETRY_DELAY_MS);
+	mhi_ee = mhi_get_exec_env(pci_priv->mhi_ctrl);
+	if (mhi_ee == MHI_EE_RDDM) {
+		del_timer(&pci_priv->dev_rddm_timer);
+		cnss_pr_info("Device in RDDM after link recovery, try to collect dump\n");
+		cnss_schedule_recovery(&pci_priv->pci_dev->dev,
+				       CNSS_REASON_RDDM);
+		return 0;
+	} else if (retry++ < RDDM_LINK_RECOVERY_RETRY) {
+		cnss_pr_dbg("Wait for RDDM after link recovery, retry #%d, Device EE: %d\n",
+			    retry, mhi_ee);
+		goto retry;
+	}
+
+	if (!cnss_pci_assert_host_sol(pci_priv))
+		return 0;
+	cnss_mhi_debug_reg_dump(pci_priv);
+	cnss_pci_soc_scratch_reg_dump(pci_priv);
+	cnss_schedule_recovery(&pci_priv->pci_dev->dev,
+			       CNSS_REASON_TIMEOUT);
+	return 0;
+}
+
 int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv)
 {
 	int ret;
@@ -5793,6 +5822,7 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv)
 		cnss_pci_dump_debug_reg(pci_priv);
 		cnss_schedule_recovery(&pci_priv->pci_dev->dev,
 				       CNSS_REASON_DEFAULT);
+		ret = 0;
 		goto runtime_pm_put;
 	}
 
@@ -5946,12 +5976,18 @@ exit:
 #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP
 void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv)
 {
-	struct cnss_ssr_driver_dump_entry ssr_entry[CNSS_HOST_DUMP_TYPE_MAX] = {0};
+	struct cnss_ssr_driver_dump_entry *ssr_entry;
 	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
 	size_t num_entries_loaded = 0;
 	int x;
 	int ret = -1;
 
+	ssr_entry = kmalloc(sizeof(*ssr_entry) * CNSS_HOST_DUMP_TYPE_MAX, GFP_KERNEL);
+	if (!ssr_entry) {
+		cnss_pr_err("ssr_entry malloc failed");
+		return;
+	}
+
 	if (pci_priv->driver_ops &&
 	    pci_priv->driver_ops->collect_driver_dump) {
 		ret = pci_priv->driver_ops->collect_driver_dump(pci_priv->pci_dev,
@@ -5971,6 +6007,8 @@ void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv)
 	} else {
 		cnss_pr_info("Host SSR elf dump collection feature disabled\n");
 	}
+
+	kfree(ssr_entry);
 }
 #endif
 
@@ -6380,7 +6418,7 @@ static void cnss_dev_rddm_timeout_hdlr(struct timer_list *t)
 
 	mhi_ee = mhi_get_exec_env(pci_priv->mhi_ctrl);
 	if (mhi_ee == MHI_EE_PBL)
-		cnss_pr_err("Unable to collect ramdumps due to abrupt reset\n");
+		cnss_pr_err("Device MHI EE is PBL, unable to collect dump\n");
 
 	if (mhi_ee == MHI_EE_RDDM) {
 		cnss_pr_info("Device MHI EE is RDDM, try to collect dump\n");
@@ -6431,6 +6469,7 @@ static int cnss_pci_handle_mhi_sys_err(struct cnss_pci_data *pci_priv)
 	cnss_ignore_qmi_failure(true);
 	set_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
 	del_timer(&plat_priv->fw_boot_timer);
+	reinit_completion(&pci_priv->wake_event_complete);
 	mod_timer(&pci_priv->dev_rddm_timer,
 		  jiffies + msecs_to_jiffies(DEV_RDDM_TIMEOUT));
 	cnss_pci_update_status(pci_priv, CNSS_FW_DOWN);
@@ -7270,6 +7309,7 @@ static int cnss_pci_probe(struct pci_dev *pci_dev,
 		cnss_pci_get_link_status(pci_priv);
 		cnss_pci_set_wlaon_pwr_ctrl(pci_priv, false, true, false);
 		cnss_pci_wake_gpio_init(pci_priv);
+		init_completion(&pci_priv->wake_event_complete);
 		break;
 	default:
 		cnss_pr_err("Unknown PCI device found: 0x%x\n",

cnss2/pci.h

@@ -169,6 +169,7 @@ struct cnss_pci_data {
 	struct mhi_controller *mhi_ctrl;
 	unsigned long mhi_state;
 	u32 remap_window;
+	struct completion wake_event_complete;
 	struct timer_list dev_rddm_timer;
 	struct timer_list boot_debug_timer;
 	struct delayed_work time_sync_work;

cnss2/pci_qcom.c

@@ -234,12 +234,14 @@ static void cnss_pci_event_cb(struct msm_pcie_notify *notify)
 		cnss_pci_handle_linkdown(pci_priv);
 		break;
 	case MSM_PCIE_EVENT_WAKEUP:
+		cnss_pr_dbg("PCI Wake up event callback\n");
 		if ((cnss_pci_get_monitor_wake_intr(pci_priv) &&
 		     cnss_pci_get_auto_suspended(pci_priv)) ||
 		     dev->power.runtime_status == RPM_SUSPENDING) {
 			cnss_pci_set_monitor_wake_intr(pci_priv, false);
 			cnss_pci_pm_request_resume(pci_priv);
 		}
+		complete(&pci_priv->wake_event_complete);
 		break;
 	case MSM_PCIE_EVENT_DRV_CONNECT:
 		cnss_pr_dbg("DRV subsystem is connected\n");

cnss_genl/niobe_consolidate_defconfig

@@ -0,0 +1,2 @@
+CONFIG_CNSS_GENL=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_genl/niobe_gki_defconfig

@@ -0,0 +1,2 @@
+CONFIG_CNSS_GENL=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_prealloc/niobe_consolidate_defconfig

@@ -0,0 +1,2 @@
+CONFIG_WCNSS_MEM_PRE_ALLOC=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_prealloc/niobe_gki_defconfig

@@ -0,0 +1,2 @@
+CONFIG_WCNSS_MEM_PRE_ALLOC=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_utils/niobe_consolidate_defconfig

@@ -0,0 +1,4 @@
+CONFIG_CNSS_UTILS=m
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_CNSS_PLAT_IPC_QMI_SVC=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_utils/niobe_gki_defconfig

@@ -0,0 +1,4 @@
+CONFIG_CNSS_UTILS=m
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_CNSS_PLAT_IPC_QMI_SVC=m
+CONFIG_CNSS_OUT_OF_TREE=y

icnss2/main.c

@@ -3129,10 +3129,11 @@ static struct icnss_msi_config msi_config_wcn6750 = {
 };
 
 static struct icnss_msi_config msi_config_wcn6450 = {
-	.total_vectors = 10,
-	.total_users = 1,
+	.total_vectors = 14,
+	.total_users = 2,
 	.users = (struct icnss_msi_user[]) {
-		{ .name = "CE", .num_vectors = 10, .base_vector = 0 },
+		{ .name = "CE", .num_vectors = 12, .base_vector = 0 },
+		{ .name = "DP", .num_vectors = 2, .base_vector = 12 },
 	},
 };
 

inc/cnss2.h

@@ -90,30 +90,121 @@ enum cnss_driver_status {
 };
 
 enum cnss_host_dump_type {
-	CNSS_HOST_WLAN_LOGS,
-	CNSS_HOST_HTC_CREDIT,
-	CNSS_HOST_WMI_TX_CMP,
-	CNSS_HOST_WMI_COMMAND_LOG,
-	CNSS_HOST_WMI_EVENT_LOG,
-	CNSS_HOST_WMI_RX_EVENT,
-	CNSS_HOST_HAL_SOC,
-	CNSS_HOST_GWLAN_LOGGING,
-	CNSS_HOST_WMI_DEBUG_LOG_INFO,
-	CNSS_HOST_HTC_CREDIT_IDX,
-	CNSS_HOST_HTC_CREDIT_LEN,
-	CNSS_HOST_WMI_TX_CMP_IDX,
-	CNSS_HOST_WMI_COMMAND_LOG_IDX,
-	CNSS_HOST_WMI_EVENT_LOG_IDX,
-	CNSS_HOST_WMI_RX_EVENT_IDX,
-	CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF,
-	CNSS_HOST_HANG_EVENT_DATA,
-	CNSS_HOST_CE_DESC_HIST,
-	CNSS_HOST_CE_COUNT_MAX,
-	CNSS_HOST_CE_HISTORY_MAX,
-	CNSS_HOST_ONLY_FOR_CRIT_CE,
-	CNSS_HOST_HIF_EVENT_HISTORY,
-	CNSS_HOST_HIF_EVENT_HIST_MAX,
-	CNSS_HOST_DUMP_TYPE_MAX,
+	CNSS_HOST_WLAN_LOGS		 = 0,
+	CNSS_HOST_HTC_CREDIT		 = 1,
+	CNSS_HOST_WMI_TX_CMP		 = 2,
+	CNSS_HOST_WMI_COMMAND_LOG	 = 3,
+	CNSS_HOST_WMI_EVENT_LOG		 = 4,
+	CNSS_HOST_WMI_RX_EVENT		 = 5,
+	CNSS_HOST_HAL_SOC		 = 6,
+	CNSS_HOST_GWLAN_LOGGING		 = 7,
+	CNSS_HOST_WMI_DEBUG_LOG_INFO	 = 8,
+	CNSS_HOST_HTC_CREDIT_IDX	 = 9,
+	CNSS_HOST_HTC_CREDIT_LEN	 = 10,
+	CNSS_HOST_WMI_TX_CMP_IDX	 = 11,
+	CNSS_HOST_WMI_COMMAND_LOG_IDX	 = 12,
+	CNSS_HOST_WMI_EVENT_LOG_IDX	 = 13,
+	CNSS_HOST_WMI_RX_EVENT_IDX	 = 14,
+	CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF = 15,
+	CNSS_HOST_HANG_EVENT_DATA	 = 16,
+	CNSS_HOST_CE_DESC_HIST		 = 17,
+	CNSS_HOST_CE_COUNT_MAX		 = 18,
+	CNSS_HOST_CE_HISTORY_MAX	 = 19,
+	CNSS_HOST_ONLY_FOR_CRIT_CE	 = 20,
+	CNSS_HOST_HIF_EVENT_HISTORY	 = 21,
+	CNSS_HOST_HIF_EVENT_HIST_MAX	 = 22,
+	CNSS_HOST_DP_WBM_DESC_REL	 = 23,
+	CNSS_HOST_DP_WBM_DESC_REL_HANDLE = 24,
+	CNSS_HOST_DP_TCL_CMD		 = 25,
+	CNSS_HOST_DP_TCL_CMD_HANDLE	 = 26,
+	CNSS_HOST_DP_TCL_STATUS		 = 27,
+	CNSS_HOST_DP_TCL_STATUS_HANDLE	 = 28,
+	CNSS_HOST_DP_REO_REINJ		 = 29,
+	CNSS_HOST_DP_REO_REINJ_HANDLE	 = 30,
+	CNSS_HOST_DP_RX_REL		 = 31,
+	CNSS_HOST_DP_RX_REL_HANDLE	 = 32,
+	CNSS_HOST_DP_REO_EXP		 = 33,
+	CNSS_HOST_DP_REO_EXP_HANDLE	 = 34,
+	CNSS_HOST_DP_REO_CMD		 = 35,
+	CNSS_HOST_DP_REO_CMD_HANDLE	 = 36,
+	CNSS_HOST_DP_REO_STATUS		 = 37,
+	CNSS_HOST_DP_REO_STATUS_HANDLE	 = 38,
+	CNSS_HOST_DP_TCL_DATA_0		 = 39,
+	CNSS_HOST_DP_TCL_DATA_0_HANDLE	 = 40,
+	CNSS_HOST_DP_TX_COMP_0		 = 41,
+	CNSS_HOST_DP_TX_COMP_0_HANDLE	 = 42,
+	CNSS_HOST_DP_TCL_DATA_1		 = 43,
+	CNSS_HOST_DP_TCL_DATA_1_HANDLE	 = 44,
+	CNSS_HOST_DP_TX_COMP_1		 = 45,
+	CNSS_HOST_DP_TX_COMP_1_HANDLE	 = 46,
+	CNSS_HOST_DP_TCL_DATA_2		 = 47,
+	CNSS_HOST_DP_TCL_DATA_2_HANDLE	 = 48,
+	CNSS_HOST_DP_TX_COMP_2		 = 49,
+	CNSS_HOST_DP_TX_COMP_2_HANDLE	 = 50,
+	CNSS_HOST_DP_REO_DST_0		 = 51,
+	CNSS_HOST_DP_REO_DST_0_HANDLE	 = 52,
+	CNSS_HOST_DP_REO_DST_1		 = 53,
+	CNSS_HOST_DP_REO_DST_1_HANDLE	 = 54,
+	CNSS_HOST_DP_REO_DST_2		 = 55,
+	CNSS_HOST_DP_REO_DST_2_HANDLE	 = 56,
+	CNSS_HOST_DP_REO_DST_3		 = 57,
+	CNSS_HOST_DP_REO_DST_3_HANDLE	 = 58,
+	CNSS_HOST_DP_REO_DST_4		 = 59,
+	CNSS_HOST_DP_REO_DST_4_HANDLE	 = 60,
+	CNSS_HOST_DP_REO_DST_5		 = 61,
+	CNSS_HOST_DP_REO_DST_5_HANDLE	 = 62,
+	CNSS_HOST_DP_REO_DST_6		 = 63,
+	CNSS_HOST_DP_REO_DST_6_HANDLE	 = 64,
+	CNSS_HOST_DP_REO_DST_7		 = 65,
+	CNSS_HOST_DP_REO_DST_7_HANDLE	 = 66,
+	CNSS_HOST_DP_PDEV_0		 = 67,
+	CNSS_HOST_DP_WLAN_CFG_CTX	 = 68,
+	CNSS_HOST_DP_SOC		 = 69,
+	CNSS_HOST_HAL_RX_FST		 = 70,
+	CNSS_HOST_DP_FISA		 = 71,
+	CNSS_HOST_DP_FISA_HW_FSE_TABLE	 = 72,
+	CNSS_HOST_DP_FISA_SW_FSE_TABLE	 = 73,
+	CNSS_HOST_HIF			 = 74,
+	CNSS_HOST_QDF_NBUF_HIST		 = 75,
+	CNSS_HOST_TCL_WBM_MAP		 = 76,
+	CNSS_HOST_RX_MAC_BUF_RING_0	 = 77,
+	CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE = 78,
+	CNSS_HOST_RX_MAC_BUF_RING_1	 = 79,
+	CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE = 80,
+	CNSS_HOST_RX_REFILL_0		 = 81,
+	CNSS_HOST_RX_REFILL_0_HANDLE	 = 82,
+	CNSS_HOST_CE_0			 = 83,
+	CNSS_HOST_CE_0_SRC_RING		 = 84,
+	CNSS_HOST_CE_0_SRC_RING_CTX	 = 85,
+	CNSS_HOST_CE_1			 = 86,
+	CNSS_HOST_CE_1_STATUS_RING	 = 87,
+	CNSS_HOST_CE_1_STATUS_RING_CTX	 = 88,
+	CNSS_HOST_CE_1_DEST_RING	 = 89,
+	CNSS_HOST_CE_1_DEST_RING_CTX	 = 90,
+	CNSS_HOST_CE_2			 = 91,
+	CNSS_HOST_CE_2_STATUS_RING	 = 92,
+	CNSS_HOST_CE_2_STATUS_RING_CTX	 = 93,
+	CNSS_HOST_CE_2_DEST_RING	 = 94,
+	CNSS_HOST_CE_2_DEST_RING_CTX	 = 95,
+	CNSS_HOST_CE_3			 = 96,
+	CNSS_HOST_CE_3_SRC_RING		 = 97,
+	CNSS_HOST_CE_3_SRC_RING_CTX	 = 98,
+	CNSS_HOST_CE_4			 = 99,
+	CNSS_HOST_CE_4_SRC_RING		 = 100,
+	CNSS_HOST_CE_4_SRC_RING_CTX	 = 101,
+	CNSS_HOST_CE_5			 = 102,
+	CNSS_HOST_CE_6			 = 103,
+	CNSS_HOST_CE_7			 = 104,
+	CNSS_HOST_CE_7_STATUS_RING	 = 105,
+	CNSS_HOST_CE_7_STATUS_RING_CTX	 = 106,
+	CNSS_HOST_CE_7_DEST_RING	 = 107,
+	CNSS_HOST_CE_7_DEST_RING_CTX	 = 108,
+	CNSS_HOST_CE_8			 = 109,
+	CNSS_HOST_DP_TCL_DATA_3		 = 110,
+	CNSS_HOST_DP_TCL_DATA_3_HANDLE	 = 111,
+	CNSS_HOST_DP_TX_COMP_3		 = 112,
+	CNSS_HOST_DP_TX_COMP_3_HANDLE	 = 113,
+	CNSS_HOST_DUMP_TYPE_MAX		 = 114,
 };
 
 enum cnss_bus_event_type {

wlan_platform_modules.bzl

@@ -9,7 +9,7 @@ _default_module_enablement_list = [
     "wlan_firmware_service"
 ]
 
-_cnss2_enabled_target = ["pineapple", "sun"]
+_cnss2_enabled_target = ["niobe", "pineapple", "sun"]
 _icnss2_enabled_target = ["blair", "pineapple"]
 
 def _get_module_list(target, variant):