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Merge "ASoC: Remove glitch during amic record"

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This commit is contained in:
qctecmdr
2020-04-08 21:02:09 -07:00
committed by Gerrit - the friendly Code Review server
parent ee9e37d20a 271dbe101b
commit 79a655928a
2 changed files with 45 additions and 28 deletions
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39
asoc/codecs/bolero/tx-macro.c
View File

@@ -902,13 +902,14 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component,
tx_vol_ctl_reg, 0x20, 0x20);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x00);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
usleep_range(1000, 1010);
if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x00);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
usleep_range(1000, 1010);
}
hpf_cut_off_freq = (
snd_soc_component_read32(component, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -937,15 +938,17 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
&tx_priv->tx_hpf_work[decimator].dwork,
msecs_to_jiffies(hpf_delay));
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x03);
hpf_gate_reg, 0x03, 0x02);
if (!(is_amic_enabled(component, decimator)
< BOLERO_ADC_MAX))
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x00);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
usleep_range(1000, 1010);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x02, 0x00);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x01);
hpf_gate_reg, 0x03, 0x01);
/*
* 6ms delay is required as per HW spec
*/
@@ -1012,9 +1015,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
component, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK,
hpf_cut_off_freq << 5);
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x02, 0x02);
if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x03, 0x02);
else
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x03, 0x03);
/*
* Minimum 1 clk cycle delay is required
* as per HW spec
@@ -1022,7 +1031,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
usleep_range(1000, 1010);
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x02, 0x00);
0x03, 0x01);
}
}
cancel_delayed_work_sync(

34
asoc/codecs/bolero/va-macro.c
View File

@@ -1086,13 +1086,14 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
/* Enable TX CLK */
snd_soc_component_update_bits(component,
tx_vol_ctl_reg, 0x20, 0x20);
snd_soc_component_update_bits(component,
if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x00);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
usleep_range(1000, 1010);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
usleep_range(1000, 1010);
}
hpf_cut_off_freq = (snd_soc_component_read32(
component, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -1111,15 +1112,16 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
va_tx_unmute_delay = unmute_delay;
}
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x03);
hpf_gate_reg, 0x03, 0x02);
if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX))
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x00);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
usleep_range(1000, 1010);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x02, 0x00);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x01);
hpf_gate_reg, 0x03, 0x01);
/*
* 6ms delay is required as per HW spec
*/
@@ -1175,9 +1177,15 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK,
hpf_cut_off_freq << 5);
snd_soc_component_update_bits(component,
if (is_amic_enabled(component, decimator) <
BOLERO_ADC_MAX)
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x02, 0x02);
0x03, 0x02);
else
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x03, 0x03);
/*
* Minimum 1 clk cycle delay is required
* as per HW spec
@@ -1185,7 +1193,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
usleep_range(1000, 1010);
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x02, 0x00);
0x03, 0x01);
}
}
cancel_delayed_work_sync(