Merge "ASoC: Remove glitch during amic record"
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79a655928a
@@ -902,13 +902,14 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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tx_vol_ctl_reg, 0x20, 0x20);
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tx_vol_ctl_reg, 0x20, 0x20);
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if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x01, 0x00);
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hpf_gate_reg, 0x01, 0x00);
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/*
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/*
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* Minimum 1 clk cycle delay is required as per HW spec
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* Minimum 1 clk cycle delay is required as per HW spec
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*/
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*/
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usleep_range(1000, 1010);
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usleep_range(1000, 1010);
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}
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hpf_cut_off_freq = (
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hpf_cut_off_freq = (
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snd_soc_component_read32(component, dec_cfg_reg) &
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snd_soc_component_read32(component, dec_cfg_reg) &
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TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
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TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
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@@ -937,15 +938,17 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
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&tx_priv->tx_hpf_work[decimator].dwork,
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&tx_priv->tx_hpf_work[decimator].dwork,
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msecs_to_jiffies(hpf_delay));
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msecs_to_jiffies(hpf_delay));
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x03, 0x03);
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hpf_gate_reg, 0x03, 0x02);
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if (!(is_amic_enabled(component, decimator)
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< BOLERO_ADC_MAX))
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x03, 0x00);
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/*
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/*
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* Minimum 1 clk cycle delay is required as per HW spec
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* Minimum 1 clk cycle delay is required as per HW spec
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*/
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*/
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usleep_range(1000, 1010);
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usleep_range(1000, 1010);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x02, 0x00);
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hpf_gate_reg, 0x03, 0x01);
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x01, 0x01);
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/*
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/*
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* 6ms delay is required as per HW spec
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* 6ms delay is required as per HW spec
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*/
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*/
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@@ -1012,9 +1015,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
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component, dec_cfg_reg,
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component, dec_cfg_reg,
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TX_HPF_CUT_OFF_FREQ_MASK,
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TX_HPF_CUT_OFF_FREQ_MASK,
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hpf_cut_off_freq << 5);
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hpf_cut_off_freq << 5);
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if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg,
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hpf_gate_reg,
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0x02, 0x02);
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0x03, 0x02);
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else
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snd_soc_component_update_bits(component,
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hpf_gate_reg,
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0x03, 0x03);
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/*
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/*
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* Minimum 1 clk cycle delay is required
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* Minimum 1 clk cycle delay is required
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* as per HW spec
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* as per HW spec
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@@ -1022,7 +1031,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
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usleep_range(1000, 1010);
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usleep_range(1000, 1010);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg,
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hpf_gate_reg,
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0x02, 0x00);
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0x03, 0x01);
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}
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}
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}
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}
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cancel_delayed_work_sync(
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cancel_delayed_work_sync(
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@@ -1086,13 +1086,14 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
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/* Enable TX CLK */
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/* Enable TX CLK */
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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tx_vol_ctl_reg, 0x20, 0x20);
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tx_vol_ctl_reg, 0x20, 0x20);
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if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x01, 0x00);
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hpf_gate_reg, 0x01, 0x00);
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/*
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/*
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* Minimum 1 clk cycle delay is required as per HW spec
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* Minimum 1 clk cycle delay is required as per HW spec
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*/
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*/
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usleep_range(1000, 1010);
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usleep_range(1000, 1010);
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}
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hpf_cut_off_freq = (snd_soc_component_read32(
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hpf_cut_off_freq = (snd_soc_component_read32(
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component, dec_cfg_reg) &
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component, dec_cfg_reg) &
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TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
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TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
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@@ -1111,15 +1112,16 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
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va_tx_unmute_delay = unmute_delay;
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va_tx_unmute_delay = unmute_delay;
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}
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}
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x03, 0x03);
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hpf_gate_reg, 0x03, 0x02);
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if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX))
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x03, 0x00);
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/*
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/*
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* Minimum 1 clk cycle delay is required as per HW spec
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* Minimum 1 clk cycle delay is required as per HW spec
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*/
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*/
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usleep_range(1000, 1010);
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usleep_range(1000, 1010);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x02, 0x00);
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hpf_gate_reg, 0x03, 0x01);
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x01, 0x01);
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/*
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/*
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* 6ms delay is required as per HW spec
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* 6ms delay is required as per HW spec
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*/
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*/
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@@ -1175,9 +1177,15 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
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dec_cfg_reg,
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dec_cfg_reg,
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TX_HPF_CUT_OFF_FREQ_MASK,
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TX_HPF_CUT_OFF_FREQ_MASK,
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hpf_cut_off_freq << 5);
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hpf_cut_off_freq << 5);
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if (is_amic_enabled(component, decimator) <
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BOLERO_ADC_MAX)
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg,
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hpf_gate_reg,
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0x02, 0x02);
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0x03, 0x02);
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else
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snd_soc_component_update_bits(component,
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hpf_gate_reg,
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0x03, 0x03);
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/*
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/*
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* Minimum 1 clk cycle delay is required
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* Minimum 1 clk cycle delay is required
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* as per HW spec
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* as per HW spec
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@@ -1185,7 +1193,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
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usleep_range(1000, 1010);
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usleep_range(1000, 1010);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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hpf_gate_reg,
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hpf_gate_reg,
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0x02, 0x00);
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0x03, 0x01);
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}
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}
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}
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}
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cancel_delayed_work_sync(
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cancel_delayed_work_sync(
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