Merge "ASoC: Remove glitch during amic record"

This commit is contained in:
qctecmdr
2020-04-08 21:02:09 -07:00
committed by Gerrit - the friendly Code Review server
2 changed files with 45 additions and 28 deletions

View File

@@ -902,13 +902,14 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
tx_vol_ctl_reg, 0x20, 0x20); tx_vol_ctl_reg, 0x20, 0x20);
if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x00); hpf_gate_reg, 0x01, 0x00);
/* /*
* Minimum 1 clk cycle delay is required as per HW spec * Minimum 1 clk cycle delay is required as per HW spec
*/ */
usleep_range(1000, 1010); usleep_range(1000, 1010);
}
hpf_cut_off_freq = ( hpf_cut_off_freq = (
snd_soc_component_read32(component, dec_cfg_reg) & snd_soc_component_read32(component, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5; TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -937,15 +938,17 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
&tx_priv->tx_hpf_work[decimator].dwork, &tx_priv->tx_hpf_work[decimator].dwork,
msecs_to_jiffies(hpf_delay)); msecs_to_jiffies(hpf_delay));
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x03); hpf_gate_reg, 0x03, 0x02);
if (!(is_amic_enabled(component, decimator)
< BOLERO_ADC_MAX))
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x00);
/* /*
* Minimum 1 clk cycle delay is required as per HW spec * Minimum 1 clk cycle delay is required as per HW spec
*/ */
usleep_range(1000, 1010); usleep_range(1000, 1010);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, 0x02, 0x00); hpf_gate_reg, 0x03, 0x01);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x01);
/* /*
* 6ms delay is required as per HW spec * 6ms delay is required as per HW spec
*/ */
@@ -1012,9 +1015,15 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
component, dec_cfg_reg, component, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK, TX_HPF_CUT_OFF_FREQ_MASK,
hpf_cut_off_freq << 5); hpf_cut_off_freq << 5);
if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, hpf_gate_reg,
0x02, 0x02); 0x03, 0x02);
else
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x03, 0x03);
/* /*
* Minimum 1 clk cycle delay is required * Minimum 1 clk cycle delay is required
* as per HW spec * as per HW spec
@@ -1022,7 +1031,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
usleep_range(1000, 1010); usleep_range(1000, 1010);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, hpf_gate_reg,
0x02, 0x00); 0x03, 0x01);
} }
} }
cancel_delayed_work_sync( cancel_delayed_work_sync(

View File

@@ -1086,13 +1086,14 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
/* Enable TX CLK */ /* Enable TX CLK */
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
tx_vol_ctl_reg, 0x20, 0x20); tx_vol_ctl_reg, 0x20, 0x20);
if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX)) {
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x00); hpf_gate_reg, 0x01, 0x00);
/* /*
* Minimum 1 clk cycle delay is required as per HW spec * Minimum 1 clk cycle delay is required as per HW spec
*/ */
usleep_range(1000, 1010); usleep_range(1000, 1010);
}
hpf_cut_off_freq = (snd_soc_component_read32( hpf_cut_off_freq = (snd_soc_component_read32(
component, dec_cfg_reg) & component, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5; TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
@@ -1111,15 +1112,16 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
va_tx_unmute_delay = unmute_delay; va_tx_unmute_delay = unmute_delay;
} }
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x03); hpf_gate_reg, 0x03, 0x02);
if (!(is_amic_enabled(component, decimator) < BOLERO_ADC_MAX))
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x03, 0x00);
/* /*
* Minimum 1 clk cycle delay is required as per HW spec * Minimum 1 clk cycle delay is required as per HW spec
*/ */
usleep_range(1000, 1010); usleep_range(1000, 1010);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, 0x02, 0x00); hpf_gate_reg, 0x03, 0x01);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x01);
/* /*
* 6ms delay is required as per HW spec * 6ms delay is required as per HW spec
*/ */
@@ -1175,9 +1177,15 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
dec_cfg_reg, dec_cfg_reg,
TX_HPF_CUT_OFF_FREQ_MASK, TX_HPF_CUT_OFF_FREQ_MASK,
hpf_cut_off_freq << 5); hpf_cut_off_freq << 5);
if (is_amic_enabled(component, decimator) <
BOLERO_ADC_MAX)
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, hpf_gate_reg,
0x02, 0x02); 0x03, 0x02);
else
snd_soc_component_update_bits(component,
hpf_gate_reg,
0x03, 0x03);
/* /*
* Minimum 1 clk cycle delay is required * Minimum 1 clk cycle delay is required
* as per HW spec * as per HW spec
@@ -1185,7 +1193,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w,
usleep_range(1000, 1010); usleep_range(1000, 1010);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
hpf_gate_reg, hpf_gate_reg,
0x02, 0x00); 0x03, 0x01);
} }
} }
cancel_delayed_work_sync( cancel_delayed_work_sync(