qcacld-4.0: Removing HIF/HTC from driver project

Remove HIF/HTC from driver project.
This is moved to host common project

Change-Id: I7dd6d4117a197a474304aa4a28edacbca924b795

core/hif/inc/hif.h

@@ -1,706 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _HIF_H_
-#define _HIF_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* Header files */
-#include "athdefs.h"
-#include "a_types.h"
-#include "osapi_linux.h"
-#include "cdf_status.h"
-#include "cdf_nbuf.h"
-#include "ol_if_athvar.h"
-#include <linux/platform_device.h>
-#ifdef HIF_PCI
-#include <linux/pci.h>
-#endif /* HIF_PCI */
-
-#define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1
-
-typedef struct htc_callbacks HTC_CALLBACKS;
-typedef void __iomem *A_target_id_t;
-
-#define HIF_TYPE_AR6002   2
-#define HIF_TYPE_AR6003   3
-#define HIF_TYPE_AR6004   5
-#define HIF_TYPE_AR9888   6
-#define HIF_TYPE_AR6320   7
-#define HIF_TYPE_AR6320V2 8
-/* For attaching Peregrine 2.0 board host_reg_tbl only */
-#define HIF_TYPE_AR9888V2 8
-#define HIF_TYPE_QCA6180  9
-#define HIF_TYPE_ADRASTEA 10
-
-#define TARGET_TYPE_UNKNOWN   0
-#define TARGET_TYPE_AR6001    1
-#define TARGET_TYPE_AR6002    2
-#define TARGET_TYPE_AR6003    3
-#define TARGET_TYPE_AR6004    5
-#define TARGET_TYPE_AR6006    6
-#define TARGET_TYPE_AR9888    7
-#define TARGET_TYPE_AR6320    8
-#define TARGET_TYPE_AR900B    9
-/* For attach Peregrine 2.0 board target_reg_tbl only */
-#define TARGET_TYPE_AR9888V2  10
-/* For attach Rome1.0 target_reg_tbl only*/
-#define TARGET_TYPE_AR6320V1    11
-/* For Rome2.0/2.1 target_reg_tbl ID*/
-#define TARGET_TYPE_AR6320V2    12
-/* For Rome3.0 target_reg_tbl ID*/
-#define TARGET_TYPE_AR6320V3    13
-/* For Tufello1.0 target_reg_tbl ID*/
-#define TARGET_TYPE_QCA9377V1   14
-/* For QCA6180 target */
-#define TARGET_TYPE_QCA6180     15
-/* For Adrastea target */
-#define TARGET_TYPE_ADRASTEA     16
-
-struct CE_state;
-#ifdef QCA_WIFI_3_0_ADRASTEA
-#define CE_COUNT_MAX 12
-#else
-#define CE_COUNT_MAX 8
-#endif
-
-/* These numbers are selected so that the product is close to current
-   higher limit of packets HIF services at one shot (1000) */
-#define QCA_NAPI_BUDGET    64
-#define QCA_NAPI_DEF_SCALE 16
-/* NOTE: This is to adapt non-NAPI solution to use
-   the same "budget" as NAPI. Will be removed
-   `once decision about NAPI is made */
-#define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE)
-
-/* NOTE: "napi->scale" can be changed,
-   but this does not change the number of buckets */
-#define QCA_NAPI_NUM_BUCKETS (QCA_NAPI_BUDGET / QCA_NAPI_DEF_SCALE)
-struct qca_napi_stat {
-	uint32_t napi_schedules;
-	uint32_t napi_polls;
-	uint32_t napi_completes;
-	uint32_t napi_workdone;
-	uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS];
-};
-
-/**
- * per NAPI instance data structure
- * This data structure holds stuff per NAPI instance.
- * Note that, in the current implementation, though scale is
- * an instance variable, it is set to the same value for all
- * instances.
- */
-struct qca_napi_info {
-	struct napi_struct   napi;    /* one NAPI Instance per CE in phase I */
-	uint8_t              scale;   /* currently same on all instances */
-	uint8_t              id;
-	struct qca_napi_stat stats[NR_CPUS];
-};
-
-/**
- * NAPI data-sructure common to all NAPI instances.
- *
- * A variable of this type will be stored in hif module context.
- */
-
-struct qca_napi_data {
-	/* NOTE: make sure the mutex is inited only at the very beginning
-	   once for the lifetime of the driver. For now, granularity of one
-	   is OK, but we might want to have a better granularity later */
-	struct mutex         mutex;
-	uint32_t             state;
-	uint32_t             ce_map; /* bitmap of created/registered NAPI
-					instances, indexed by pipe_id,
-					not used by clients (clients use an
-					id returned by create) */
-	struct net_device    netdev; /* dummy net_dev */
-	struct qca_napi_info napis[CE_COUNT_MAX];
-};
-
-struct ol_softc {
-	void __iomem *mem;      /* IO mapped memory base address */
-	cdf_dma_addr_t mem_pa;
-	uint32_t soc_version;
-	/*
-	 * handle for code that uses the osdep.h version of OS
-	 * abstraction primitives
-	 */
-	struct _NIC_DEV aps_osdev;
-	enum ath_hal_bus_type bus_type;
-	uint32_t lcr_val;
-	bool pkt_log_init;
-	bool request_irq_done;
-	/*
-	 * handle for code that uses cdf version of OS
-	 * abstraction primitives
-	 */
-	cdf_device_t cdf_dev;
-
-	struct ol_version version;
-
-	/* Packet statistics */
-	struct ol_ath_stats pkt_stats;
-
-	/* A_TARGET_TYPE_* */
-	uint32_t target_type;
-	uint32_t target_fw_version;
-	uint32_t target_version;
-	uint32_t target_revision;
-	uint8_t crm_version_string[64];
-	uint8_t wlan_version_string[64];
-	ol_target_status target_status;
-	bool is_sim;
-	/* calibration data is stored in flash */
-	uint8_t *cal_in_flash;
-	/* virtual address for the calibration data on the flash */
-	void *cal_mem;
-	/* status of target init */
-	WLAN_INIT_STATUS wlan_init_status;
-
-	/* BMI info */
-	/* OS-dependent private info for BMI */
-	void *bmi_ol_priv;
-	bool bmi_done;
-	bool bmi_ua_done;
-	uint8_t *bmi_cmd_buff;
-	dma_addr_t bmi_cmd_da;
-	OS_DMA_MEM_CONTEXT(bmicmd_dmacontext)
-
-	uint8_t *bmi_rsp_buff;
-	dma_addr_t bmi_rsp_da;
-	/* length of last response */
-	uint32_t last_rxlen;
-	OS_DMA_MEM_CONTEXT(bmirsp_dmacontext)
-
-	void *msi_magic;
-	dma_addr_t msi_magic_da;
-	OS_DMA_MEM_CONTEXT(msi_dmacontext)
-
-	/* Handles for Lower Layers : filled in at init time */
-	hif_handle_t hif_hdl;
-#ifdef HIF_PCI
-	struct hif_pci_softc *hif_sc;
-#endif
-
-#ifdef WLAN_FEATURE_FASTPATH
-	int fastpath_mode_on; /* Duplicating this for data path efficiency */
-#endif /* WLAN_FEATURE_FASTPATH */
-
-	/* HTC handles */
-	void *htc_handle;
-
-	bool fEnableBeaconEarlyTermination;
-	uint8_t bcnEarlyTermWakeInterval;
-
-	/* UTF event information */
-	struct {
-		uint8_t *data;
-		uint32_t length;
-		cdf_size_t offset;
-		uint8_t currentSeq;
-		uint8_t expectedSeq;
-	} utf_event_info;
-
-	struct ol_wow_info *scn_wowInfo;
-	/* enable uart/serial prints from target */
-	bool enableuartprint;
-	/* enable fwlog */
-	bool enablefwlog;
-
-	HAL_REG_CAPABILITIES hal_reg_capabilities;
-	struct ol_regdmn *ol_regdmn_handle;
-	uint8_t bcn_mode;
-	uint8_t arp_override;
-	/*
-	 * Includes host side stack level stats +
-	 * radio level athstats
-	 */
-	struct wlan_dbg_stats ath_stats;
-	/* noise_floor */
-	int16_t chan_nf;
-	uint32_t min_tx_power;
-	uint32_t max_tx_power;
-	uint32_t txpowlimit2G;
-	uint32_t txpowlimit5G;
-	uint32_t txpower_scale;
-	uint32_t chan_tx_pwr;
-	uint32_t vdev_count;
-	uint32_t max_bcn_ie_size;
-	cdf_spinlock_t scn_lock;
-	uint8_t vow_extstats;
-	/* if dcs enabled or not */
-	uint8_t scn_dcs;
-	wdi_event_subscribe scn_rx_peer_invalid_subscriber;
-	uint8_t proxy_sta;
-	uint8_t bcn_enabled;
-	/* Dynamic Tx Chainmask Selection enabled/disabled */
-	uint8_t dtcs;
-	/* true if vht ies are set on target */
-	uint32_t set_ht_vht_ies:1;
-	/*CWM enable/disable state */
-	bool scn_cwmenable;
-	uint8_t max_no_of_peers;
-#ifdef CONFIG_CNSS
-	struct cnss_fw_files fw_files;
-#endif
-#if defined(CONFIG_CNSS)
-	void *ramdump_base;
-	unsigned long ramdump_address;
-	unsigned long ramdump_size;
-#endif
-	bool enable_self_recovery;
-#ifdef WLAN_FEATURE_LPSS
-	bool enablelpasssupport;
-#endif
-	bool enable_ramdump_collection;
-	struct targetdef_s *targetdef;
-	struct ce_reg_def *target_ce_def;
-	struct hostdef_s *hostdef;
-	struct host_shadow_regs_s *host_shadow_regs;
-	bool athdiag_procfs_inited;
-	/*
-	 * Guard changes to Target HW state and to software
-	 * structures that track hardware state.
-	 */
-	unsigned int ce_count;  /* Number of Copy Engines supported */
-	struct CE_state *ce_id_to_state[CE_COUNT_MAX];  /* CE id to CE_state */
-#ifdef FEATURE_NAPI
-	struct qca_napi_data napi_data;
-#endif /* FEATURE_NAPI */
-	int htc_endpoint;
-	bool recovery;
-	bool hif_init_done;
-	int linkstate_vote;
-	atomic_t link_suspended;
-	atomic_t wow_done;
-	atomic_t tasklet_from_intr;
-	atomic_t active_tasklet_cnt;
-	bool notice_send;
-#ifdef HIF_PCI
-	cdf_spinlock_t irq_lock;
-	uint32_t ce_irq_summary;
-#endif
-	uint32_t *vaddr_rri_on_ddr;
-};
-
-typedef enum {
-	HIF_DEVICE_POWER_UP,       /* HIF layer should power up interface
-				    * and/or module */
-	HIF_DEVICE_POWER_DOWN,     /* HIF layer should initiate bus-specific
-				    * measures to minimize power */
-	HIF_DEVICE_POWER_CUT       /* HIF layer should initiate bus-specific
-				    * AND/OR platform-specific measures
-				    * to completely power-off the module and
-				    * associated hardware (i.e. cut power
-				    * supplies) */
-} HIF_DEVICE_POWER_CHANGE_TYPE;
-
-/**
- * enum hif_enable_type: what triggered the enabling of hif
- *
- * @HIF_ENABLE_TYPE_PROBE: probe triggered enable
- * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable
- */
-enum hif_enable_type {
-	HIF_ENABLE_TYPE_PROBE,
-	HIF_ENABLE_TYPE_REINIT,
-	HIF_ENABLE_TYPE_MAX
-};
-
-/**
- * enum hif_disable_type: what triggered the disabling of hif
- *
- * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable
- * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered
- *  							 disable
- * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable
- * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable
- */
-enum hif_disable_type {
-	HIF_DISABLE_TYPE_PROBE_ERROR,
-	HIF_DISABLE_TYPE_REINIT_ERROR,
-	HIF_DISABLE_TYPE_REMOVE,
-	HIF_DISABLE_TYPE_SHUTDOWN,
-	HIF_DISABLE_TYPE_MAX
-};
-
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-typedef struct _HID_ACCESS_LOG {
-	uint32_t seqnum;
-	bool is_write;
-	void *addr;
-	uint32_t value;
-} HIF_ACCESS_LOG;
-#endif
-
-#define HIF_MAX_DEVICES                 1
-
-struct htc_callbacks {
-	void *context;		/* context to pass to the dsrhandler
-				 * note : rwCompletionHandler is provided
-				 * the context passed to hif_read_write  */
-	int (*rwCompletionHandler)(void *rwContext, int status);
-	int (*dsrHandler)(void *context);
-};
-
-typedef struct osdrv_callbacks {
-	void *context;          /* context to pass for all callbacks
-				 * except deviceRemovedHandler
-				 * the deviceRemovedHandler is only
-				 * called if the device is claimed */
-	int (*deviceInsertedHandler)(void *context, void *hif_handle);
-	int (*deviceRemovedHandler)(void *claimedContext,
-				    void *hif_handle);
-	int (*deviceSuspendHandler)(void *context);
-	int (*deviceResumeHandler)(void *context);
-	int (*deviceWakeupHandler)(void *context);
-	int (*devicePowerChangeHandler)(void *context,
-					HIF_DEVICE_POWER_CHANGE_TYPE
-					config);
-} OSDRV_CALLBACKS;
-
-/*
- * This API is used to perform any global initialization of the HIF layer
- * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
- *
- */
-int hif_init(OSDRV_CALLBACKS *callbacks);
-
-/* This API detaches the HTC layer from the HIF device */
-void hif_detach_htc(struct ol_softc *scn);
-
-/****************************************************************/
-/* BMI and Diag window abstraction                              */
-/****************************************************************/
-
-#define HIF_BMI_EXCHANGE_NO_TIMEOUT  ((uint32_t)(0))
-
-#define DIAG_TRANSFER_LIMIT 2048U   /* maximum number of bytes that can be
-				     * handled atomically by
-				     * DiagRead/DiagWrite */
-
-/*
- * API to handle HIF-specific BMI message exchanges, this API is synchronous
- * and only allowed to be called from a context that can block (sleep) */
-CDF_STATUS hif_exchange_bmi_msg(struct ol_softc *scn,
-			 uint8_t *pSendMessage,
-			 uint32_t Length,
-			 uint8_t *pResponseMessage,
-			 uint32_t *pResponseLength, uint32_t TimeoutMS);
-
-/*
- * APIs to handle HIF specific diagnostic read accesses. These APIs are
- * synchronous and only allowed to be called from a context that
- * can block (sleep). They are not high performance APIs.
- *
- * hif_diag_read_access reads a 4 Byte aligned/length value from a
- * Target register or memory word.
- *
- * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory.
- */
-CDF_STATUS hif_diag_read_access(struct ol_softc *scn, uint32_t address,
-			 uint32_t *data);
-CDF_STATUS hif_diag_read_mem(struct ol_softc *scn, uint32_t address,
-		      uint8_t *data, int nbytes);
-void hif_dump_target_memory(struct ol_softc *scn, void *ramdump_base,
-			    uint32_t address, uint32_t size);
-/*
- * APIs to handle HIF specific diagnostic write accesses. These APIs are
- * synchronous and only allowed to be called from a context that
- * can block (sleep).
- * They are not high performance APIs.
- *
- * hif_diag_write_access writes a 4 Byte aligned/length value to a
- * Target register or memory word.
- *
- * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory.
- */
-CDF_STATUS hif_diag_write_access(struct ol_softc *scn, uint32_t address,
-			  uint32_t data);
-CDF_STATUS hif_diag_write_mem(struct ol_softc *scn, uint32_t address,
-		       uint8_t *data, int nbytes);
-
-/*
- * Set the FASTPATH_mode_on flag in sc, for use by data path
- */
-#ifdef WLAN_FEATURE_FASTPATH
-void hif_enable_fastpath(struct ol_softc *hif_dev);
-#endif
-
-#if defined(HIF_PCI) && !defined(A_SIMOS_DEVHOST)
-/*
- * This API allows the Host to access Target registers of a given
- * A_target_id_t directly and relatively efficiently over PCIe.
- * This allows the Host to avoid extra overhead associated with
- * sending a message to firmware and waiting for a response message
- * from firmware, as is done on other interconnects.
- *
- * Yet there is some complexity with direct accesses because the
- * Target's power state is not known a priori. The Host must issue
- * special PCIe reads/writes in order to explicitly wake the Target
- * and to verify that it is awake and will remain awake.
- *
- * NB: Host endianness conversion is left for the caller to handle.
- *     These interfaces handle access; not interpretation.
- *
- * Usage:
- *   During initialization, use A_TARGET_ID to obtain an 'target ID'
- *   for use with these interfaces.
- *
- *   Use A_TARGET_READ and A_TARGET_WRITE to access Target space.
- *   These calls must be bracketed by A_TARGET_ACCESS_BEGIN and
- *   A_TARGET_ACCESS_END.  A single BEGIN/END pair is adequate for
- *   multiple READ/WRITE operations.
- *
- *   Use A_TARGET_ACCESS_BEGIN to put the Target in a state in
- *   which it is legal for the Host to directly access it. This
- *   may involve waking the Target from a low power state, which
- *   may take up to 2Ms!
- *
- *   Use A_TARGET_ACCESS_END to tell the Target that as far as
- *   this code path is concerned, it no longer needs to remain
- *   directly accessible.  BEGIN/END is under a reference counter;
- *   multiple code paths may issue BEGIN/END on a single targid.
- *
- *   For added efficiency, the Host may use A_TARGET_ACCESS_LIKELY.
- *   The LIKELY interface works just like A_TARGET_ACCESS_BEGIN,
- *   except that it may return before the Target is actually
- *   available. It's a vague indication that some Target accesses
- *   are expected "soon".  When the LIKELY API is used,
- *   A_TARGET_ACCESS_BEGIN must be used before any access.
- *
- *   There are several uses for the LIKELY/UNLIKELY API:
- *     -If there is some potential time before Target accesses
- *      and we want to get a head start on waking the Target
- *      (e.g. to overlap Target wake with Host-side malloc)
- *     -High-level code knows that it will call low-level
- *      functions that will use BEGIN/END, and we don't want
- *      to allow the Target to sleep until the entire sequence
- *      has completed.
- *
- *   A_TARGET_ACCESS_OK verifies that the Target can be
- *   accessed. In general, this should not be needed, but it
- *   may be useful for debugging or for special uses.
- *
- *   Note that there must be a matching END for each BEGIN
- *       AND   there must be a matching UNLIKELY for each LIKELY!
- *
- *   NB: This API is designed to allow some flexibility in tradeoffs
- *   between Target power utilization and Host efficiency and
- *   system performance.
- */
-
-/*
- * Enable/disable CDC max performance workaround
- * For max-performace set this to 0
- * To allow SoC to enter sleep set this to 1
- */
-#define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
-#endif
-
-#ifdef IPA_OFFLOAD
-void hif_ipa_get_ce_resource(struct ol_softc *scn,
-			     cdf_dma_addr_t *ce_sr_base_paddr,
-			     uint32_t *ce_sr_ring_size,
-			     cdf_dma_addr_t *ce_reg_paddr);
-#else
-/**
- * hif_ipa_get_ce_resource() - get uc resource on hif
- * @scn: bus context
- * @ce_sr_base_paddr: copyengine source ring base physical address
- * @ce_sr_ring_size: copyengine source ring size
- * @ce_reg_paddr: copyengine register physical address
- *
- * IPA micro controller data path offload feature enabled,
- * HIF should release copy engine related resource information to IPA UC
- * IPA UC will access hardware resource with released information
- *
- * Return: None
- */
-static inline void hif_ipa_get_ce_resource(struct ol_softc *scn,
-			     cdf_dma_addr_t *ce_sr_base_paddr,
-			     uint32_t *ce_sr_ring_size,
-			     cdf_dma_addr_t *ce_reg_paddr)
-{
-	return;
-}
-#endif /* IPA_OFFLOAD */
-
-
-void hif_read_phy_mem_base(struct ol_softc *scn,
-	cdf_dma_addr_t *bar_value);
-
-/**
- * @brief List of callbacks - filled in by HTC.
- */
-struct hif_msg_callbacks {
-	void *Context;
-	/**< context meaningful to HTC */
-	CDF_STATUS (*txCompletionHandler)(void *Context, cdf_nbuf_t wbuf,
-					uint32_t transferID,
-					uint32_t toeplitz_hash_result);
-	CDF_STATUS (*rxCompletionHandler)(void *Context, cdf_nbuf_t wbuf,
-					uint8_t pipeID);
-	void (*txResourceAvailHandler)(void *context, uint8_t pipe);
-	void (*fwEventHandler)(void *context, CDF_STATUS status);
-};
-
-#define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \
-	(attr |= (v & 0x01) << 5)
-#define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \
-	(attr |= (v & 0x03) << 6)
-#define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \
-	(attr |= (v & 0x01) << 13)
-#define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \
-	(attr |= (v & 0x01) << 14)
-#define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \
-	(attr |= (v & 0x01) << 15)
-#define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \
-	(attr |= (v & 0x0FFF) << 16)
-#define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \
-	(attr |= (v & 0x01) << 30)
-
-#ifdef HIF_PCI
-typedef struct pci_device_id hif_bus_id;
-#else
-typedef struct device hif_bus_id;
-#endif
-
-void hif_post_init(struct ol_softc *scn, void *hHTC,
-		   struct hif_msg_callbacks *callbacks);
-CDF_STATUS hif_start(struct ol_softc *scn);
-void hif_stop(struct ol_softc *scn);
-void hif_flush_surprise_remove(struct ol_softc *scn);
-void hif_dump(struct ol_softc *scn, uint8_t CmdId, bool start);
-CDF_STATUS hif_send_head(struct ol_softc *scn, uint8_t PipeID,
-				  uint32_t transferID, uint32_t nbytes,
-				  cdf_nbuf_t wbuf, uint32_t data_attr);
-void hif_send_complete_check(struct ol_softc *scn, uint8_t PipeID,
-			     int force);
-void hif_cancel_deferred_target_sleep(struct ol_softc *scn);
-void hif_get_default_pipe(struct ol_softc *scn, uint8_t *ULPipe,
-			  uint8_t *DLPipe);
-int hif_map_service_to_pipe(struct ol_softc *scn, uint16_t svc_id,
-			uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
-			int *dl_is_polled);
-uint16_t hif_get_free_queue_number(struct ol_softc *scn, uint8_t PipeID);
-void *hif_get_targetdef(struct ol_softc *scn);
-void hi_fsuspendwow(struct ol_softc *scn);
-uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset);
-void hif_set_target_sleep(struct ol_softc *scn, bool sleep_ok,
-		     bool wait_for_it);
-int hif_check_fw_reg(struct ol_softc *scn);
-int hif_check_soc_status(struct ol_softc *scn);
-void hif_get_hw_info(void *scn, u32 *version, u32 *revision,
-		     const char **target_name);
-void hif_set_fw_info(void *scn, u32 target_fw_version);
-void hif_disable_isr(void *scn);
-void hif_reset_soc(void *scn);
-void hif_disable_aspm(void);
-void hif_save_htc_htt_config_endpoint(int htc_endpoint);
-CDF_STATUS hif_open(enum ath_hal_bus_type bus_type);
-void hif_close(void *hif_ctx);
-CDF_STATUS hif_enable(void *hif_ctx, struct device *dev, void *bdev,
-	const hif_bus_id *bid, enum ath_hal_bus_type bus_type,
-	enum hif_enable_type type);
-void hif_disable(void *hif_ctx, enum hif_disable_type type);
-void hif_enable_power_gating(void *hif_ctx);
-
-#ifdef FEATURE_RUNTIME_PM
-struct hif_pm_runtime_lock;
-int hif_pm_runtime_get(void *hif_ctx);
-void hif_pm_runtime_get_noresume(void *hif_ctx);
-int hif_pm_runtime_put(void *hif_ctx);
-struct hif_pm_runtime_lock *hif_runtime_lock_init(const char *name);
-void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock);
-int hif_pm_runtime_prevent_suspend(void *ol_sc,
-		struct hif_pm_runtime_lock *lock);
-int hif_pm_runtime_allow_suspend(void *ol_sc,
-		struct hif_pm_runtime_lock *lock);
-int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc,
-		struct hif_pm_runtime_lock *lock, unsigned int delay);
-#else
-struct hif_pm_runtime_lock {
-	const char *name;
-};
-
-static inline void hif_pm_runtime_get_noresume(void *hif_ctx)
-{}
-
-static inline int hif_pm_runtime_get(void *hif_ctx)
-{ return 0; }
-static inline int hif_pm_runtime_put(void *hif_ctx)
-{ return 0; }
-static inline struct hif_pm_runtime_lock *hif_runtime_lock_init(
-		const char *name)
-{ return NULL; }
-static inline void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock)
-{}
-
-static inline int hif_pm_runtime_prevent_suspend(void *ol_sc,
-		struct hif_pm_runtime_lock *lock)
-{ return 0; }
-static inline int hif_pm_runtime_allow_suspend(void *ol_sc,
-		struct hif_pm_runtime_lock *lock)
-{ return 0; }
-static inline int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc,
-		struct hif_pm_runtime_lock *lock, unsigned int delay)
-{ return 0; }
-#endif
-
-void hif_enable_power_management(void *hif_ctx);
-void hif_disable_power_management(void *hif_ctx);
-
-void hif_vote_link_down(void);
-void hif_vote_link_up(void);
-bool hif_can_suspend_link(void);
-
-int hif_bus_resume(void);
-int hif_bus_suspend(void);
-
-#ifdef FEATURE_RUNTIME_PM
-int hif_pre_runtime_suspend(void);
-void hif_pre_runtime_resume(void);
-int hif_runtime_suspend(void);
-int hif_runtime_resume(void);
-void hif_process_runtime_suspend_success(void);
-void hif_process_runtime_suspend_failure(void);
-void hif_process_runtime_resume_success(void);
-#endif
-
-int hif_dump_registers(struct ol_softc *scn);
-int ol_copy_ramdump(struct ol_softc *scn);
-void hif_pktlogmod_exit(void *hif_ctx);
-void hif_crash_shutdown(void *hif_ctx);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _HIF_H_ */

core/hif/inc/hif_napi.h

@@ -1,153 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __HIF_NAPI_H__
-#define __HIF_NAPI_H__
-
-/**
- * DOC: hif_napi.h
- *
- * Interface to HIF implemented functions of NAPI.
- * These are used by hdd_napi.
- */
-
-
-/* CLD headers */
-#include <hif.h> /* struct ol_softc; */
-
-/**
- * common stuff
- * The declarations until #ifdef FEATURE_NAPI below
- * are valid whether or not FEATURE_NAPI has been
- * defined.
- */
-
-/* the following triggers napi_enable/disable as required */
-enum qca_napi_event {
-	NAPI_EVT_INVALID,
-	NAPI_EVT_INI_FILE,
-	NAPI_EVT_CMD_STATE /* ioctl enable/disable commands */
-};
-
-/**
- * Macros to map ids -returned by ...create()- to pipes and vice versa
- */
-#define NAPI_ID2PIPE(i) ((i)-1)
-#define NAPI_PIPE2ID(p) ((p)+1)
-
-
-#ifdef FEATURE_NAPI
-
-/**
- * NAPI HIF API
- *
- * the declarations below only apply to the case
- * where FEATURE_NAPI is defined
- */
-
-int hif_napi_create(struct ol_softc   *hif,
-		    uint8_t            pipe_id,
-		    int (*poll)(struct napi_struct *, int),
-		    int                budget,
-		    int                scale);
-int hif_napi_destroy(struct ol_softc  *hif,
-		     uint8_t           id,
-		     int               force);
-
-struct qca_napi_data *hif_napi_get_all(struct ol_softc   *hif);
-
-int hif_napi_event(struct ol_softc     *hif,
-		   enum  qca_napi_event event,
-		   void                *data);
-
-/* called from the ISR within hif, so, ce is known */
-int hif_napi_enabled(struct ol_softc *hif, int ce);
-
-/* called from hdd (napi_poll), using napi id as a selector */
-void hif_napi_enable_irq(struct ol_softc *hif, int id);
-
-/* called by ce_tasklet.c::ce_irq_handler */
-int hif_napi_schedule(struct ol_softc *scn, int ce_id);
-
-/* called by hdd_napi, which is called by kernel */
-int hif_napi_poll(struct napi_struct *napi, int budget);
-
-#ifdef FEATURE_NAPI_DEBUG
-#define NAPI_DEBUG(fmt, ...)			\
-	cdf_print("wlan: NAPI: %s:%d "fmt, __func__, __LINE__, ##__VA_ARGS__);
-#else
-#define NAPI_DEBUG(fmt, ...) /* NO-OP */
-#endif /* FEATURE NAPI_DEBUG */
-
-#else /* ! defined(FEATURE_NAPI) */
-
-/**
- * Stub API
- *
- * The declarations in this section are valid only
- * when FEATURE_NAPI has *not* been defined.
- */
-
-#define NAPI_DEBUG(fmt, ...) /* NO-OP */
-
-static inline int hif_napi_create(struct ol_softc   *hif,
-				  uint8_t            pipe_id,
-				  int (*poll)(struct napi_struct *, int),
-				  int                budget,
-				  int                scale)
-{ return -EPERM; }
-
-static inline int hif_napi_destroy(struct ol_softc  *hif,
-				   uint8_t           id,
-				   int               force)
-{ return -EPERM; }
-
-static inline struct qca_napi_data *hif_napi_get_all(struct ol_softc   *hif)
-{ return NULL; }
-
-static inline int hif_napi_event(struct ol_softc     *hif,
-				 enum  qca_napi_event event,
-				 void                *data)
-{ return -EPERM; }
-
-/* called from the ISR within hif, so, ce is known */
-static inline int hif_napi_enabled(struct ol_softc *hif, int ce)
-{ return 0; }
-
-/* called from hdd (napi_poll), using napi id as a selector */
-static inline void hif_napi_enable_irq(struct ol_softc *hif, int id)
-{ return; }
-
-static inline int hif_napi_schedule(struct ol_softc *hif, int ce_id)
-{ return 0; }
-
-static inline int hif_napi_poll(struct napi_struct *napi, int budget)
-{ return -EPERM; }
-
-#endif /* FEATURE_NAPI */
-
-#endif /* __HIF_NAPI_H__ */

core/hif/inc/platform_icnss.h

@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _PLATFORM_ICNSS_H_
-#define _PLATFORM_ICNSS_H_
-
-#ifdef HIF_PCI
-#include "icnss_stub.h"
-#else
-#include <soc/qcom/icnss.h>
-#endif
-
-#endif

core/hif/inc/regtable.h

@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _REGTABLE_H_
-#define _REGTABLE_H_
-
-#include "regtable_pcie.h"
-#include "regtable_ce.h"
-#endif

core/hif/inc/regtable_ce.h

@@ -1,260 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _REGTABLE_CE_H_
-#define _REGTABLE_CE_H_
-
-/*
- * @d_DST_WR_INDEX_ADDRESS: Destination ring write index
- *
- * @d_SRC_WATERMARK_ADDRESS: Source ring watermark
- *
- * @d_SRC_WATERMARK_LOW_MASK: Bits indicating low watermark from Source ring
- *			      watermark
- *
- * @d_SRC_WATERMARK_HIGH_MASK: Bits indicating high watermark from Source ring
- *			       watermark
- *
- * @d_DST_WATERMARK_LOW_MASK: Bits indicating low watermark from Destination
- *			      ring watermark
- *
- * @d_DST_WATERMARK_HIGH_MASK: Bits indicating high watermark from Destination
- *			       ring watermark
- *
- * @d_CURRENT_SRRI_ADDRESS: Current source ring read index.The Start Offset
- *			    will be reflected after a CE transfer is completed.
- *
- * @d_CURRENT_DRRI_ADDRESS: Current Destination ring read index. The Start
- *			    Offset will be reflected after a CE transfer
- *			    is completed.
- *
- * @d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK: Source ring high watermark
- *					    Interrupt Status
- *
- * @d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK: Source ring low watermark
- *					   Interrupt Status
- *
- * @d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK: Destination ring high watermark
- *					    Interrupt Status
- *
- * @d_HOST_IS_DST_RING_LOW_WATERMARK_MASK: Source ring low watermark
- *					   Interrupt Status
- *
- * @d_HOST_IS_ADDRESS: Host Interrupt Status Register
- *
- * @d_MISC_IS_ADDRESS: Miscellaneous Interrupt Status Register
- *
- * @d_HOST_IS_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
- *				  status from the Host Interrupt Status
- *				  register
- *
- * @d_CE_WRAPPER_BASE_ADDRESS: Copy Engine Wrapper Base Address
- *
- * @d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS: CE Wrapper summary for interrupts
- *					    to host
- *
- * @d_CE_WRAPPER_INDEX_BASE_LOW: The LSB Base address to which source and
- *				 destination read indices are written
- *
- * @d_CE_WRAPPER_INDEX_BASE_HIGH: The MSB Base address to which source and
- *				  destination read indices are written
- *
- * @d_HOST_IE_ADDRESS: Host Line Interrupt Enable Register
- *
- * @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
- * 				  enable from the IE register
- *
- * @d_SR_BA_ADDRESS: LSB of Source Ring Base Address
- *
- * @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address
- *
- * @d_SR_SIZE_ADDRESS: Source Ring size - number of entries and Start Offset
- *
- * @d_CE_CTRL1_ADDRESS: CE Control register
- *
- * @d_CE_CTRL1_DMAX_LENGTH_MASK: Destination buffer Max Length used for error
- * 				 check
- *
- * @d_DR_BA_ADDRESS: Destination Ring Base Address Low
- *
- * @d_DR_BA_ADDRESS_HIGH: Destination Ring Base Address High
- *
- * @d_DR_SIZE_ADDRESS: Destination Ring size - number of entries Start Offset
- *
- * @d_CE_CMD_REGISTER: Implements commands to all CE Halt Flush
- *
- * @d_CE_MSI_ADDRESS: CE MSI LOW Address register
- *
- * @d_CE_MSI_ADDRESS_HIGH: CE MSI High Address register
- *
- * @d_CE_MSI_DATA: CE MSI Data Register
- *
- * @d_CE_MSI_ENABLE_BIT: Bit in CTRL1 register indication the MSI enable
- *
- * @d_MISC_IE_ADDRESS: Miscellaneous Interrupt Enable Register
- *
- * @d_MISC_IS_AXI_ERR_MASK: Bit in Misc IS indicating AXI Timeout Interrupt
- *			    status
- *
- * @d_MISC_IS_DST_ADDR_ERR_MASK: Bit in Misc IS indicating Destination Address
- * 				 Error
- *
- * @d_MISC_IS_SRC_LEN_ERR_MASK: Bit in Misc IS indicating Source Zero Length
- * 				Error Interrupt status
- *
- * @d_MISC_IS_DST_MAX_LEN_VIO_MASK: Bit in Misc IS indicating Destination Max
- *				    Length Violated Interrupt status
- *
- * @d_MISC_IS_DST_RING_OVERFLOW_MASK: Bit in Misc IS indicating Destination
- * 				      Ring Overflow Interrupt status
- *
- * @d_MISC_IS_SRC_RING_OVERFLOW_MASK: Bit in Misc IS indicating Source Ring
- * 				      Overflow Interrupt status
- *
- * @d_SRC_WATERMARK_LOW_LSB: Source Ring Low Watermark LSB
- *
- * @d_SRC_WATERMARK_HIGH_LSB: Source Ring Low Watermark MSB
- *
- * @d_DST_WATERMARK_LOW_LSB: Destination Ring Low Watermark LSB
- *
- * @d_DST_WATERMARK_HIGH_LSB: Destination Ring High Watermark LSB
- *
- *
- * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK: Bits in
- * 						  d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
- * 						  indicating Copy engine
- * 						  miscellaneous interrupt summary
- *
- * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB:Bits in
- * 						d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
- * 						indicating Host interrupts summary
- *
- * @d_CE_CTRL1_DMAX_LENGTH_LSB: LSB of Destination buffer Max Length used for
- *				error check
- *
- * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK: Bits indicating Source ring Byte Swap
- * 					   enable. Treats source ring memory
- * 					   organisation as big-endian
- *
- * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK: Bits indicating Destination ring
- * 					   byte swap enable. Treats destination
- * 					   ring memory organisation as big-endian
- *
- * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB: LSB of Source ring Byte Swap enable
- *
- * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB: LSB of Destination ring Byte Swap enable
- *
- * @d_CE_WRAPPER_DEBUG_OFFSET: Offset of CE OBS BUS Select register
- *
- * @d_CE_WRAPPER_DEBUG_SEL_MSB: MSB of Control register selecting inputs for
- *				trace/debug
- *
- * @d_CE_WRAPPER_DEBUG_SEL_LSB: LSB of Control register selecting inputs for
- * 				trace/debug
- *
- * @d_CE_WRAPPER_DEBUG_SEL_MASK: Bits indicating Control register selecting
- * 				 inputs for trace/debug
- *
- * @d_CE_DEBUG_OFFSET: Offset of Copy Engine FSM Debug Status
- *
- * @d_CE_DEBUG_SEL_MSB: MSB of Copy Engine FSM Debug Status
- *
- * @d_CE_DEBUG_SEL_LSB: LSB of Copy Engine FSM Debug Status
- *
- * @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status
- *
-*/
-
-struct ce_reg_def {
-	/* copy_engine.c */
-	uint32_t d_DST_WR_INDEX_ADDRESS;
-	uint32_t d_SRC_WATERMARK_ADDRESS;
-	uint32_t d_SRC_WATERMARK_LOW_MASK;
-	uint32_t d_SRC_WATERMARK_HIGH_MASK;
-	uint32_t d_DST_WATERMARK_LOW_MASK;
-	uint32_t d_DST_WATERMARK_HIGH_MASK;
-	uint32_t d_CURRENT_SRRI_ADDRESS;
-	uint32_t d_CURRENT_DRRI_ADDRESS;
-	uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK;
-	uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK;
-	uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK;
-	uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK;
-	uint32_t d_HOST_IS_ADDRESS;
-	uint32_t d_MISC_IS_ADDRESS;
-	uint32_t d_HOST_IS_COPY_COMPLETE_MASK;
-	uint32_t d_CE_WRAPPER_BASE_ADDRESS;
-	uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
-	uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW;
-	uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH;
-	uint32_t d_HOST_IE_ADDRESS;
-	uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
-	uint32_t d_SR_BA_ADDRESS;
-	uint32_t d_SR_BA_ADDRESS_HIGH;
-	uint32_t d_SR_SIZE_ADDRESS;
-	uint32_t d_CE_CTRL1_ADDRESS;
-	uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK;
-	uint32_t d_DR_BA_ADDRESS;
-	uint32_t d_DR_BA_ADDRESS_HIGH;
-	uint32_t d_DR_SIZE_ADDRESS;
-	uint32_t d_CE_CMD_REGISTER;
-	uint32_t d_CE_MSI_ADDRESS;
-	uint32_t d_CE_MSI_ADDRESS_HIGH;
-	uint32_t d_CE_MSI_DATA;
-	uint32_t d_CE_MSI_ENABLE_BIT;
-	uint32_t d_MISC_IE_ADDRESS;
-	uint32_t d_MISC_IS_AXI_ERR_MASK;
-	uint32_t d_MISC_IS_DST_ADDR_ERR_MASK;
-	uint32_t d_MISC_IS_SRC_LEN_ERR_MASK;
-	uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK;
-	uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK;
-	uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK;
-	uint32_t d_SRC_WATERMARK_LOW_LSB;
-	uint32_t d_SRC_WATERMARK_HIGH_LSB;
-	uint32_t d_DST_WATERMARK_LOW_LSB;
-	uint32_t d_DST_WATERMARK_HIGH_LSB;
-	uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK;
-	uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB;
-	uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB;
-	uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK;
-	uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
-	uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
-	uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
-	uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK;
-	uint32_t d_CE_WRAPPER_DEBUG_OFFSET;
-	uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
-	uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB;
-	uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK;
-	uint32_t d_CE_DEBUG_OFFSET;
-	uint32_t d_CE_DEBUG_SEL_MSB;
-	uint32_t d_CE_DEBUG_SEL_LSB;
-	uint32_t d_CE_DEBUG_SEL_MASK;
-	uint32_t d_CE0_BASE_ADDRESS;
-	uint32_t d_CE1_BASE_ADDRESS;
-	uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES;
-	uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS;
-};
-#endif /* _REGTABLE_CE_H_ */

core/hif/inc/regtable_pcie.h

@@ -1,1030 +0,0 @@
-/*
- * Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _REGTABLE_PCIE_H_
-#define _REGTABLE_PCIE_H_
-
-#define MISSING  0
-
-struct targetdef_s {
-	uint32_t d_RTC_SOC_BASE_ADDRESS;
-	uint32_t d_RTC_WMAC_BASE_ADDRESS;
-	uint32_t d_SYSTEM_SLEEP_OFFSET;
-	uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET;
-	uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
-	uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
-	uint32_t d_CLOCK_CONTROL_OFFSET;
-	uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK;
-	uint32_t d_RESET_CONTROL_OFFSET;
-	uint32_t d_RESET_CONTROL_MBOX_RST_MASK;
-	uint32_t d_RESET_CONTROL_SI0_RST_MASK;
-	uint32_t d_WLAN_RESET_CONTROL_OFFSET;
-	uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK;
-	uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK;
-	uint32_t d_GPIO_BASE_ADDRESS;
-	uint32_t d_GPIO_PIN0_OFFSET;
-	uint32_t d_GPIO_PIN1_OFFSET;
-	uint32_t d_GPIO_PIN0_CONFIG_MASK;
-	uint32_t d_GPIO_PIN1_CONFIG_MASK;
-	uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB;
-	uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK;
-	uint32_t d_SI_CONFIG_I2C_LSB;
-	uint32_t d_SI_CONFIG_I2C_MASK;
-	uint32_t d_SI_CONFIG_POS_SAMPLE_LSB;
-	uint32_t d_SI_CONFIG_POS_SAMPLE_MASK;
-	uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB;
-	uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK;
-	uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB;
-	uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK;
-	uint32_t d_SI_CONFIG_DIVIDER_LSB;
-	uint32_t d_SI_CONFIG_DIVIDER_MASK;
-	uint32_t d_SI_BASE_ADDRESS;
-	uint32_t d_SI_CONFIG_OFFSET;
-	uint32_t d_SI_TX_DATA0_OFFSET;
-	uint32_t d_SI_TX_DATA1_OFFSET;
-	uint32_t d_SI_RX_DATA0_OFFSET;
-	uint32_t d_SI_RX_DATA1_OFFSET;
-	uint32_t d_SI_CS_OFFSET;
-	uint32_t d_SI_CS_DONE_ERR_MASK;
-	uint32_t d_SI_CS_DONE_INT_MASK;
-	uint32_t d_SI_CS_START_LSB;
-	uint32_t d_SI_CS_START_MASK;
-	uint32_t d_SI_CS_RX_CNT_LSB;
-	uint32_t d_SI_CS_RX_CNT_MASK;
-	uint32_t d_SI_CS_TX_CNT_LSB;
-	uint32_t d_SI_CS_TX_CNT_MASK;
-	uint32_t d_BOARD_DATA_SZ;
-	uint32_t d_BOARD_EXT_DATA_SZ;
-	uint32_t d_MBOX_BASE_ADDRESS;
-	uint32_t d_LOCAL_SCRATCH_OFFSET;
-	uint32_t d_CPU_CLOCK_OFFSET;
-	uint32_t d_LPO_CAL_OFFSET;
-	uint32_t d_GPIO_PIN10_OFFSET;
-	uint32_t d_GPIO_PIN11_OFFSET;
-	uint32_t d_GPIO_PIN12_OFFSET;
-	uint32_t d_GPIO_PIN13_OFFSET;
-	uint32_t d_CLOCK_GPIO_OFFSET;
-	uint32_t d_CPU_CLOCK_STANDARD_LSB;
-	uint32_t d_CPU_CLOCK_STANDARD_MASK;
-	uint32_t d_LPO_CAL_ENABLE_LSB;
-	uint32_t d_LPO_CAL_ENABLE_MASK;
-	uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
-	uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
-	uint32_t d_ANALOG_INTF_BASE_ADDRESS;
-	uint32_t d_WLAN_MAC_BASE_ADDRESS;
-	uint32_t d_FW_INDICATOR_ADDRESS;
-	uint32_t d_DRAM_BASE_ADDRESS;
-	uint32_t d_SOC_CORE_BASE_ADDRESS;
-	uint32_t d_CORE_CTRL_ADDRESS;
-	uint32_t d_CE_COUNT;
-	uint32_t d_MSI_NUM_REQUEST;
-	uint32_t d_MSI_ASSIGN_FW;
-	uint32_t d_MSI_ASSIGN_CE_INITIAL;
-	uint32_t d_PCIE_INTR_ENABLE_ADDRESS;
-	uint32_t d_PCIE_INTR_CLR_ADDRESS;
-	uint32_t d_PCIE_INTR_FIRMWARE_MASK;
-	uint32_t d_PCIE_INTR_CE_MASK_ALL;
-	uint32_t d_CORE_CTRL_CPU_INTR_MASK;
-	uint32_t d_SR_WR_INDEX_ADDRESS;
-	uint32_t d_DST_WATERMARK_ADDRESS;
-
-	/* htt_rx.c */
-	uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
-	uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
-	uint32_t d_RX_MPDU_START_0_RETRY_LSB;
-	uint32_t d_RX_MPDU_START_0_RETRY_MASK;
-	uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK;
-	uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB;
-	uint32_t d_RX_MPDU_START_2_PN_47_32_LSB;
-	uint32_t d_RX_MPDU_START_2_PN_47_32_MASK;
-	uint32_t d_RX_MPDU_START_2_TID_LSB;
-	uint32_t d_RX_MPDU_START_2_TID_MASK;
-	uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK;
-	uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB;
-	uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK;
-	uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB;
-	uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK;
-	uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB;
-	uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK;
-	uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB;
-	uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK;
-	uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB;
-	uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK;
-	uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK;
-	uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB;
-	uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK;
-	uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB;
-	uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET;
-	uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK;
-	uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB;
-	uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK;
-	uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB;
-	uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK;
-	uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK;
-	uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK;
-	/* end */
-
-	/* PLL start */
-	uint32_t d_EFUSE_OFFSET;
-	uint32_t d_EFUSE_XTAL_SEL_MSB;
-	uint32_t d_EFUSE_XTAL_SEL_LSB;
-	uint32_t d_EFUSE_XTAL_SEL_MASK;
-	uint32_t d_BB_PLL_CONFIG_OFFSET;
-	uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB;
-	uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB;
-	uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK;
-	uint32_t d_BB_PLL_CONFIG_FRAC_MSB;
-	uint32_t d_BB_PLL_CONFIG_FRAC_LSB;
-	uint32_t d_BB_PLL_CONFIG_FRAC_MASK;
-	uint32_t d_WLAN_PLL_SETTLE_TIME_MSB;
-	uint32_t d_WLAN_PLL_SETTLE_TIME_LSB;
-	uint32_t d_WLAN_PLL_SETTLE_TIME_MASK;
-	uint32_t d_WLAN_PLL_SETTLE_OFFSET;
-	uint32_t d_WLAN_PLL_SETTLE_SW_MASK;
-	uint32_t d_WLAN_PLL_SETTLE_RSTMASK;
-	uint32_t d_WLAN_PLL_SETTLE_RESET;
-	uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB;
-	uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB;
-	uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK;
-	uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB;
-	uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB;
-	uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK;
-	uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET;
-	uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB;
-	uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB;
-	uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK;
-	uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET;
-	uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB;
-	uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB;
-	uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK;
-	uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET;
-	uint32_t d_WLAN_PLL_CONTROL_DIV_MSB;
-	uint32_t d_WLAN_PLL_CONTROL_DIV_LSB;
-	uint32_t d_WLAN_PLL_CONTROL_DIV_MASK;
-	uint32_t d_WLAN_PLL_CONTROL_DIV_RESET;
-	uint32_t d_WLAN_PLL_CONTROL_OFFSET;
-	uint32_t d_WLAN_PLL_CONTROL_SW_MASK;
-	uint32_t d_WLAN_PLL_CONTROL_RSTMASK;
-	uint32_t d_WLAN_PLL_CONTROL_RESET;
-	uint32_t d_SOC_CORE_CLK_CTRL_OFFSET;
-	uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB;
-	uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB;
-	uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK;
-	uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB;
-	uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB;
-	uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK;
-	uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET;
-	uint32_t d_RTC_SYNC_STATUS_OFFSET;
-	uint32_t d_SOC_CPU_CLOCK_OFFSET;
-	uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB;
-	uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB;
-	uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK;
-	/* PLL end */
-
-	uint32_t d_SOC_POWER_REG_OFFSET;
-	uint32_t d_PCIE_INTR_CAUSE_ADDRESS;
-	uint32_t d_SOC_RESET_CONTROL_ADDRESS;
-	uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK;
-	uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB;
-	uint32_t d_SOC_RESET_CONTROL_CE_RST_MASK;
-	uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
-	uint32_t d_CPU_INTR_ADDRESS;
-	uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
-	uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
-
-	/* chip id start */
-	uint32_t d_SOC_CHIP_ID_ADDRESS;
-	uint32_t d_SOC_CHIP_ID_VERSION_MASK;
-	uint32_t d_SOC_CHIP_ID_VERSION_LSB;
-	uint32_t d_SOC_CHIP_ID_REVISION_MASK;
-	uint32_t d_SOC_CHIP_ID_REVISION_LSB;
-	/* chip id end */
-
-	uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS;
-	uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS;
-	uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS;
-	uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS;
-	uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS;
-	uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS;
-	uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS;
-	uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS;
-	uint32_t d_A_SOC_CORE_SPARE_0_REGISTER;
-	uint32_t d_PCIE_INTR_FIRMWARE_ROUTE_MASK;
-	uint32_t d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1;
-	uint32_t d_A_SOC_CORE_SPARE_1_REGISTER;
-	uint32_t d_A_SOC_CORE_PCIE_INTR_CLR_GRP1;
-	uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1;
-	uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_0;
-	uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_1;
-	uint32_t d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA;
-	uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_2;
-	uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK;
-
-	uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
-	uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
-	uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
-	uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
-	uint32_t d_WLAN_DEBUG_CONTROL_OFFSET;
-	uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
-	uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
-	uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
-	uint32_t d_WLAN_DEBUG_OUT_OFFSET;
-	uint32_t d_WLAN_DEBUG_OUT_DATA_MSB;
-	uint32_t d_WLAN_DEBUG_OUT_DATA_LSB;
-	uint32_t d_WLAN_DEBUG_OUT_DATA_MASK;
-	uint32_t d_AMBA_DEBUG_BUS_OFFSET;
-	uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB;
-	uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB;
-	uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
-	uint32_t d_AMBA_DEBUG_BUS_SEL_MSB;
-	uint32_t d_AMBA_DEBUG_BUS_SEL_LSB;
-	uint32_t d_AMBA_DEBUG_BUS_SEL_MASK;
-
-#ifdef QCA_WIFI_3_0_ADRASTEA
-	uint32_t d_Q6_ENABLE_REGISTER_0;
-	uint32_t d_Q6_ENABLE_REGISTER_1;
-	uint32_t d_Q6_CAUSE_REGISTER_0;
-	uint32_t d_Q6_CAUSE_REGISTER_1;
-	uint32_t d_Q6_CLEAR_REGISTER_0;
-	uint32_t d_Q6_CLEAR_REGISTER_1;
-#endif
-};
-
-#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \
-	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
-#define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \
-	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1)
-#define A_SOC_CORE_SPARE_1_REGISTER \
-	(scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER)
-#define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \
-	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1)
-#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \
-	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1)
-#define A_SOC_PCIE_PCIE_SCRATCH_0 \
-	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0)
-#define A_SOC_PCIE_PCIE_SCRATCH_1 \
-	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1)
-#define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \
-	(scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA)
-#define A_SOC_PCIE_PCIE_SCRATCH_2 \
-	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2)
-/* end Q6 iHelium emu registers */
-
-#define PCIE_INTR_FIRMWARE_ROUTE_MASK \
-	(scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK)
-#define A_SOC_CORE_SPARE_0_REGISTER \
-	(scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
-#define A_SOC_CORE_SCRATCH_0_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
-#define A_SOC_CORE_SCRATCH_1_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
-#define A_SOC_CORE_SCRATCH_2_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
-#define A_SOC_CORE_SCRATCH_3_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
-#define A_SOC_CORE_SCRATCH_4_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
-#define A_SOC_CORE_SCRATCH_5_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
-#define A_SOC_CORE_SCRATCH_6_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
-#define A_SOC_CORE_SCRATCH_7_ADDRESS  \
-	(scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
-#define RTC_SOC_BASE_ADDRESS  (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
-#define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
-#define SYSTEM_SLEEP_OFFSET   (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
-#define WLAN_SYSTEM_SLEEP_OFFSET \
-	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
-#define WLAN_SYSTEM_SLEEP_DISABLE_LSB \
-	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
-#define WLAN_SYSTEM_SLEEP_DISABLE_MASK \
-	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
-#define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
-#define CLOCK_CONTROL_SI0_CLK_MASK \
-	(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
-#define RESET_CONTROL_OFFSET    (scn->targetdef->d_RESET_CONTROL_OFFSET)
-#define RESET_CONTROL_MBOX_RST_MASK \
-	(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
-#define RESET_CONTROL_SI0_RST_MASK \
-	(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
-#define WLAN_RESET_CONTROL_OFFSET \
-	(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
-#define WLAN_RESET_CONTROL_COLD_RST_MASK \
-	(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
-#define WLAN_RESET_CONTROL_WARM_RST_MASK \
-	(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
-#define GPIO_BASE_ADDRESS       (scn->targetdef->d_GPIO_BASE_ADDRESS)
-#define GPIO_PIN0_OFFSET        (scn->targetdef->d_GPIO_PIN0_OFFSET)
-#define GPIO_PIN1_OFFSET        (scn->targetdef->d_GPIO_PIN1_OFFSET)
-#define GPIO_PIN0_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
-#define GPIO_PIN1_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
-#define A_SOC_CORE_SCRATCH_0    (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
-#define SI_CONFIG_BIDIR_OD_DATA_LSB \
-	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
-#define SI_CONFIG_BIDIR_OD_DATA_MASK \
-	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
-#define SI_CONFIG_I2C_LSB       (scn->targetdef->d_SI_CONFIG_I2C_LSB)
-#define SI_CONFIG_I2C_MASK \
-	(scn->targetdef->d_SI_CONFIG_I2C_MASK)
-#define SI_CONFIG_POS_SAMPLE_LSB \
-	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
-#define SI_CONFIG_POS_SAMPLE_MASK \
-	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
-#define SI_CONFIG_INACTIVE_CLK_LSB \
-	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
-#define SI_CONFIG_INACTIVE_CLK_MASK \
-	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
-#define SI_CONFIG_INACTIVE_DATA_LSB \
-	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
-#define SI_CONFIG_INACTIVE_DATA_MASK \
-	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
-#define SI_CONFIG_DIVIDER_LSB   (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
-#define SI_CONFIG_DIVIDER_MASK  (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
-#define SI_BASE_ADDRESS         (scn->targetdef->d_SI_BASE_ADDRESS)
-#define SI_CONFIG_OFFSET        (scn->targetdef->d_SI_CONFIG_OFFSET)
-#define SI_TX_DATA0_OFFSET      (scn->targetdef->d_SI_TX_DATA0_OFFSET)
-#define SI_TX_DATA1_OFFSET      (scn->targetdef->d_SI_TX_DATA1_OFFSET)
-#define SI_RX_DATA0_OFFSET      (scn->targetdef->d_SI_RX_DATA0_OFFSET)
-#define SI_RX_DATA1_OFFSET      (scn->targetdef->d_SI_RX_DATA1_OFFSET)
-#define SI_CS_OFFSET            (scn->targetdef->d_SI_CS_OFFSET)
-#define SI_CS_DONE_ERR_MASK     (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
-#define SI_CS_DONE_INT_MASK     (scn->targetdef->d_SI_CS_DONE_INT_MASK)
-#define SI_CS_START_LSB         (scn->targetdef->d_SI_CS_START_LSB)
-#define SI_CS_START_MASK        (scn->targetdef->d_SI_CS_START_MASK)
-#define SI_CS_RX_CNT_LSB        (scn->targetdef->d_SI_CS_RX_CNT_LSB)
-#define SI_CS_RX_CNT_MASK       (scn->targetdef->d_SI_CS_RX_CNT_MASK)
-#define SI_CS_TX_CNT_LSB        (scn->targetdef->d_SI_CS_TX_CNT_LSB)
-#define SI_CS_TX_CNT_MASK       (scn->targetdef->d_SI_CS_TX_CNT_MASK)
-#define EEPROM_SZ               (scn->targetdef->d_BOARD_DATA_SZ)
-#define EEPROM_EXT_SZ           (scn->targetdef->d_BOARD_EXT_DATA_SZ)
-#define MBOX_BASE_ADDRESS       (scn->targetdef->d_MBOX_BASE_ADDRESS)
-#define LOCAL_SCRATCH_OFFSET    (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
-#define CPU_CLOCK_OFFSET        (scn->targetdef->d_CPU_CLOCK_OFFSET)
-#define LPO_CAL_OFFSET          (scn->targetdef->d_LPO_CAL_OFFSET)
-#define GPIO_PIN10_OFFSET       (scn->targetdef->d_GPIO_PIN10_OFFSET)
-#define GPIO_PIN11_OFFSET       (scn->targetdef->d_GPIO_PIN11_OFFSET)
-#define GPIO_PIN12_OFFSET       (scn->targetdef->d_GPIO_PIN12_OFFSET)
-#define GPIO_PIN13_OFFSET       (scn->targetdef->d_GPIO_PIN13_OFFSET)
-#define CLOCK_GPIO_OFFSET       (scn->targetdef->d_CLOCK_GPIO_OFFSET)
-#define CPU_CLOCK_STANDARD_LSB  (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
-#define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
-#define LPO_CAL_ENABLE_LSB      (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
-#define LPO_CAL_ENABLE_MASK     (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
-#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \
-	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
-#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \
-	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
-#define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
-#define WLAN_MAC_BASE_ADDRESS    (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
-#define FW_INDICATOR_ADDRESS     (scn->targetdef->d_FW_INDICATOR_ADDRESS)
-#define DRAM_BASE_ADDRESS        (scn->targetdef->d_DRAM_BASE_ADDRESS)
-#define SOC_CORE_BASE_ADDRESS    (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
-#define CORE_CTRL_ADDRESS        (scn->targetdef->d_CORE_CTRL_ADDRESS)
-#define CE_COUNT                 (scn->targetdef->d_CE_COUNT)
-#define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
-#define PCIE_INTR_CLR_ADDRESS    (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
-#define PCIE_INTR_FIRMWARE_MASK  (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
-#define PCIE_INTR_CE_MASK_ALL    (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
-#define CORE_CTRL_CPU_INTR_MASK  (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
-#define PCIE_INTR_CAUSE_ADDRESS  (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
-#define SOC_RESET_CONTROL_ADDRESS  (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
-#define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \
-	A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
-#define SOC_RESET_CONTROL_CE_RST_MASK \
-	(scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
-#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \
-	(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
-#define CPU_INTR_ADDRESS        (scn->targetdef->d_CPU_INTR_ADDRESS)
-#define SOC_LF_TIMER_CONTROL0_ADDRESS \
-	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
-#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
-	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
-#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
-	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
-#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \
-	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
-
-#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \
-	(((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \
-	 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
-#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \
-	(((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \
-		SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
-
-/* hif_pci.c */
-#define CHIP_ID_ADDRESS           (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
-#define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
-#define SOC_CHIP_ID_REVISION_LSB  (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
-#define SOC_CHIP_ID_VERSION_MASK  (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
-#define SOC_CHIP_ID_VERSION_LSB   (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
-#define CHIP_ID_REVISION_GET(x) \
-	(((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB)
-#define CHIP_ID_VERSION_GET(x) \
-	(((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB)
-/* hif_pci.c end */
-
-/* misc */
-#define SR_WR_INDEX_ADDRESS     (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
-#define DST_WATERMARK_ADDRESS   (scn->targetdef->d_DST_WATERMARK_ADDRESS)
-#define SOC_POWER_REG_OFFSET    (scn->targetdef->d_SOC_POWER_REG_OFFSET)
-/* end */
-
-/* htt_rx.c */
-#define RX_MSDU_END_4_FIRST_MSDU_MASK \
-	(pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK)
-#define RX_MSDU_END_4_FIRST_MSDU_LSB \
-	(pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB)
-#define RX_MPDU_START_0_RETRY_LSB  \
-	(pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB)
-#define RX_MPDU_START_0_RETRY_MASK  \
-	(pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK)
-#define RX_MPDU_START_0_SEQ_NUM_MASK \
-	(pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK)
-#define RX_MPDU_START_0_SEQ_NUM_LSB \
-	(pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB)
-#define RX_MPDU_START_2_PN_47_32_LSB \
-	(pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB)
-#define RX_MPDU_START_2_PN_47_32_MASK \
-	(pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK)
-#define RX_MPDU_START_2_TID_LSB  \
-	(pdev->targetdef->d_RX_MPDU_START_2_TID_LSB)
-#define RX_MPDU_START_2_TID_MASK  \
-	(pdev->targetdef->d_RX_MPDU_START_2_TID_MASK)
-#define RX_MSDU_END_1_KEY_ID_OCT_MASK \
-	(pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK)
-#define RX_MSDU_END_1_KEY_ID_OCT_LSB \
-	(pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB)
-#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \
-	(pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK)
-#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB \
-	(pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB)
-#define RX_MSDU_END_4_LAST_MSDU_MASK \
-	(pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK)
-#define RX_MSDU_END_4_LAST_MSDU_LSB \
-	(pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB)
-#define RX_ATTENTION_0_MCAST_BCAST_MASK \
-	(pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK)
-#define RX_ATTENTION_0_MCAST_BCAST_LSB \
-	(pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB)
-#define RX_ATTENTION_0_FRAGMENT_MASK \
-	(pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK)
-#define RX_ATTENTION_0_FRAGMENT_LSB \
-	(pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB)
-#define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK \
-	(pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK)
-#define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \
-	(pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK)
-#define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB \
-	(pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB)
-#define RX_MSDU_START_0_MSDU_LENGTH_MASK \
-	(pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK)
-#define RX_MSDU_START_0_MSDU_LENGTH_LSB \
-	(pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB)
-#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET \
-	(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET)
-#define RX_MSDU_START_2_DECAP_FORMAT_MASK \
-	(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK)
-#define RX_MSDU_START_2_DECAP_FORMAT_LSB \
-	(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB)
-#define RX_MPDU_START_0_ENCRYPTED_MASK \
-	(pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK)
-#define RX_MPDU_START_0_ENCRYPTED_LSB \
-	(pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB)
-#define RX_ATTENTION_0_MORE_DATA_MASK \
-	(pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK)
-#define RX_ATTENTION_0_MSDU_DONE_MASK \
-	(pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK)
-#define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \
-	(pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK)
-/* end */
-
-/* copy_engine.c */
-/* end */
-/* PLL start */
-#define EFUSE_OFFSET              (scn->targetdef->d_EFUSE_OFFSET)
-#define EFUSE_XTAL_SEL_MSB        (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
-#define EFUSE_XTAL_SEL_LSB        (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
-#define EFUSE_XTAL_SEL_MASK       (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
-#define BB_PLL_CONFIG_OFFSET      (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
-#define BB_PLL_CONFIG_OUTDIV_MSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
-#define BB_PLL_CONFIG_OUTDIV_LSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
-#define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
-#define BB_PLL_CONFIG_FRAC_MSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
-#define BB_PLL_CONFIG_FRAC_LSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
-#define BB_PLL_CONFIG_FRAC_MASK   (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
-#define WLAN_PLL_SETTLE_TIME_MSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
-#define WLAN_PLL_SETTLE_TIME_LSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
-#define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
-#define WLAN_PLL_SETTLE_OFFSET    (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
-#define WLAN_PLL_SETTLE_SW_MASK   (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
-#define WLAN_PLL_SETTLE_RSTMASK   (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
-#define WLAN_PLL_SETTLE_RESET     (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
-#define WLAN_PLL_CONTROL_NOPWD_MSB  \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
-#define WLAN_PLL_CONTROL_NOPWD_LSB  \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
-#define WLAN_PLL_CONTROL_NOPWD_MASK \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
-#define WLAN_PLL_CONTROL_BYPASS_MSB \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
-#define WLAN_PLL_CONTROL_BYPASS_LSB \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
-#define WLAN_PLL_CONTROL_BYPASS_MASK \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
-#define WLAN_PLL_CONTROL_BYPASS_RESET \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
-#define WLAN_PLL_CONTROL_CLK_SEL_MSB \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
-#define WLAN_PLL_CONTROL_CLK_SEL_LSB \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
-#define WLAN_PLL_CONTROL_CLK_SEL_MASK \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
-#define WLAN_PLL_CONTROL_CLK_SEL_RESET \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
-#define WLAN_PLL_CONTROL_REFDIV_MSB \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
-#define WLAN_PLL_CONTROL_REFDIV_LSB \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
-#define WLAN_PLL_CONTROL_REFDIV_MASK \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
-#define WLAN_PLL_CONTROL_REFDIV_RESET \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
-#define WLAN_PLL_CONTROL_DIV_MSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
-#define WLAN_PLL_CONTROL_DIV_LSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
-#define WLAN_PLL_CONTROL_DIV_MASK  (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
-#define WLAN_PLL_CONTROL_DIV_RESET \
-	(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
-#define WLAN_PLL_CONTROL_OFFSET    (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
-#define WLAN_PLL_CONTROL_SW_MASK   (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
-#define WLAN_PLL_CONTROL_RSTMASK   (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
-#define WLAN_PLL_CONTROL_RESET     (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
-#define SOC_CORE_CLK_CTRL_OFFSET   (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
-#define SOC_CORE_CLK_CTRL_DIV_MSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
-#define SOC_CORE_CLK_CTRL_DIV_LSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
-#define SOC_CORE_CLK_CTRL_DIV_MASK \
-	(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
-#define RTC_SYNC_STATUS_PLL_CHANGING_MSB \
-	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
-#define RTC_SYNC_STATUS_PLL_CHANGING_LSB \
-	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
-#define RTC_SYNC_STATUS_PLL_CHANGING_MASK \
-	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
-#define RTC_SYNC_STATUS_PLL_CHANGING_RESET \
-	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
-#define RTC_SYNC_STATUS_OFFSET      (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
-#define SOC_CPU_CLOCK_OFFSET        (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
-#define SOC_CPU_CLOCK_STANDARD_MSB \
-	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
-#define SOC_CPU_CLOCK_STANDARD_LSB \
-	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
-#define SOC_CPU_CLOCK_STANDARD_MASK \
-	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
-/* PLL end */
-
-/* SET macros */
-#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \
-	(((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
-	    WLAN_SYSTEM_SLEEP_DISABLE_MASK)
-#define SI_CONFIG_BIDIR_OD_DATA_SET(x) \
-	(((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
-#define SI_CONFIG_I2C_SET(x)  (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
-#define SI_CONFIG_POS_SAMPLE_SET(x) \
-	(((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
-#define SI_CONFIG_INACTIVE_CLK_SET(x) \
-	(((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
-#define SI_CONFIG_INACTIVE_DATA_SET(x) \
-	(((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
-#define SI_CONFIG_DIVIDER_SET(x) \
-	(((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
-#define SI_CS_START_SET(x)  (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
-#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
-#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
-#define LPO_CAL_ENABLE_SET(x) \
-	(((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
-#define CPU_CLOCK_STANDARD_SET(x) \
-	(((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
-#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \
-	(((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
-/* copy_engine.c */
-/* end */
-/* PLL start */
-#define EFUSE_XTAL_SEL_GET(x) \
-	(((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB)
-#define EFUSE_XTAL_SEL_SET(x) \
-	(((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK)
-#define BB_PLL_CONFIG_OUTDIV_GET(x) \
-	(((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB)
-#define BB_PLL_CONFIG_OUTDIV_SET(x) \
-	(((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK)
-#define BB_PLL_CONFIG_FRAC_GET(x) \
-	(((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
-#define BB_PLL_CONFIG_FRAC_SET(x) \
-	(((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
-#define WLAN_PLL_SETTLE_TIME_GET(x) \
-	(((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
-#define WLAN_PLL_SETTLE_TIME_SET(x) \
-	(((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
-#define WLAN_PLL_CONTROL_NOPWD_GET(x) \
-	(((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
-#define WLAN_PLL_CONTROL_NOPWD_SET(x) \
-	(((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
-#define WLAN_PLL_CONTROL_BYPASS_GET(x) \
-	(((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
-#define WLAN_PLL_CONTROL_BYPASS_SET(x) \
-	(((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
-#define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \
-	(((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB)
-#define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \
-	(((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK)
-#define WLAN_PLL_CONTROL_REFDIV_GET(x) \
-	(((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
-#define WLAN_PLL_CONTROL_REFDIV_SET(x) \
-	(((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
-#define WLAN_PLL_CONTROL_DIV_GET(x) \
-	(((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
-#define WLAN_PLL_CONTROL_DIV_SET(x) \
-	(((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
-#define SOC_CORE_CLK_CTRL_DIV_GET(x) \
-	(((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
-#define SOC_CORE_CLK_CTRL_DIV_SET(x) \
-	(((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
-#define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \
-	(((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \
-		RTC_SYNC_STATUS_PLL_CHANGING_LSB)
-#define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \
-	(((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \
-		RTC_SYNC_STATUS_PLL_CHANGING_MASK)
-#define SOC_CPU_CLOCK_STANDARD_GET(x) \
-	(((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
-#define SOC_CPU_CLOCK_STANDARD_SET(x) \
-	(((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
-/* PLL end */
-
-#ifdef QCA_WIFI_3_0_ADRASTEA
-#define Q6_ENABLE_REGISTER_0 \
-	(scn->targetdef->d_Q6_ENABLE_REGISTER_0)
-#define Q6_ENABLE_REGISTER_1 \
-	(scn->targetdef->d_Q6_ENABLE_REGISTER_1)
-#define Q6_CAUSE_REGISTER_0 \
-	(scn->targetdef->d_Q6_CAUSE_REGISTER_0)
-#define Q6_CAUSE_REGISTER_1 \
-	(scn->targetdef->d_Q6_CAUSE_REGISTER_1)
-#define Q6_CLEAR_REGISTER_0 \
-	(scn->targetdef->d_Q6_CLEAR_REGISTER_0)
-#define Q6_CLEAR_REGISTER_1 \
-	(scn->targetdef->d_Q6_CLEAR_REGISTER_1)
-#endif
-
-struct hostdef_s {
-	A_UINT32 d_INT_STATUS_ENABLE_ERROR_LSB;
-	A_UINT32 d_INT_STATUS_ENABLE_ERROR_MASK;
-	A_UINT32 d_INT_STATUS_ENABLE_CPU_LSB;
-	A_UINT32 d_INT_STATUS_ENABLE_CPU_MASK;
-	A_UINT32 d_INT_STATUS_ENABLE_COUNTER_LSB;
-	A_UINT32 d_INT_STATUS_ENABLE_COUNTER_MASK;
-	A_UINT32 d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
-	A_UINT32 d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
-	A_UINT32 d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
-	A_UINT32 d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
-	A_UINT32 d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
-	A_UINT32 d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
-	A_UINT32 d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
-	A_UINT32 d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
-	A_UINT32 d_INT_STATUS_ENABLE_ADDRESS;
-	A_UINT32 d_CPU_INT_STATUS_ENABLE_BIT_LSB;
-	A_UINT32 d_CPU_INT_STATUS_ENABLE_BIT_MASK;
-	A_UINT32 d_HOST_INT_STATUS_ADDRESS;
-	A_UINT32 d_CPU_INT_STATUS_ADDRESS;
-	A_UINT32 d_ERROR_INT_STATUS_ADDRESS;
-	A_UINT32 d_ERROR_INT_STATUS_WAKEUP_MASK;
-	A_UINT32 d_ERROR_INT_STATUS_WAKEUP_LSB;
-	A_UINT32 d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
-	A_UINT32 d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
-	A_UINT32 d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
-	A_UINT32 d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
-	A_UINT32 d_COUNT_DEC_ADDRESS;
-	A_UINT32 d_HOST_INT_STATUS_CPU_MASK;
-	A_UINT32 d_HOST_INT_STATUS_CPU_LSB;
-	A_UINT32 d_HOST_INT_STATUS_ERROR_MASK;
-	A_UINT32 d_HOST_INT_STATUS_ERROR_LSB;
-	A_UINT32 d_HOST_INT_STATUS_COUNTER_MASK;
-	A_UINT32 d_HOST_INT_STATUS_COUNTER_LSB;
-	A_UINT32 d_RX_LOOKAHEAD_VALID_ADDRESS;
-	A_UINT32 d_WINDOW_DATA_ADDRESS;
-	A_UINT32 d_WINDOW_READ_ADDR_ADDRESS;
-	A_UINT32 d_WINDOW_WRITE_ADDR_ADDRESS;
-	A_UINT32 d_SOC_GLOBAL_RESET_ADDRESS;
-	A_UINT32 d_RTC_STATE_ADDRESS;
-	A_UINT32 d_RTC_STATE_COLD_RESET_MASK;
-	A_UINT32 d_PCIE_LOCAL_BASE_ADDRESS;
-	A_UINT32 d_PCIE_SOC_WAKE_RESET;
-	A_UINT32 d_PCIE_SOC_WAKE_ADDRESS;
-	A_UINT32 d_PCIE_SOC_WAKE_V_MASK;
-	A_UINT32 d_RTC_STATE_V_MASK;
-	A_UINT32 d_RTC_STATE_V_LSB;
-	A_UINT32 d_FW_IND_EVENT_PENDING;
-	A_UINT32 d_FW_IND_INITIALIZED;
-	A_UINT32 d_FW_IND_HELPER;
-	A_UINT32 d_RTC_STATE_V_ON;
-#if defined(SDIO_3_0)
-	A_UINT32 d_HOST_INT_STATUS_MBOX_DATA_MASK;
-	A_UINT32 d_HOST_INT_STATUS_MBOX_DATA_LSB;
-#endif
-	A_UINT32 d_PCIE_SOC_RDY_STATUS_ADDRESS;
-	A_UINT32 d_PCIE_SOC_RDY_STATUS_BAR_MASK;
-	A_UINT32 d_SOC_PCIE_BASE_ADDRESS;
-	A_UINT32 d_MSI_MAGIC_ADR_ADDRESS;
-	A_UINT32 d_MSI_MAGIC_ADDRESS;
-	uint32_t d_HOST_CE_COUNT;
-	uint32_t d_ENABLE_MSI;
-	uint32_t d_MUX_ID_MASK;
-	uint32_t d_TRANSACTION_ID_MASK;
-	uint32_t d_DESC_DATA_FLAG_MASK;
-	uint32_t d_A_SOC_PCIE_PCIE_BAR0_START;
-};
-#define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
-#define DESC_DATA_FLAG_MASK        (scn->hostdef->d_DESC_DATA_FLAG_MASK)
-#define MUX_ID_MASK                (scn->hostdef->d_MUX_ID_MASK)
-#define TRANSACTION_ID_MASK        (scn->hostdef->d_TRANSACTION_ID_MASK)
-#define HOST_CE_COUNT              (scn->hostdef->d_HOST_CE_COUNT)
-#define ENABLE_MSI                 (scn->hostdef->d_ENABLE_MSI)
-#define INT_STATUS_ENABLE_ERROR_LSB \
-	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
-#define INT_STATUS_ENABLE_ERROR_MASK \
-	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
-#define INT_STATUS_ENABLE_CPU_LSB  (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
-#define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
-#define INT_STATUS_ENABLE_COUNTER_LSB \
-	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
-#define INT_STATUS_ENABLE_COUNTER_MASK \
-	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
-#define INT_STATUS_ENABLE_MBOX_DATA_LSB \
-	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
-#define INT_STATUS_ENABLE_MBOX_DATA_MASK \
-	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \
-	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \
-	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \
-	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \
-	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
-#define COUNTER_INT_STATUS_ENABLE_BIT_LSB \
-	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
-#define COUNTER_INT_STATUS_ENABLE_BIT_MASK \
-	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
-#define INT_STATUS_ENABLE_ADDRESS \
-	(scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
-#define CPU_INT_STATUS_ENABLE_BIT_LSB \
-	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
-#define CPU_INT_STATUS_ENABLE_BIT_MASK \
-	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
-#define HOST_INT_STATUS_ADDRESS     (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
-#define CPU_INT_STATUS_ADDRESS      (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
-#define ERROR_INT_STATUS_ADDRESS    (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
-#define ERROR_INT_STATUS_WAKEUP_MASK \
-	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
-#define ERROR_INT_STATUS_WAKEUP_LSB \
-	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
-#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \
-	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
-#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \
-	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
-#define ERROR_INT_STATUS_TX_OVERFLOW_MASK \
-	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
-#define ERROR_INT_STATUS_TX_OVERFLOW_LSB \
-	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
-#define COUNT_DEC_ADDRESS          (scn->hostdef->d_COUNT_DEC_ADDRESS)
-#define HOST_INT_STATUS_CPU_MASK   (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
-#define HOST_INT_STATUS_CPU_LSB    (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
-#define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
-#define HOST_INT_STATUS_ERROR_LSB  (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
-#define HOST_INT_STATUS_COUNTER_MASK \
-	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
-#define HOST_INT_STATUS_COUNTER_LSB \
-	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
-#define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
-#define WINDOW_DATA_ADDRESS        (scn->hostdef->d_WINDOW_DATA_ADDRESS)
-#define WINDOW_READ_ADDR_ADDRESS   (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
-#define WINDOW_WRITE_ADDR_ADDRESS  (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
-#define SOC_GLOBAL_RESET_ADDRESS   (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
-#define RTC_STATE_ADDRESS          (scn->hostdef->d_RTC_STATE_ADDRESS)
-#define RTC_STATE_COLD_RESET_MASK  (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
-#define PCIE_LOCAL_BASE_ADDRESS    (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
-#define PCIE_SOC_WAKE_RESET        (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
-#define PCIE_SOC_WAKE_ADDRESS      (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
-#define PCIE_SOC_WAKE_V_MASK       (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
-#define RTC_STATE_V_MASK           (scn->hostdef->d_RTC_STATE_V_MASK)
-#define RTC_STATE_V_LSB            (scn->hostdef->d_RTC_STATE_V_LSB)
-#define FW_IND_EVENT_PENDING       (scn->hostdef->d_FW_IND_EVENT_PENDING)
-#define FW_IND_INITIALIZED         (scn->hostdef->d_FW_IND_INITIALIZED)
-#define FW_IND_HELPER              (scn->hostdef->d_FW_IND_HELPER)
-#define RTC_STATE_V_ON             (scn->hostdef->d_RTC_STATE_V_ON)
-#if defined(SDIO_3_0)
-#define HOST_INT_STATUS_MBOX_DATA_MASK \
-	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
-#define HOST_INT_STATUS_MBOX_DATA_LSB \
-	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
-#endif
-
-#if !defined(SOC_PCIE_BASE_ADDRESS)
-#define SOC_PCIE_BASE_ADDRESS 0
-#endif
-
-#if !defined(PCIE_SOC_RDY_STATUS_ADDRESS)
-#define PCIE_SOC_RDY_STATUS_ADDRESS 0
-#define PCIE_SOC_RDY_STATUS_BAR_MASK 0
-#endif
-
-#if !defined(MSI_MAGIC_ADR_ADDRESS)
-#define MSI_MAGIC_ADR_ADDRESS 0
-#define MSI_MAGIC_ADDRESS 0
-#endif
-
-/* SET/GET macros */
-#define INT_STATUS_ENABLE_ERROR_SET(x) \
-	(((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
-#define INT_STATUS_ENABLE_CPU_SET(x) \
-	(((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
-#define INT_STATUS_ENABLE_COUNTER_SET(x) \
-	(((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \
-		INT_STATUS_ENABLE_COUNTER_MASK)
-#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \
-	(((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \
-	 INT_STATUS_ENABLE_MBOX_DATA_MASK)
-#define CPU_INT_STATUS_ENABLE_BIT_SET(x) \
-	(((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \
-		CPU_INT_STATUS_ENABLE_BIT_MASK)
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \
-	(((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \
-		ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \
-	(((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \
-		ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
-#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \
-	(((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \
-		COUNTER_INT_STATUS_ENABLE_BIT_MASK)
-#define ERROR_INT_STATUS_WAKEUP_GET(x) \
-	(((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \
-		ERROR_INT_STATUS_WAKEUP_LSB)
-#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \
-	(((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \
-		ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
-#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \
-	(((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \
-		ERROR_INT_STATUS_TX_OVERFLOW_LSB)
-#define HOST_INT_STATUS_CPU_GET(x) \
-	(((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
-#define HOST_INT_STATUS_ERROR_GET(x) \
-	(((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
-#define HOST_INT_STATUS_COUNTER_GET(x) \
-	(((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
-#define RTC_STATE_V_GET(x) \
-	(((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
-#if defined(SDIO_3_0)
-#define HOST_INT_STATUS_MBOX_DATA_GET(x) \
-	(((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \
-		HOST_INT_STATUS_MBOX_DATA_LSB)
-#endif
-
-#define INVALID_REG_LOC_DUMMY_DATA 0xAA
-
-#define AR6320_CORE_CLK_DIV_ADDR        0x403fa8
-#define AR6320_CPU_PLL_INIT_DONE_ADDR   0x403fd0
-#define AR6320_CPU_SPEED_ADDR           0x403fa4
-#define AR6320V2_CORE_CLK_DIV_ADDR      0x403fd8
-#define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0
-#define AR6320V2_CPU_SPEED_ADDR         0x403fd4
-#define AR6320V3_CORE_CLK_DIV_ADDR      0x404028
-#define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020
-#define AR6320V3_CPU_SPEED_ADDR         0x404024
-
-typedef enum {
-	SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
-	SOC_REFCLK_48_MHZ = 0,
-	SOC_REFCLK_19_2_MHZ = 1,
-	SOC_REFCLK_24_MHZ = 2,
-	SOC_REFCLK_26_MHZ = 3,
-	SOC_REFCLK_37_4_MHZ = 4,
-	SOC_REFCLK_38_4_MHZ = 5,
-	SOC_REFCLK_40_MHZ = 6,
-	SOC_REFCLK_52_MHZ = 7,
-} A_refclk_speed_t;
-
-#define A_REFCLK_UNKNOWN    SOC_REFCLK_UNKNOWN
-#define A_REFCLK_48_MHZ     SOC_REFCLK_48_MHZ
-#define A_REFCLK_19_2_MHZ   SOC_REFCLK_19_2_MHZ
-#define A_REFCLK_24_MHZ     SOC_REFCLK_24_MHZ
-#define A_REFCLK_26_MHZ     SOC_REFCLK_26_MHZ
-#define A_REFCLK_37_4_MHZ   SOC_REFCLK_37_4_MHZ
-#define A_REFCLK_38_4_MHZ   SOC_REFCLK_38_4_MHZ
-#define A_REFCLK_40_MHZ     SOC_REFCLK_40_MHZ
-#define A_REFCLK_52_MHZ     SOC_REFCLK_52_MHZ
-
-#define TARGET_CPU_FREQ 176000000
-
-struct wlan_pll_s {
-	uint32_t refdiv;
-	uint32_t div;
-	uint32_t rnfrac;
-	uint32_t outdiv;
-};
-
-struct cmnos_clock_s {
-	A_refclk_speed_t refclk_speed;
-	uint32_t refclk_hz;
-	uint32_t pll_settling_time;     /* 50us */
-	struct wlan_pll_s wlan_pll;
-};
-
-typedef struct TGT_REG_SECTION {
-	uint32_t start_addr;
-	uint32_t end_addr;
-} tgt_reg_section;
-
-typedef struct TGT_REG_TABLE {
-	tgt_reg_section *section;
-	uint32_t section_size;
-} tgt_reg_table;
-
-struct ol_softc;
-void target_register_tbl_attach(struct ol_softc *scn, u32 target_type);
-void hif_register_tbl_attach(struct ol_softc *scn, u32 hif_type);
-
-struct host_shadow_regs_s {
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_0;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_1;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_2;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_3;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_4;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_5;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_6;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_7;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_8;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_9;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_10;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_11;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_12;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_13;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_14;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_15;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_16;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_17;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_18;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_19;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_20;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_21;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_22;
-	uint32_t d_A_LOCAL_SHADOW_REG_VALUE_23;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_0;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_1;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_2;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_3;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_4;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_5;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_6;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_7;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_8;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_9;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_10;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_11;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_12;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_13;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_14;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_15;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_16;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_17;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_18;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_19;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_20;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_21;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_22;
-	uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_23;
-};
-
-#endif /* _REGTABLE_PCIE_H_ */

core/hif/src/adrastea_reg_def.h

@@ -1,2367 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef ADRASTEA_REG_DEF_H
-#define ADRASTEA_REG_DEF_H
-
-/*
- *  Start auto-generated headers from register parser
- *
- *  DO NOT CHANGE MANUALLY
-*/
-
-
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___S 1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW (0x00241000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___M 0x00000001
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2 (0x00030028)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___POR 0x000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW (0x00244000)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___M 0x00000001
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___M 0x000003FF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE (0x00032060)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6 (0x00030038)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH (0x00032064)
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY___M 0x00FFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___S 1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___M 0x00000010
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___M 0x00000080
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___M 0x00000010
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___S 17
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___M 0x0003FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___M 0x00000002
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___M 0x00FFF000
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___M 0x00FFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4 (0x00030030)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___M 0x00000100
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___S 4
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___M 0x00000001
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX (0x00240040)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS (0x00240038)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR (0x002F1008)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___M 0x00000080
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___M 0x00000010
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___M 0x00000FFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___M 0x00000002
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20 (0x00030070)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12 (0x00032030)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___M 0x00000002
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___POR 0x000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___S 18
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___M 0x00000FFF
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB (0x00032070)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___M 0x00000080
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___S 9
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13 (0x00032034)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3 (0x0003002C)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID (0x000300E0)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22 (0x00032058)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___M 0x00000020
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14 (0x00030058)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___M 0x0000007F
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___S 19
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1 (0x00032004)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___S 5
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___M 0x00000004
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___M 0x00000FFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14 (0x00032038)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___M 0x00000010
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___M 0x00000FFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___M 0x00000001
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___S 1
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___M 0x00000010
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___S 4
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___M 0x0000001F
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23 (0x0003205C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE (0x00240034)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY (0x0024D000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15 (0x0003005C)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE (0x0024002C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___S 4
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___S 7
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___M 0x0000001F
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___M 0x00000010
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___M 0x01FFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___POR 0x000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___POR 0x0000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___S 24
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0 (0x00032000)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___M 0xFFFF0000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR (0x00030014)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___M 0x00000080
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20 (0x00032050)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___S 3
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___S 2
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___M 0x00008000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___POR 0x0000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___M 0x00020000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW (0x0024B000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET (0x002F1004)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2 (0x00032008)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___S 5
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___M 0xFFFF0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___POR 0x00
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___M 0x00000002
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___M 0x00000001
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___S 2
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___M 0x00000060
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___S 6
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___M 0x0FFC0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___POR 0x0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___S 6
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___S 8
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW (0x00245000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22 (0x00030078)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___M 0x00000040
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___POR 0x00000005
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___S 3
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___POR 0x000
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___S 1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___POR 0x1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK (0x0024004C)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___M 0x00000004
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___S 11
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17 (0x00030064)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW (0x0024000C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___M 0x00FFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW (0x0024A000)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___S 4
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___M 0x00000003
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___M 0x00000040
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS (0x00030008)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___S 3
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___M 0x00010000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___M 0x000FF800
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___S 8
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___M 0x00000010
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19 (0x0003204C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___S 3
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5 (0x00030034)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___M 0x00000020
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___M 0x00000FFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___M 0x00FFF000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___S 4
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___S 16
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___M 0x000FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___M 0x000FF800
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___M 0x00010000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___POR 0x0000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___S 8
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___M 0x00000080
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___POR 0x0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5 (0x00032014)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS (0x0003000C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___M 0x0000001F
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___S 16
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9 (0x00032024)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___M 0x00000001
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___M 0x0000001F
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___M 0x00000001
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___S 11
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___POR 0x000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___S 6
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___M 0x00004000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___M 0x00000004
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___M 0x00020000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___M 0x00000008
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___M 0x00000008
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___POR 0x00000080
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18 (0x00032048)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___M 0x00001000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK (0x00240050)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW (0x00243000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___S 16
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY (0x00030080)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW (0x00248000)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___S 2
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16 (0x00032040)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___M 0x0000000F
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___S 16
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY (0x0024C000)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___M 0x00000800
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___S 18
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS (0x00032078)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___S 2
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12 (0x00030050)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___M 0x00000007
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___M 0x00000020
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___M 0x00000004
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___S 14
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___M 0x00000004
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___M 0x00040000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___S 8
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___M 0x00000100
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7 (0x0003003C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET (0x002F0084)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___POR 0x0000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___S 2
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___POR 0x000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8 (0x00030040)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS (0x00240030)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___M 0x00000010
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15 (0x0003203C)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___M 0x00000002
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH (0x00240004)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___S 17
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___S 6
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___S 4
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___POR 0x0080
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___POR 0x0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___S 3
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___S 3
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW (0x00240000)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13 (0x00030054)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___S 15
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH (0x00240010)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___S 11
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___S 2
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4 (0x00032010)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___M 0x00000001
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___S 7
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___S 7
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW (0x00246000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___POR 0x000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___S 12
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___POR 0x000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___M 0x00000004
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23 (0x0003007C)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___M 0x0000001F
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___M 0x00000040
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___S 16
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___S 12
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___POR 0x00
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___M 0x00000100
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___POR 0x1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1 (0x00240018)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19 (0x0003006C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX (0x0024003C)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___M 0x0000000F
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___POR 0x0000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___M 0x0000000F
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___M 0x0FFFDDFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7 (0x0003201C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___M 0x00000004
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___S 3
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___M 0x0000000C
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___POR 0x0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___S 1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___M 0x00000001
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___S 1
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___S 7
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___S 3
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___RWC QCSR_REG_WO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___M 0x00000FFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___S 16
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___M 0x00000002
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16 (0x00030060)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS (0x00030144)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___POR 0x0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17 (0x00032044)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___M 0x000003FF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___M 0x00020000
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___M 0x00000002
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___M 0xFFFF0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___S 1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___S 8
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___M 0x00000001
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___POR 0x0000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___M 0x000FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___S 4
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___M 0x000FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___M 0x00000007
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___S 6
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___S 1
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW (0x00242000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___S 7
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___S 4
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE (0x00030010)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___M 0x00000002
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8 (0x00032020)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___M 0x00000FFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M 0x00080000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___S 6
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0 (0x00030020)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___S 5
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___M 0x00FFF000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___POR 0x0000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___M 0x01000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11 (0x0003004C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___M 0x00000400
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___POR 0x0000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB (0x0003206C)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___M 0x00000001
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE (0x00240014)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___M 0x00000007
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11 (0x0003202C)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI (0x00240048)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___S 3
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW (0x00249000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___S 4
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___S 8
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___M 0x00000004
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___S 2
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___M 0x00000001
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___S 1
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___S 16
-#define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___M 0x00010000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___POR 0x000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL (0x00030000)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI (0x00240044)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___M 0x00FFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___M 0x000003FF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD (0x00240020)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___M 0x00000004
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___S 12
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES (0x002F1000)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9 (0x00030044)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6 (0x00032018)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21 (0x00032054)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___M 0x0000001F
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___S 12
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW (0x00247000)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18 (0x00030068)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___M 0x00000040
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___M 0x00000010
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___S 2
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE (0x00240008)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___S 3
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___M 0x00000040
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___M 0x00000080
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1 (0x00030024)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2 (0x0024001C)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___M 0x00000002
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21 (0x00030074)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___S 7
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB (0x00032074)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___M 0x00000001
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___S 2
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___S 2
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___M 0xFFFF0000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10 (0x00030048)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___S 5
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___M 0x0000FFFF
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___M 0x003FFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___M 0x00000002
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___M 0x00000001
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___S 10
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___S 3
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___RWC QCSR_REG_RO
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___S 9
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___POR 0x000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___S 2
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB (0x00032068)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___S 17
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___S 0
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___M 0x00000040
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___M 0x00000200
-#define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY (0x00030004)
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___RWC QCSR_REG_RW
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___S 0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___POR 0x0
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___M 0x00000004
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___POR 0x0
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10 (0x00032028)
-#define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___M 0x00000008
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3 (0x0003200C)
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___POR 0x00000000
-#define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___S 1
-#define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___S 0
-
-
-/* End auto-generated headers from register parser */
-
-#define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW	0x0024C004
-#define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH	0x0024C008
-
-#define MISSING                                        0
-#define MISSING_FOR_ADRASTEA                           MISSING
-#define ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS           0
-#define ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS                     0x45000
-#define ADRASTEA_RTC_SOC_REG_BASE_ADDRESS                      0x113000
-#define ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS               0x85000
-#define ADRASTEA_SI_REG_BASE_ADDRESS                           0x84000
-#define ADRASTEA_SOC_CORE_REG_BASE_ADDRESS                     0x113000
-#define ADRASTEA_CE_WRAPPER_REG_CSR_BASE_ADDRESS               0xC000
-#define ADRASTEA_MAC_WIFICMN_REG_BASE_ADDRESS                  MISSING
-
-/* Base Addresses */
-#define ADRASTEA_RTC_SOC_BASE_ADDRESS                   0x00000000
-#define ADRASTEA_RTC_WMAC_BASE_ADDRESS                  0x00000000
-#define ADRASTEA_MAC_COEX_BASE_ADDRESS                  0x0000f000
-#define ADRASTEA_BT_COEX_BASE_ADDRESS                   0x00002000
-#define ADRASTEA_SOC_PCIE_BASE_ADDRESS                  0x00130000
-#define ADRASTEA_SOC_CORE_BASE_ADDRESS                  0x00000000
-#define ADRASTEA_WLAN_UART_BASE_ADDRESS                 0x00111000
-#define ADRASTEA_WLAN_SI_BASE_ADDRESS                   0x00010000
-#define ADRASTEA_WLAN_GPIO_BASE_ADDRESS                 0x00000000
-#define ADRASTEA_WLAN_ANALOG_INTF_BASE_ADDRESS          0x00000000
-#define ADRASTEA_WLAN_MAC_BASE_ADDRESS                  0x00000000
-#define ADRASTEA_EFUSE_BASE_ADDRESS                     0x00024000
-#define ADRASTEA_FPGA_REG_BASE_ADDRESS                  0x00039000
-#define ADRASTEA_WLAN_UART2_BASE_ADDRESS                0x00054c00
-
-#define ADRASTEA_CE_WRAPPER_BASE_ADDRESS \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY
-#define ADRASTEA_CE0_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW
-#define ADRASTEA_CE1_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW
-#define ADRASTEA_CE2_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW
-#define ADRASTEA_CE3_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW
-#define ADRASTEA_CE4_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW
-#define ADRASTEA_CE5_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW
-#define ADRASTEA_CE6_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW
-#define ADRASTEA_CE7_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW
-#define ADRASTEA_CE8_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW
-#define ADRASTEA_CE9_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW
-#define ADRASTEA_CE10_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW
-#define ADRASTEA_CE11_BASE_ADDRESS \
-			ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW
-
-#define ADRASTEA_A_SOC_PCIE_SOC_PCIE_REG                MISSING
-#define ADRASTEA_DBI_BASE_ADDRESS                       MISSING
-#define ADRASTEA_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS     MISSING
-#define ADRASTEA_WIFICMN_BASE_ADDRESS                   MISSING
-#define ADRASTEA_BOARD_DATA_SZ                          MISSING
-#define ADRASTEA_BOARD_EXT_DATA_SZ                      MISSING
-#define ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START		MISSING
-#define ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS           MISSING
-#define ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER            MISSING
-#define ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK          MISSING
-#define ADRASTEA_SCRATCH_3_ADDRESS                      MISSING
-#define ADRASTEA_TARG_DRAM_START                        0x00400000
-#define ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET                0x000000c0
-#define ADRASTEA_SOC_RESET_CONTROL_OFFSET \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
-#define ADRASTEA_SOC_CLOCK_CONTROL_OFFSET \
-	(0x00000028 + _RTC_SOC_REG_BASE_ADDRESS)
-#define ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK         0x00000001
-#define ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK         0x00000001
-#define ADRASTEA_WLAN_GPIO_PIN0_ADDRESS \
-	(0x50 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_GPIO_PIN1_ADDRESS \
-	(0x54 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK             0x00007800
-#define ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK             0x00007800
-#define ADRASTEA_SOC_CPU_CLOCK_OFFSET                   0x00000020
-#define ADRASTEA_SOC_LPO_CAL_OFFSET \
-	(0xe0 + _RTC_SOC_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_GPIO_PIN10_ADDRESS \
-	(0x78 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_GPIO_PIN11_ADDRESS \
-	(0x7c + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_GPIO_PIN12_ADDRESS \
-	(0x80 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_GPIO_PIN13_ADDRESS \
-	(0x84 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB             0
-#define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK            0x00000003
-#define ADRASTEA_SOC_LPO_CAL_ENABLE_LSB                 20
-#define ADRASTEA_SOC_LPO_CAL_ENABLE_MASK                0x00100000
-
-#define ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB          0
-#define ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK         0x00000001
-#define ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK       0x00000002
-#define ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK       0x00000001
-#define ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB            18
-#define ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK           0x00040000
-#define ADRASTEA_SI_CONFIG_I2C_LSB                      16
-#define ADRASTEA_SI_CONFIG_I2C_MASK                     0x00010000
-#define ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB               7
-#define ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK              0x00000080
-#define ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB             4
-#define ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK            0x00000010
-#define ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB            5
-#define ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK           0x00000020
-#define ADRASTEA_SI_CONFIG_DIVIDER_LSB                  0
-#define ADRASTEA_SI_CONFIG_DIVIDER_MASK                 0x0000000f
-#define ADRASTEA_SI_CONFIG_OFFSET    (0x00000000 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_TX_DATA0_OFFSET  (0x00000008 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_TX_DATA1_OFFSET  (0x0000000c + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_RX_DATA0_OFFSET  (0x00000010 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_RX_DATA1_OFFSET  (0x00000014 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_CS_OFFSET        (0x00000004 + _SI_REG_BASE_ADDRESS)
-#define ADRASTEA_SI_CS_DONE_ERR_MASK                    0x00000400
-#define ADRASTEA_SI_CS_DONE_INT_MASK                    0x00000200
-#define ADRASTEA_SI_CS_START_LSB                        8
-#define ADRASTEA_SI_CS_START_MASK                       0x00000100
-#define ADRASTEA_SI_CS_RX_CNT_LSB                       4
-#define ADRASTEA_SI_CS_RX_CNT_MASK                      0x000000f0
-#define ADRASTEA_SI_CS_TX_CNT_LSB                       0
-#define ADRASTEA_SI_CS_TX_CNT_MASK                      0x0000000f
-#define ADRASTEA_CE_COUNT                               12
-#define ADRASTEA_SR_WR_INDEX_OFFSET   (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX \
-						- ADRASTEA_CE0_BASE_ADDRESS)
-#define ADRASTEA_DST_WATERMARK_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK \
-						- ADRASTEA_CE0_BASE_ADDRESS)
-#define ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB           14
-#define ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK          0x00004000
-#define ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB            16
-#define ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK           0x0fff0000
-#define ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB           0
-#define ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK          0x0000ffff
-#define ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB    16
-#define ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK   0xffff0000
-#define ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB            15
-#define ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK           0x00008000
-#define ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB         2
-#define ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK        0x00000004
-#define ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB            13
-#define ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK           0x00002000
-#define ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK    0x08000000
-#define ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB    16
-#define ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK   0x00ff0000
-#define ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB        0
-#define ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK       0x00003fff
-
-#define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET    0x00000008
-#define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB       8
-#define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK      0x00000300
-#define ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB          13
-#define ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK         0x00002000
-#define ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK          0x00000400
-#define ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK          0x80000000
-#define ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK     0x00040000
-
-#define ADRASTEA_DST_WR_INDEX_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX\
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_SRC_WATERMARK_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK\
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_SRC_WATERMARK_LOW_MASK                      0xffff0000
-#define ADRASTEA_SRC_WATERMARK_HIGH_MASK                     0x0000ffff
-#define ADRASTEA_DST_WATERMARK_LOW_MASK                      0xffff0000
-#define ADRASTEA_DST_WATERMARK_HIGH_MASK                     0x0000ffff
-
-#define ADRASTEA_CURRENT_SRRI_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI\
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_CURRENT_DRRI_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI\
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK        0x00000002
-#define ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___M
-
-#define ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___M
-
-#define ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___M
-
-#define ADRASTEA_HOST_IS_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS \
-				- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_MISC_IS_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS \
-				- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_HOST_IS_COPY_COMPLETE_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___M
-
-#define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET \
-	(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY\
-	- ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
-
-/*
- * Base address where the CE source and destination ring read
- * indices are written to be viewed by host.
- */
-
-#define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW \
-	(A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW\
-	- ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
-
-#define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH \
-	(A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH - ADRASTEA_CE_WRAPPER_BASE_ADDRESS)
-
-#define ADRASTEA_HOST_IE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE\
-				- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_HOST_IE_COPY_COMPLETE_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___M
-
-#define ADRASTEA_SR_BA_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW\
-				- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_SR_BA_ADDRESS_HIGH_OFFSET \
-				(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH \
-				- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_SR_SIZE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE \
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_CE_CTRL1_OFFSET   (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1 \
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___M
-
-#define ADRASTEA_DR_BA_OFFSET       (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW\
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_DR_BA_ADDRESS_HIGH_OFFSET  (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH\
-						- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_DR_SIZE_OFFSET     (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE\
-					- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_CE_CMD_REGISTER_OFFSET     (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD\
-						- ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_MISC_IE_OFFSET \
-	(ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE - ADRASTEA_CE0_BASE_ADDRESS)
-
-#define ADRASTEA_MISC_IS_AXI_ERR_MASK 0x00000100
-
-#define ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK                   0x00000200
-
-#define ADRASTEA_MISC_IS_AXI_TIMEOUT_ERR \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___M
-
-#define ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___M
-
-#define ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK\
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___M
-
-#define ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___M
-
-#define ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___M
-
-#define ADRASTEA_SRC_WATERMARK_LOW_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___S
-
-#define ADRASTEA_SRC_WATERMARK_HIGH_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___S
-
-#define ADRASTEA_DST_WATERMARK_LOW_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___S
-
-#define ADRASTEA_DST_WATERMARK_HIGH_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___S
-
-#define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___M
-
-#define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___S
-
-#define ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___S
-
-#define ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___M
-
-#define ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___M
-
-#define ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___S
-
-#define ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
-	ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___S
-
-#define ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK  0x0000004
-#define ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB   2
-#define ADRASTEA_SOC_GLOBAL_RESET_ADDRESS \
-	(0x0008 + ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS)
-#define ADRASTEA_RTC_STATE_ADDRESS \
-	(0x0000 + ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS)
-#define ADRASTEA_RTC_STATE_COLD_RESET_MASK                   0x400
-
-#define ADRASTEA_PCIE_SOC_WAKE_RESET                         0x00000000
-#define ADRASTEA_PCIE_SOC_WAKE_ADDRESS                       (ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE)
-#define ADRASTEA_PCIE_SOC_WAKE_V_MASK                        0x00000001
-
-#define ADRASTEA_RTC_STATE_V_MASK                            0x00000007
-#define ADRASTEA_RTC_STATE_V_LSB                             0
-#define ADRASTEA_RTC_STATE_V_ON                              5
-#define ADRASTEA_PCIE_LOCAL_BASE_ADDRESS                     0x0
-#define ADRASTEA_FW_IND_EVENT_PENDING                        1
-#define ADRASTEA_FW_IND_INITIALIZED                          2
-#define ADRASTEA_FW_IND_HELPER                               4
-
-#define ADRASTEA_PCIE_INTR_FIRMWARE_MASK                     0x00000000
-#define ADRASTEA_PCIE_INTR_CE0_MASK                          0x00000100
-#define ADRASTEA_PCIE_INTR_CE_MASK_ALL                       0x00001ffe
-
-#define ADRASTEA_CPU_INTR_ADDRESS                            0xffffffff
-#define ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS               0xffffffff
-#define ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK           0xffffffff
-#define ADRASTEA_SOC_RESET_CONTROL_ADDRESS \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
-#define ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK            0x0100
-#define ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
-#define ADRASTEA_CORE_CTRL_ADDRESS        (0x0000 + _SOC_CORE_REG_BASE_ADDRESS)
-#define ADRASTEA_CORE_CTRL_CPU_INTR_MASK                  0x00002000
-#define ADRASTEA_LOCAL_SCRATCH_OFFSET                     0x00000018
-#define ADRASTEA_CLOCK_GPIO_OFFSET                        0xffffffff
-#define ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
-#define ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
-#define ADRASTEA_SOC_CHIP_ID_ADDRESS                      0x000000f0
-#define ADRASTEA_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
-#define ADRASTEA_SOC_CHIP_ID_VERSION_LSB                  18
-#define ADRASTEA_SOC_CHIP_ID_REVISION_MASK                0x00000f00
-#define ADRASTEA_SOC_CHIP_ID_REVISION_LSB                 8
-#define ADRASTEA_SOC_POWER_REG_OFFSET                     0x0000010c
-
-/* Copy Engine Debug */
-#define ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
-#define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
-#define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
-#define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
-#define ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
-#define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
-#define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
-#define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
-#define ADRASTEA_WLAN_DEBUG_OUT_OFFSET                    0x00000110
-#define ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB                  19
-#define ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB                  0
-#define ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
-#define ADRASTEA_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
-#define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
-#define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
-#define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
-#define ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB                   4
-#define ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB                   0
-#define ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
-#define ADRASTEA_CE_WRAPPER_DEBUG_OFFSET                  0x0008
-#define ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB                 4
-#define ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB                 0
-#define ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK                0x0000001f
-#define ADRASTEA_CE_DEBUG_OFFSET                          0x0054
-#define ADRASTEA_CE_DEBUG_SEL_MSB                         5
-#define ADRASTEA_CE_DEBUG_SEL_LSB                         0
-#define ADRASTEA_CE_DEBUG_SEL_MASK                        0x0000003f
-/* End */
-
-/* PLL start */
-#define ADRASTEA_EFUSE_OFFSET                             0x0000032c
-#define ADRASTEA_EFUSE_XTAL_SEL_MSB                       10
-#define ADRASTEA_EFUSE_XTAL_SEL_LSB                       8
-#define ADRASTEA_EFUSE_XTAL_SEL_MASK                      0x00000700
-#define ADRASTEA_BB_PLL_CONFIG_OFFSET                     0x000002f4
-#define ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB                 20
-#define ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB                 18
-#define ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
-#define ADRASTEA_BB_PLL_CONFIG_FRAC_MSB                   17
-#define ADRASTEA_BB_PLL_CONFIG_FRAC_LSB                   0
-#define ADRASTEA_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
-#define ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB                 10
-#define ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB                 0
-#define ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
-#define ADRASTEA_WLAN_PLL_SETTLE_OFFSET                   0x0018
-#define ADRASTEA_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
-#define ADRASTEA_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
-#define ADRASTEA_WLAN_PLL_SETTLE_RESET                    0x00000400
-#define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB               18
-#define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB               18
-#define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
-#define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB              16
-#define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB              16
-#define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
-#define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
-#define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
-#define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
-#define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
-#define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
-#define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB              13
-#define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB              10
-#define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
-#define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
-#define ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB                 9
-#define ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB                 0
-#define ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
-#define ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET               0x11
-#define ADRASTEA_WLAN_PLL_CONTROL_OFFSET                  0x0014
-#define ADRASTEA_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
-#define ADRASTEA_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
-#define ADRASTEA_WLAN_PLL_CONTROL_RESET                   0x00010011
-#define ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
-#define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB                2
-#define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB                0
-#define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
-#define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
-#define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
-#define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
-#define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
-#define ADRASTEA_RTC_SYNC_STATUS_OFFSET                   0x0244
-#define ADRASTEA_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB               1
-#define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-/* PLL end */
-
-#define ADRASTEA_PCIE_INTR_CE_MASK(n) (ADRASTEA_PCIE_INTR_CE0_MASK << (n))
-#define ADRASTEA_DRAM_BASE_ADDRESS     ADRASTEA_TARG_DRAM_START
-#define ADRASTEA_FW_INDICATOR_ADDRESS \
-	(ADRASTEA_WIFICMN_BASE_ADDRESS + ADRASTEA_SCRATCH_3_ADDRESS)
-#define ADRASTEA_SYSTEM_SLEEP_OFFSET       ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET
-#define ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET  (0x002c + _WIFI_RTC_REG_BASE_ADDRESS)
-#define ADRASTEA_WLAN_RESET_CONTROL_OFFSET (0x0000 + _WIFI_RTC_REG_BASE_ADDRESS)
-#define ADRASTEA_CLOCK_CONTROL_OFFSET      ADRASTEA_SOC_CLOCK_CONTROL_OFFSET
-#define ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK \
-	ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK
-#define ADRASTEA_RESET_CONTROL_MBOX_RST_MASK 0x00000004
-#define ADRASTEA_RESET_CONTROL_SI0_RST_MASK \
-	ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK
-#define ADRASTEA_GPIO_BASE_ADDRESS         ADRASTEA_WLAN_GPIO_BASE_ADDRESS
-#define ADRASTEA_GPIO_PIN0_OFFSET          ADRASTEA_WLAN_GPIO_PIN0_ADDRESS
-#define ADRASTEA_GPIO_PIN1_OFFSET          ADRASTEA_WLAN_GPIO_PIN1_ADDRESS
-#define ADRASTEA_GPIO_PIN0_CONFIG_MASK     ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK
-#define ADRASTEA_GPIO_PIN1_CONFIG_MASK     ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK
-#define ADRASTEA_SI_BASE_ADDRESS           0x00000000
-#define ADRASTEA_CPU_CLOCK_OFFSET          (0x20 + _RTC_SOC_REG_BASE_ADDRESS)
-#define ADRASTEA_LPO_CAL_OFFSET            ADRASTEA_SOC_LPO_CAL_OFFSET
-#define ADRASTEA_GPIO_PIN10_OFFSET         ADRASTEA_WLAN_GPIO_PIN10_ADDRESS
-#define ADRASTEA_GPIO_PIN11_OFFSET         ADRASTEA_WLAN_GPIO_PIN11_ADDRESS
-#define ADRASTEA_GPIO_PIN12_OFFSET         ADRASTEA_WLAN_GPIO_PIN12_ADDRESS
-#define ADRASTEA_GPIO_PIN13_OFFSET         ADRASTEA_WLAN_GPIO_PIN13_ADDRESS
-#define ADRASTEA_CPU_CLOCK_STANDARD_LSB    0
-#define ADRASTEA_CPU_CLOCK_STANDARD_MASK   0x1
-#define ADRASTEA_LPO_CAL_ENABLE_LSB        ADRASTEA_SOC_LPO_CAL_ENABLE_LSB
-#define ADRASTEA_LPO_CAL_ENABLE_MASK       ADRASTEA_SOC_LPO_CAL_ENABLE_MASK
-#define ADRASTEA_ANALOG_INTF_BASE_ADDRESS  ADRASTEA_WLAN_ANALOG_INTF_BASE_ADDRESS
-#define ADRASTEA_MBOX_BASE_ADDRESS         0x00008000
-#define ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB              MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK            MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_CPU_LSB               MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_CPU_MASK              MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB           MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK          MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
-#define ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
-#define ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
-#define ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
-#define ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
-#define ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
-#define ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
-#define ADRASTEA_INT_STATUS_ENABLE_ADDRESS               MISSING
-#define ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
-#define ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
-#define ADRASTEA_HOST_INT_STATUS_ADDRESS                 MISSING
-#define ADRASTEA_CPU_INT_STATUS_ADDRESS                  MISSING
-#define ADRASTEA_ERROR_INT_STATUS_ADDRESS                MISSING
-#define ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK            MISSING
-#define ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB             MISSING
-#define ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
-#define ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
-#define ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
-#define ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
-#define ADRASTEA_COUNT_DEC_ADDRESS                       MISSING
-#define ADRASTEA_HOST_INT_STATUS_CPU_MASK                MISSING
-#define ADRASTEA_HOST_INT_STATUS_CPU_LSB                 MISSING
-#define ADRASTEA_HOST_INT_STATUS_ERROR_MASK              MISSING
-#define ADRASTEA_HOST_INT_STATUS_ERROR_LSB               MISSING
-#define ADRASTEA_HOST_INT_STATUS_COUNTER_MASK            MISSING
-#define ADRASTEA_HOST_INT_STATUS_COUNTER_LSB             MISSING
-#define ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS              MISSING
-#define ADRASTEA_WINDOW_DATA_ADDRESS                     MISSING
-#define ADRASTEA_WINDOW_READ_ADDR_ADDRESS                MISSING
-#define ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS               MISSING
-
-/* Shadow Registers - Start */
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22
-#define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23
-
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22
-#define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23 \
-					ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23
-
-/* Q6 iHelium emulation registers */
-#define ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1	0x00113018
-#define ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER		0x00113184
-#define ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1		0x00113020
-#define ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1	0x00113010
-#define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0		0x00130040
-#define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1		0x00130044
-
-#define ADRASTEA_HOST_ENABLE_REGISTER    0x00188000
-#define ADRASTEA_Q6_ENABLE_REGISTER_0    0x00188004
-#define ADRASTEA_Q6_ENABLE_REGISTER_1    0x00188008
-#define ADRASTEA_HOST_CAUSE_REGISTER     0x0018800c
-#define ADRASTEA_Q6_CAUSE_REGISTER_0     0x00188010
-#define ADRASTEA_Q6_CAUSE_REGISTER_1     0x00188014
-#define ADRASTEA_HOST_CLEAR_REGISTER     0x00188018
-#define ADRASTEA_Q6_CLEAR_REGISTER_0     0x0018801c
-#define ADRASTEA_Q6_CLEAR_REGISTER_1     0x00188020
-
-#define ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA	0x08
-#define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2			0x0013005C
-#define ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK        0x0
-/* end: Q6 iHelium emulation registers */
-
-struct targetdef_s adrastea_targetdef = {
-	.d_RTC_SOC_BASE_ADDRESS = ADRASTEA_RTC_SOC_BASE_ADDRESS,
-	.d_RTC_WMAC_BASE_ADDRESS = ADRASTEA_RTC_WMAC_BASE_ADDRESS,
-	.d_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
-	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
-	ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
-	.d_CLOCK_CONTROL_OFFSET = ADRASTEA_CLOCK_CONTROL_OFFSET,
-	.d_CLOCK_CONTROL_SI0_CLK_MASK = ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK,
-	.d_RESET_CONTROL_OFFSET = ADRASTEA_SOC_RESET_CONTROL_OFFSET,
-	.d_RESET_CONTROL_MBOX_RST_MASK = ADRASTEA_RESET_CONTROL_MBOX_RST_MASK,
-	.d_RESET_CONTROL_SI0_RST_MASK = ADRASTEA_RESET_CONTROL_SI0_RST_MASK,
-	.d_WLAN_RESET_CONTROL_OFFSET = ADRASTEA_WLAN_RESET_CONTROL_OFFSET,
-	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
-	ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK,
-	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
-	ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK,
-	.d_GPIO_BASE_ADDRESS = ADRASTEA_GPIO_BASE_ADDRESS,
-	.d_GPIO_PIN0_OFFSET = ADRASTEA_GPIO_PIN0_OFFSET,
-	.d_GPIO_PIN1_OFFSET = ADRASTEA_GPIO_PIN1_OFFSET,
-	.d_GPIO_PIN0_CONFIG_MASK = ADRASTEA_GPIO_PIN0_CONFIG_MASK,
-	.d_GPIO_PIN1_CONFIG_MASK = ADRASTEA_GPIO_PIN1_CONFIG_MASK,
-	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB,
-	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK,
-	.d_SI_CONFIG_I2C_LSB = ADRASTEA_SI_CONFIG_I2C_LSB,
-	.d_SI_CONFIG_I2C_MASK = ADRASTEA_SI_CONFIG_I2C_MASK,
-	.d_SI_CONFIG_POS_SAMPLE_LSB = ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB,
-	.d_SI_CONFIG_POS_SAMPLE_MASK = ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK,
-	.d_SI_CONFIG_INACTIVE_CLK_LSB = ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB,
-	.d_SI_CONFIG_INACTIVE_CLK_MASK = ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK,
-	.d_SI_CONFIG_INACTIVE_DATA_LSB = ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB,
-	.d_SI_CONFIG_INACTIVE_DATA_MASK = ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK,
-	.d_SI_CONFIG_DIVIDER_LSB = ADRASTEA_SI_CONFIG_DIVIDER_LSB,
-	.d_SI_CONFIG_DIVIDER_MASK = ADRASTEA_SI_CONFIG_DIVIDER_MASK,
-	.d_SI_BASE_ADDRESS = ADRASTEA_SI_BASE_ADDRESS,
-	.d_SI_CONFIG_OFFSET = ADRASTEA_SI_CONFIG_OFFSET,
-	.d_SI_TX_DATA0_OFFSET = ADRASTEA_SI_TX_DATA0_OFFSET,
-	.d_SI_TX_DATA1_OFFSET = ADRASTEA_SI_TX_DATA1_OFFSET,
-	.d_SI_RX_DATA0_OFFSET = ADRASTEA_SI_RX_DATA0_OFFSET,
-	.d_SI_RX_DATA1_OFFSET = ADRASTEA_SI_RX_DATA1_OFFSET,
-	.d_SI_CS_OFFSET = ADRASTEA_SI_CS_OFFSET,
-	.d_SI_CS_DONE_ERR_MASK = ADRASTEA_SI_CS_DONE_ERR_MASK,
-	.d_SI_CS_DONE_INT_MASK = ADRASTEA_SI_CS_DONE_INT_MASK,
-	.d_SI_CS_START_LSB = ADRASTEA_SI_CS_START_LSB,
-	.d_SI_CS_START_MASK = ADRASTEA_SI_CS_START_MASK,
-	.d_SI_CS_RX_CNT_LSB = ADRASTEA_SI_CS_RX_CNT_LSB,
-	.d_SI_CS_RX_CNT_MASK = ADRASTEA_SI_CS_RX_CNT_MASK,
-	.d_SI_CS_TX_CNT_LSB = ADRASTEA_SI_CS_TX_CNT_LSB,
-	.d_SI_CS_TX_CNT_MASK = ADRASTEA_SI_CS_TX_CNT_MASK,
-	.d_BOARD_DATA_SZ = ADRASTEA_BOARD_DATA_SZ,
-	.d_BOARD_EXT_DATA_SZ = ADRASTEA_BOARD_EXT_DATA_SZ,
-	.d_MBOX_BASE_ADDRESS = ADRASTEA_MBOX_BASE_ADDRESS,
-	.d_LOCAL_SCRATCH_OFFSET = ADRASTEA_LOCAL_SCRATCH_OFFSET,
-	.d_CPU_CLOCK_OFFSET = ADRASTEA_CPU_CLOCK_OFFSET,
-	.d_LPO_CAL_OFFSET = ADRASTEA_LPO_CAL_OFFSET,
-	.d_GPIO_PIN10_OFFSET = ADRASTEA_GPIO_PIN10_OFFSET,
-	.d_GPIO_PIN11_OFFSET = ADRASTEA_GPIO_PIN11_OFFSET,
-	.d_GPIO_PIN12_OFFSET = ADRASTEA_GPIO_PIN12_OFFSET,
-	.d_GPIO_PIN13_OFFSET = ADRASTEA_GPIO_PIN13_OFFSET,
-	.d_CLOCK_GPIO_OFFSET = ADRASTEA_CLOCK_GPIO_OFFSET,
-	.d_CPU_CLOCK_STANDARD_LSB = ADRASTEA_CPU_CLOCK_STANDARD_LSB,
-	.d_CPU_CLOCK_STANDARD_MASK = ADRASTEA_CPU_CLOCK_STANDARD_MASK,
-	.d_LPO_CAL_ENABLE_LSB = ADRASTEA_LPO_CAL_ENABLE_LSB,
-	.d_LPO_CAL_ENABLE_MASK = ADRASTEA_LPO_CAL_ENABLE_MASK,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
-		ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
-	.d_ANALOG_INTF_BASE_ADDRESS = ADRASTEA_ANALOG_INTF_BASE_ADDRESS,
-	.d_WLAN_MAC_BASE_ADDRESS = ADRASTEA_WLAN_MAC_BASE_ADDRESS,
-	.d_FW_INDICATOR_ADDRESS = ADRASTEA_FW_INDICATOR_ADDRESS,
-	.d_DRAM_BASE_ADDRESS = ADRASTEA_DRAM_BASE_ADDRESS,
-	.d_SOC_CORE_BASE_ADDRESS = ADRASTEA_SOC_CORE_BASE_ADDRESS,
-	.d_CORE_CTRL_ADDRESS = ADRASTEA_CORE_CTRL_ADDRESS,
-	.d_CE_COUNT = ADRASTEA_CE_COUNT,
-	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
-	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
-	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
-	.d_PCIE_INTR_ENABLE_ADDRESS = ADRASTEA_HOST_ENABLE_REGISTER,
-	.d_PCIE_INTR_CLR_ADDRESS = ADRASTEA_HOST_CLEAR_REGISTER,
-	.d_PCIE_INTR_FIRMWARE_MASK = ADRASTEA_PCIE_INTR_FIRMWARE_MASK,
-	.d_PCIE_INTR_CE_MASK_ALL = ADRASTEA_PCIE_INTR_CE_MASK_ALL,
-	.d_CORE_CTRL_CPU_INTR_MASK = ADRASTEA_CORE_CTRL_CPU_INTR_MASK,
-	.d_SR_WR_INDEX_ADDRESS = ADRASTEA_SR_WR_INDEX_OFFSET,
-	.d_DST_WATERMARK_ADDRESS = ADRASTEA_DST_WATERMARK_OFFSET,
-	/* htt_rx.c */
-	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
-	ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK,
-	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB,
-	.d_RX_MPDU_START_0_SEQ_NUM_MASK = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_LSB = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_LSB = ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_MASK =
-		ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
-		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
-		ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
-	.d_RX_MSDU_END_4_LAST_MSDU_MASK = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK,
-	.d_RX_MSDU_END_4_LAST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB,
-	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
-		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK,
-	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
-		ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB,
-	.d_RX_ATTENTION_0_FRAGMENT_MASK = ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK,
-	.d_RX_ATTENTION_0_FRAGMENT_LSB = ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB,
-	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
-		ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
-		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
-		ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
-		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
-		ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
-		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
-		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
-		ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB,
-	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
-		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK,
-	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
-		ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB,
-	.d_RX_ATTENTION_0_MORE_DATA_MASK =
-		ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK,
-	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
-		ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK,
-	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
-		ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-
-	/* PLL start */
-	.d_EFUSE_OFFSET = ADRASTEA_EFUSE_OFFSET,
-	.d_EFUSE_XTAL_SEL_MSB = ADRASTEA_EFUSE_XTAL_SEL_MSB,
-	.d_EFUSE_XTAL_SEL_LSB = ADRASTEA_EFUSE_XTAL_SEL_LSB,
-	.d_EFUSE_XTAL_SEL_MASK = ADRASTEA_EFUSE_XTAL_SEL_MASK,
-	.d_BB_PLL_CONFIG_OFFSET = ADRASTEA_BB_PLL_CONFIG_OFFSET,
-	.d_BB_PLL_CONFIG_OUTDIV_MSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB,
-	.d_BB_PLL_CONFIG_OUTDIV_LSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB,
-	.d_BB_PLL_CONFIG_OUTDIV_MASK = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK,
-	.d_BB_PLL_CONFIG_FRAC_MSB = ADRASTEA_BB_PLL_CONFIG_FRAC_MSB,
-	.d_BB_PLL_CONFIG_FRAC_LSB = ADRASTEA_BB_PLL_CONFIG_FRAC_LSB,
-	.d_BB_PLL_CONFIG_FRAC_MASK = ADRASTEA_BB_PLL_CONFIG_FRAC_MASK,
-	.d_WLAN_PLL_SETTLE_TIME_MSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB,
-	.d_WLAN_PLL_SETTLE_TIME_LSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB,
-	.d_WLAN_PLL_SETTLE_TIME_MASK = ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK,
-	.d_WLAN_PLL_SETTLE_OFFSET = ADRASTEA_WLAN_PLL_SETTLE_OFFSET,
-	.d_WLAN_PLL_SETTLE_SW_MASK = ADRASTEA_WLAN_PLL_SETTLE_SW_MASK,
-	.d_WLAN_PLL_SETTLE_RSTMASK = ADRASTEA_WLAN_PLL_SETTLE_RSTMASK,
-	.d_WLAN_PLL_SETTLE_RESET = ADRASTEA_WLAN_PLL_SETTLE_RESET,
-	.d_WLAN_PLL_CONTROL_NOPWD_MSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_LSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_MASK = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_MSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_LSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_MASK = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
-		ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
-		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
-		ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET,
-	.d_WLAN_PLL_CONTROL_REFDIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK,
-	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
-		ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET,
-	.d_WLAN_PLL_CONTROL_DIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB,
-	.d_WLAN_PLL_CONTROL_DIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB,
-	.d_WLAN_PLL_CONTROL_DIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK,
-	.d_WLAN_PLL_CONTROL_DIV_RESET = ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET,
-	.d_WLAN_PLL_CONTROL_OFFSET = ADRASTEA_WLAN_PLL_CONTROL_OFFSET,
-	.d_WLAN_PLL_CONTROL_SW_MASK = ADRASTEA_WLAN_PLL_CONTROL_SW_MASK,
-	.d_WLAN_PLL_CONTROL_RSTMASK = ADRASTEA_WLAN_PLL_CONTROL_RSTMASK,
-	.d_WLAN_PLL_CONTROL_RESET = ADRASTEA_WLAN_PLL_CONTROL_RESET,
-	.d_SOC_CORE_CLK_CTRL_OFFSET = ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET,
-	.d_SOC_CORE_CLK_CTRL_DIV_MSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_LSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_MASK = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
-		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
-		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
-		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
-		ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
-	.d_RTC_SYNC_STATUS_OFFSET = ADRASTEA_RTC_SYNC_STATUS_OFFSET,
-	.d_SOC_CPU_CLOCK_OFFSET = ADRASTEA_SOC_CPU_CLOCK_OFFSET,
-	.d_SOC_CPU_CLOCK_STANDARD_MSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB,
-	.d_SOC_CPU_CLOCK_STANDARD_LSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB,
-	.d_SOC_CPU_CLOCK_STANDARD_MASK = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK,
-	/* PLL end */
-	.d_SOC_POWER_REG_OFFSET = ADRASTEA_SOC_POWER_REG_OFFSET,
-	.d_PCIE_INTR_CAUSE_ADDRESS = ADRASTEA_HOST_CAUSE_REGISTER,
-	.d_SOC_RESET_CONTROL_ADDRESS = ADRASTEA_SOC_RESET_CONTROL_ADDRESS,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
-		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
-		ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
-	.d_SOC_RESET_CONTROL_CE_RST_MASK =
-		ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK,
-	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
-		ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
-	.d_CPU_INTR_ADDRESS = ADRASTEA_CPU_INTR_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
-		ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
-		ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
-	/* chip id start */
-	.d_SOC_CHIP_ID_ADDRESS = ADRASTEA_SOC_CHIP_ID_ADDRESS,
-	.d_SOC_CHIP_ID_VERSION_MASK = ADRASTEA_SOC_CHIP_ID_VERSION_MASK,
-	.d_SOC_CHIP_ID_VERSION_LSB = ADRASTEA_SOC_CHIP_ID_VERSION_LSB,
-	.d_SOC_CHIP_ID_REVISION_MASK = ADRASTEA_SOC_CHIP_ID_REVISION_MASK,
-	.d_SOC_CHIP_ID_REVISION_LSB = ADRASTEA_SOC_CHIP_ID_REVISION_LSB,
-	/* chip id end */
-	.d_A_SOC_CORE_SCRATCH_0_ADDRESS = ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS,
-	.d_A_SOC_CORE_SPARE_0_REGISTER = ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER,
-	.d_PCIE_INTR_FIRMWARE_ROUTE_MASK =
-		ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK,
-	.d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 =
-		ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1,
-	.d_A_SOC_CORE_SPARE_1_REGISTER =
-		ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER,
-	.d_A_SOC_CORE_PCIE_INTR_CLR_GRP1 =
-		ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1,
-	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 =
-		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_0 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_1 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1,
-	.d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA =
-		ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_2 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2,
-	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK =
-		ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK,
-	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
-		ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
-	.d_WLAN_DEBUG_CONTROL_OFFSET = ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
-		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
-		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
-		ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK,
-	.d_WLAN_DEBUG_OUT_OFFSET = ADRASTEA_WLAN_DEBUG_OUT_OFFSET,
-	.d_WLAN_DEBUG_OUT_DATA_MSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB,
-	.d_WLAN_DEBUG_OUT_DATA_LSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB,
-	.d_WLAN_DEBUG_OUT_DATA_MASK = ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK,
-	.d_AMBA_DEBUG_BUS_OFFSET = ADRASTEA_AMBA_DEBUG_BUS_OFFSET,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
-		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
-		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
-		ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
-	.d_AMBA_DEBUG_BUS_SEL_MSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_SEL_LSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_SEL_MASK = ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK,
-
-#ifdef QCA_WIFI_3_0_ADRASTEA
-	.d_Q6_ENABLE_REGISTER_0 = ADRASTEA_Q6_ENABLE_REGISTER_0,
-	.d_Q6_ENABLE_REGISTER_1 = ADRASTEA_Q6_ENABLE_REGISTER_1,
-	.d_Q6_CAUSE_REGISTER_0 = ADRASTEA_Q6_CAUSE_REGISTER_0,
-	.d_Q6_CAUSE_REGISTER_1 = ADRASTEA_Q6_CAUSE_REGISTER_1,
-	.d_Q6_CLEAR_REGISTER_0 = ADRASTEA_Q6_CLEAR_REGISTER_0,
-	.d_Q6_CLEAR_REGISTER_1 = ADRASTEA_Q6_CLEAR_REGISTER_1,
-#endif
-};
-
-struct hostdef_s adrastea_hostdef = {
-	.d_INT_STATUS_ENABLE_ERROR_LSB = ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB,
-	.d_INT_STATUS_ENABLE_ERROR_MASK = ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK,
-	.d_INT_STATUS_ENABLE_CPU_LSB = ADRASTEA_INT_STATUS_ENABLE_CPU_LSB,
-	.d_INT_STATUS_ENABLE_CPU_MASK = ADRASTEA_INT_STATUS_ENABLE_CPU_MASK,
-	.d_INT_STATUS_ENABLE_COUNTER_LSB =
-		ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB,
-	.d_INT_STATUS_ENABLE_COUNTER_MASK =
-		ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
-		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
-		ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
-		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
-		ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
-		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
-		ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
-		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
-		ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
-	.d_INT_STATUS_ENABLE_ADDRESS = ADRASTEA_INT_STATUS_ENABLE_ADDRESS,
-	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
-		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB,
-	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
-		ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK,
-	.d_HOST_INT_STATUS_ADDRESS = ADRASTEA_HOST_INT_STATUS_ADDRESS,
-	.d_CPU_INT_STATUS_ADDRESS = ADRASTEA_CPU_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_ADDRESS = ADRASTEA_ERROR_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_WAKEUP_MASK = ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK,
-	.d_ERROR_INT_STATUS_WAKEUP_LSB = ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
-		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
-		ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
-		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
-		ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
-	.d_COUNT_DEC_ADDRESS = ADRASTEA_COUNT_DEC_ADDRESS,
-	.d_HOST_INT_STATUS_CPU_MASK = ADRASTEA_HOST_INT_STATUS_CPU_MASK,
-	.d_HOST_INT_STATUS_CPU_LSB = ADRASTEA_HOST_INT_STATUS_CPU_LSB,
-	.d_HOST_INT_STATUS_ERROR_MASK = ADRASTEA_HOST_INT_STATUS_ERROR_MASK,
-	.d_HOST_INT_STATUS_ERROR_LSB = ADRASTEA_HOST_INT_STATUS_ERROR_LSB,
-	.d_HOST_INT_STATUS_COUNTER_MASK = ADRASTEA_HOST_INT_STATUS_COUNTER_MASK,
-	.d_HOST_INT_STATUS_COUNTER_LSB = ADRASTEA_HOST_INT_STATUS_COUNTER_LSB,
-	.d_RX_LOOKAHEAD_VALID_ADDRESS = ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS,
-	.d_WINDOW_DATA_ADDRESS = ADRASTEA_WINDOW_DATA_ADDRESS,
-	.d_WINDOW_READ_ADDR_ADDRESS = ADRASTEA_WINDOW_READ_ADDR_ADDRESS,
-	.d_WINDOW_WRITE_ADDR_ADDRESS = ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS,
-	.d_SOC_GLOBAL_RESET_ADDRESS = ADRASTEA_SOC_GLOBAL_RESET_ADDRESS,
-	.d_RTC_STATE_ADDRESS = ADRASTEA_RTC_STATE_ADDRESS,
-	.d_RTC_STATE_COLD_RESET_MASK = ADRASTEA_RTC_STATE_COLD_RESET_MASK,
-	.d_PCIE_LOCAL_BASE_ADDRESS = ADRASTEA_PCIE_LOCAL_BASE_ADDRESS,
-	.d_PCIE_SOC_WAKE_RESET = ADRASTEA_PCIE_SOC_WAKE_RESET,
-	.d_PCIE_SOC_WAKE_ADDRESS = ADRASTEA_PCIE_SOC_WAKE_ADDRESS,
-	.d_PCIE_SOC_WAKE_V_MASK = ADRASTEA_PCIE_SOC_WAKE_V_MASK,
-	.d_RTC_STATE_V_MASK = ADRASTEA_RTC_STATE_V_MASK,
-	.d_RTC_STATE_V_LSB = ADRASTEA_RTC_STATE_V_LSB,
-	.d_FW_IND_EVENT_PENDING = ADRASTEA_FW_IND_EVENT_PENDING,
-	.d_FW_IND_INITIALIZED = ADRASTEA_FW_IND_INITIALIZED,
-	.d_FW_IND_HELPER = ADRASTEA_FW_IND_HELPER,
-	.d_RTC_STATE_V_ON = ADRASTEA_RTC_STATE_V_ON,
-#if defined(SDIO_3_0)
-	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
-		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_MASK,
-	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
-		ADRASTEA_HOST_INT_STATUS_MBOX_DATA_LSB,
-#endif
-	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
-	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
-	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
-	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
-	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
-	.d_HOST_CE_COUNT = ADRASTEA_CE_COUNT,
-	.d_ENABLE_MSI = 0,
-	.d_MUX_ID_MASK = 0xf000,
-	.d_TRANSACTION_ID_MASK = 0x0fff,
-	.d_DESC_DATA_FLAG_MASK = 0x1FFFE3E0,
-	.d_A_SOC_PCIE_PCIE_BAR0_START = ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START,
-};
-
-
-struct ce_reg_def adrastea_ce_targetdef = {
-	/* copy_engine.c  */
-	.d_DST_WR_INDEX_ADDRESS = ADRASTEA_DST_WR_INDEX_OFFSET,
-	.d_SRC_WATERMARK_ADDRESS = ADRASTEA_SRC_WATERMARK_OFFSET,
-	.d_SRC_WATERMARK_LOW_MASK = ADRASTEA_SRC_WATERMARK_LOW_MASK,
-	.d_SRC_WATERMARK_HIGH_MASK = ADRASTEA_SRC_WATERMARK_HIGH_MASK,
-	.d_DST_WATERMARK_LOW_MASK = ADRASTEA_DST_WATERMARK_LOW_MASK,
-	.d_DST_WATERMARK_HIGH_MASK = ADRASTEA_DST_WATERMARK_HIGH_MASK,
-	.d_CURRENT_SRRI_ADDRESS = ADRASTEA_CURRENT_SRRI_OFFSET,
-	.d_CURRENT_DRRI_ADDRESS = ADRASTEA_CURRENT_DRRI_OFFSET,
-	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
-		ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
-		ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
-		ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
-		ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_ADDRESS = ADRASTEA_HOST_IS_OFFSET,
-	.d_MISC_IS_ADDRESS = ADRASTEA_MISC_IS_OFFSET,
-	.d_HOST_IS_COPY_COMPLETE_MASK = ADRASTEA_HOST_IS_COPY_COMPLETE_MASK,
-	.d_CE_WRAPPER_BASE_ADDRESS = ADRASTEA_CE_WRAPPER_BASE_ADDRESS,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
-		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET,
-	.d_CE_DDR_ADDRESS_FOR_RRI_LOW =
-		ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW,
-	.d_CE_DDR_ADDRESS_FOR_RRI_HIGH =
-		ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH,
-	.d_HOST_IE_ADDRESS = ADRASTEA_HOST_IE_OFFSET,
-	.d_HOST_IE_COPY_COMPLETE_MASK = ADRASTEA_HOST_IE_COPY_COMPLETE_MASK,
-	.d_SR_BA_ADDRESS = ADRASTEA_SR_BA_OFFSET,
-	.d_SR_SIZE_ADDRESS = ADRASTEA_SR_SIZE_OFFSET,
-	.d_CE_CTRL1_ADDRESS = ADRASTEA_CE_CTRL1_OFFSET,
-	.d_CE_CTRL1_DMAX_LENGTH_MASK = ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK,
-	.d_DR_BA_ADDRESS = ADRASTEA_DR_BA_OFFSET,
-	.d_DR_SIZE_ADDRESS = ADRASTEA_DR_SIZE_OFFSET,
-	.d_CE_CMD_REGISTER = ADRASTEA_CE_CMD_REGISTER_OFFSET,
-	.d_CE_MSI_ADDRESS = MISSING_FOR_ADRASTEA,
-	.d_CE_MSI_ADDRESS_HIGH = MISSING_FOR_ADRASTEA,
-	.d_CE_MSI_DATA = MISSING_FOR_ADRASTEA,
-	.d_CE_MSI_ENABLE_BIT = MISSING_FOR_ADRASTEA,
-	.d_MISC_IE_ADDRESS = ADRASTEA_MISC_IE_OFFSET,
-	.d_MISC_IS_AXI_ERR_MASK = ADRASTEA_MISC_IS_AXI_ERR_MASK,
-	.d_MISC_IS_DST_ADDR_ERR_MASK = ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK,
-	.d_MISC_IS_SRC_LEN_ERR_MASK = ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK,
-	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK,
-	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
-		ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK,
-	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
-		ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK,
-	.d_SRC_WATERMARK_LOW_LSB = ADRASTEA_SRC_WATERMARK_LOW_LSB,
-	.d_SRC_WATERMARK_HIGH_LSB = ADRASTEA_SRC_WATERMARK_HIGH_LSB,
-	.d_DST_WATERMARK_LOW_LSB = ADRASTEA_DST_WATERMARK_LOW_LSB,
-	.d_DST_WATERMARK_HIGH_LSB = ADRASTEA_DST_WATERMARK_HIGH_LSB,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
-		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
-		ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
-	.d_CE_CTRL1_DMAX_LENGTH_LSB = ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
-		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
-		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
-		ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
-		ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_CTRL1_IDX_UPD_EN_MASK =
-		ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M,
-	.d_CE_WRAPPER_DEBUG_OFFSET = ADRASTEA_CE_WRAPPER_DEBUG_OFFSET,
-	.d_CE_WRAPPER_DEBUG_SEL_MSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB,
-	.d_CE_WRAPPER_DEBUG_SEL_LSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB,
-	.d_CE_WRAPPER_DEBUG_SEL_MASK = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK,
-	.d_CE_DEBUG_OFFSET = ADRASTEA_CE_DEBUG_OFFSET,
-	.d_CE_DEBUG_SEL_MSB = ADRASTEA_CE_DEBUG_SEL_MSB,
-	.d_CE_DEBUG_SEL_LSB = ADRASTEA_CE_DEBUG_SEL_LSB,
-	.d_CE_DEBUG_SEL_MASK = ADRASTEA_CE_DEBUG_SEL_MASK,
-	.d_CE0_BASE_ADDRESS = ADRASTEA_CE0_BASE_ADDRESS,
-	.d_CE1_BASE_ADDRESS = ADRASTEA_CE1_BASE_ADDRESS,
-	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES =
-		MISSING_FOR_ADRASTEA,
-	.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS =
-		MISSING_FOR_ADRASTEA,
-};
-
-
-struct host_shadow_regs_s adrastea_host_shadow_regs = {
-	.d_A_LOCAL_SHADOW_REG_VALUE_0  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0,
-	.d_A_LOCAL_SHADOW_REG_VALUE_1  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1,
-	.d_A_LOCAL_SHADOW_REG_VALUE_2  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2,
-	.d_A_LOCAL_SHADOW_REG_VALUE_3  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3,
-	.d_A_LOCAL_SHADOW_REG_VALUE_4  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4,
-	.d_A_LOCAL_SHADOW_REG_VALUE_5  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5,
-	.d_A_LOCAL_SHADOW_REG_VALUE_6  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6,
-	.d_A_LOCAL_SHADOW_REG_VALUE_7  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7,
-	.d_A_LOCAL_SHADOW_REG_VALUE_8  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8,
-	.d_A_LOCAL_SHADOW_REG_VALUE_9  =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9,
-	.d_A_LOCAL_SHADOW_REG_VALUE_10 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10,
-	.d_A_LOCAL_SHADOW_REG_VALUE_11 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11,
-	.d_A_LOCAL_SHADOW_REG_VALUE_12 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12,
-	.d_A_LOCAL_SHADOW_REG_VALUE_13 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13,
-	.d_A_LOCAL_SHADOW_REG_VALUE_14 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14,
-	.d_A_LOCAL_SHADOW_REG_VALUE_15 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15,
-	.d_A_LOCAL_SHADOW_REG_VALUE_16 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16,
-	.d_A_LOCAL_SHADOW_REG_VALUE_17 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17,
-	.d_A_LOCAL_SHADOW_REG_VALUE_18 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18,
-	.d_A_LOCAL_SHADOW_REG_VALUE_19 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19,
-	.d_A_LOCAL_SHADOW_REG_VALUE_20 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20,
-	.d_A_LOCAL_SHADOW_REG_VALUE_21 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21,
-	.d_A_LOCAL_SHADOW_REG_VALUE_22 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22,
-	.d_A_LOCAL_SHADOW_REG_VALUE_23 =
-		ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_0  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_1  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_2  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_3  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_4  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_5  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_6  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_7  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_8  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_9  =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_10 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_11 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_12 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_13 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_14 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_15 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_16 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_17 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_18 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_19 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_20 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_21 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_22 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22,
-	.d_A_LOCAL_SHADOW_REG_ADDRESS_23 =
-		 ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23
-};
-
-#endif /* ADRASTEA_REG_DEF_H */

core/hif/src/ar6320def.h

@@ -1,796 +0,0 @@
-/*
- * Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _AR6320DEF_H_
-#define  _AR6320DEF_H_
-
-/* Base Addresses */
-#define AR6320_RTC_SOC_BASE_ADDRESS                     0x00000000
-#define AR6320_RTC_WMAC_BASE_ADDRESS                    0x00001000
-#define AR6320_MAC_COEX_BASE_ADDRESS                    0x0000f000
-#define AR6320_BT_COEX_BASE_ADDRESS                     0x00002000
-#define AR6320_SOC_PCIE_BASE_ADDRESS                    0x00038000
-#define AR6320_SOC_CORE_BASE_ADDRESS                    0x0003a000
-#define AR6320_WLAN_UART_BASE_ADDRESS                   0x0000c000
-#define AR6320_WLAN_SI_BASE_ADDRESS                     0x00010000
-#define AR6320_WLAN_GPIO_BASE_ADDRESS                   0x00005000
-#define AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS            0x00006000
-#define AR6320_WLAN_MAC_BASE_ADDRESS                    0x00010000
-#define AR6320_EFUSE_BASE_ADDRESS                       0x00024000
-#define AR6320_FPGA_REG_BASE_ADDRESS                    0x00039000
-#define AR6320_WLAN_UART2_BASE_ADDRESS                  0x00054c00
-#define AR6320_CE_WRAPPER_BASE_ADDRESS                  0x00034000
-#define AR6320_CE0_BASE_ADDRESS                         0x00034400
-#define AR6320_CE1_BASE_ADDRESS                         0x00034800
-#define AR6320_CE2_BASE_ADDRESS                         0x00034c00
-#define AR6320_CE3_BASE_ADDRESS                         0x00035000
-#define AR6320_CE4_BASE_ADDRESS                         0x00035400
-#define AR6320_CE5_BASE_ADDRESS                         0x00035800
-#define AR6320_CE6_BASE_ADDRESS                         0x00035c00
-#define AR6320_CE7_BASE_ADDRESS                         0x00036000
-#define AR6320_DBI_BASE_ADDRESS                         0x0003c000
-#define AR6320_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS       0x00007800
-
-#define AR6320_SCRATCH_3_ADDRESS                        0x0028
-#define AR6320_TARG_DRAM_START                          0x00400000
-#define AR6320_SOC_SYSTEM_SLEEP_OFFSET                  0x000000c0
-#define AR6320_SOC_RESET_CONTROL_OFFSET                 0x00000000
-#define AR6320_SOC_CLOCK_CONTROL_OFFSET                 0x00000028
-#define AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
-#define AR6320_SOC_RESET_CONTROL_SI0_RST_MASK           0x00000000
-#define AR6320_WLAN_GPIO_PIN0_ADDRESS                   0x00000068
-#define AR6320_WLAN_GPIO_PIN1_ADDRESS                   0x0000006c
-#define AR6320_WLAN_GPIO_PIN0_CONFIG_MASK               0x00007800
-#define AR6320_WLAN_GPIO_PIN1_CONFIG_MASK               0x00007800
-#define AR6320_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define AR6320_SOC_LPO_CAL_OFFSET                       0x000000e0
-#define AR6320_WLAN_GPIO_PIN10_ADDRESS                  0x00000090
-#define AR6320_WLAN_GPIO_PIN11_ADDRESS                  0x00000094
-#define AR6320_WLAN_GPIO_PIN12_ADDRESS                  0x00000098
-#define AR6320_WLAN_GPIO_PIN13_ADDRESS                  0x0000009c
-#define AR6320_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define AR6320_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-#define AR6320_SOC_LPO_CAL_ENABLE_LSB                   20
-#define AR6320_SOC_LPO_CAL_ENABLE_MASK                  0x00100000
-
-#define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
-#define AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
-#define AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000008
-#define AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000004
-#define AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB              18
-#define AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
-#define AR6320_SI_CONFIG_I2C_LSB                        16
-#define AR6320_SI_CONFIG_I2C_MASK                       0x00010000
-#define AR6320_SI_CONFIG_POS_SAMPLE_LSB                 7
-#define AR6320_SI_CONFIG_POS_SAMPLE_MASK                0x00000080
-#define AR6320_SI_CONFIG_INACTIVE_CLK_LSB               4
-#define AR6320_SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
-#define AR6320_SI_CONFIG_INACTIVE_DATA_LSB              5
-#define AR6320_SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
-#define AR6320_SI_CONFIG_DIVIDER_LSB                    0
-#define AR6320_SI_CONFIG_DIVIDER_MASK                   0x0000000f
-#define AR6320_SI_CONFIG_OFFSET                         0x00000000
-#define AR6320_SI_TX_DATA0_OFFSET                       0x00000008
-#define AR6320_SI_TX_DATA1_OFFSET                       0x0000000c
-#define AR6320_SI_RX_DATA0_OFFSET                       0x00000010
-#define AR6320_SI_RX_DATA1_OFFSET                       0x00000014
-#define AR6320_SI_CS_OFFSET                             0x00000004
-#define AR6320_SI_CS_DONE_ERR_MASK                      0x00000400
-#define AR6320_SI_CS_DONE_INT_MASK                      0x00000200
-#define AR6320_SI_CS_START_LSB                          8
-#define AR6320_SI_CS_START_MASK                         0x00000100
-#define AR6320_SI_CS_RX_CNT_LSB                         4
-#define AR6320_SI_CS_RX_CNT_MASK                        0x000000f0
-#define AR6320_SI_CS_TX_CNT_LSB                         0
-#define AR6320_SI_CS_TX_CNT_MASK                        0x0000000f
-#define AR6320_CE_COUNT                                 8
-#define AR6320_SR_WR_INDEX_ADDRESS                      0x003c
-#define AR6320_DST_WATERMARK_ADDRESS                    0x0050
-#define AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB             14
-#define AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK            0x00004000
-#define AR6320_RX_MPDU_START_0_RETRY_LSB                14
-#define AR6320_RX_MPDU_START_0_RETRY_MASK               0x00004000
-#define AR6320_RX_MPDU_START_0_SEQ_NUM_LSB              16
-#define AR6320_RX_MPDU_START_0_SEQ_NUM_MASK             0x0fff0000
-#define AR6320_RX_MPDU_START_2_TID_LSB                  28
-#define AR6320_RX_MPDU_START_2_TID_MASK                 0xf0000000
-#define AR6320_RX_MPDU_START_2_PN_47_32_LSB             0
-#define AR6320_RX_MPDU_START_2_PN_47_32_MASK            0x0000ffff
-#define AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK            0x000000ff
-#define AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB             0
-#define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB      16
-#define AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK     0xffff0000
-#define AR6320_RX_MSDU_END_4_LAST_MSDU_LSB              15
-#define AR6320_RX_MSDU_END_4_LAST_MSDU_MASK             0x00008000
-#define AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB           2
-#define AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK          0x00000004
-#define AR6320_RX_ATTENTION_0_FRAGMENT_LSB              13
-#define AR6320_RX_ATTENTION_0_FRAGMENT_MASK             0x00002000
-#define AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK      0x08000000
-#define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB      16
-#define AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK     0x00ff0000
-#define AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB          0
-#define AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK         0x00003fff
-#define AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET      0x00000008
-#define AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB         8
-#define AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK        0x00000300
-#define AR6320_RX_MPDU_START_0_ENCRYPTED_LSB            13
-#define AR6320_RX_MPDU_START_0_ENCRYPTED_MASK           0x00002000
-#define AR6320_RX_ATTENTION_0_MORE_DATA_MASK            0x00000400
-#define AR6320_RX_ATTENTION_0_MSDU_DONE_MASK            0x80000000
-#define AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK  0x00040000
-#define AR6320_DST_WR_INDEX_ADDRESS                     0x0040
-#define AR6320_SRC_WATERMARK_ADDRESS                    0x004c
-#define AR6320_SRC_WATERMARK_LOW_MASK                   0xffff0000
-#define AR6320_SRC_WATERMARK_HIGH_MASK                  0x0000ffff
-#define AR6320_DST_WATERMARK_LOW_MASK                   0xffff0000
-#define AR6320_DST_WATERMARK_HIGH_MASK                  0x0000ffff
-#define AR6320_CURRENT_SRRI_ADDRESS                     0x0044
-#define AR6320_CURRENT_DRRI_ADDRESS                     0x0048
-#define AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK     0x00000002
-#define AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK      0x00000004
-#define AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK     0x00000008
-#define AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK      0x00000010
-#define AR6320_HOST_IS_ADDRESS                          0x0030
-#define AR6320_HOST_IS_COPY_COMPLETE_MASK               0x00000001
-#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS     0x0000
-#define AR6320_HOST_IE_ADDRESS                          0x002c
-#define AR6320_HOST_IE_COPY_COMPLETE_MASK               0x00000001
-#define AR6320_SR_BA_ADDRESS                            0x0000
-#define AR6320_SR_SIZE_ADDRESS                          0x0004
-#define AR6320_CE_CTRL1_ADDRESS                         0x0010
-#define AR6320_CE_CTRL1_DMAX_LENGTH_MASK                0x0000ffff
-#define AR6320_DR_BA_ADDRESS                            0x0008
-#define AR6320_DR_SIZE_ADDRESS                          0x000c
-#define AR6320_MISC_IE_ADDRESS                          0x0034
-#define AR6320_MISC_IS_AXI_ERR_MASK                     0x00000400
-#define AR6320_MISC_IS_DST_ADDR_ERR_MASK                0x00000200
-#define AR6320_MISC_IS_SRC_LEN_ERR_MASK                 0x00000100
-#define AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK             0x00000080
-#define AR6320_MISC_IS_DST_RING_OVERFLOW_MASK           0x00000040
-#define AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK           0x00000020
-#define AR6320_SRC_WATERMARK_LOW_LSB                    16
-#define AR6320_SRC_WATERMARK_HIGH_LSB                   0
-#define AR6320_DST_WATERMARK_LOW_LSB                    16
-#define AR6320_DST_WATERMARK_HIGH_LSB                   0
-#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
-#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  8
-#define AR6320_CE_CTRL1_DMAX_LENGTH_LSB                 0
-#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK      0x00010000
-#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK      0x00020000
-#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB       16
-#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB       17
-#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
-#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB  5
-#define AR6320_SOC_GLOBAL_RESET_ADDRESS                 0x0008
-#define AR6320_RTC_STATE_ADDRESS                        0x0000
-#define AR6320_RTC_STATE_COLD_RESET_MASK                0x00002000
-#define AR6320_PCIE_SOC_WAKE_RESET                      0x00000000
-#define AR6320_PCIE_SOC_WAKE_ADDRESS                    0x0004
-#define AR6320_PCIE_SOC_WAKE_V_MASK                     0x00000001
-#define AR6320_RTC_STATE_V_MASK                         0x00000007
-#define AR6320_RTC_STATE_V_LSB                          0
-#define AR6320_RTC_STATE_V_ON                           3
-#define AR6320_MUX_ID_MASK                              0x0000
-#define AR6320_TRANSACTION_ID_MASK                      0x3fff
-#define AR6320_PCIE_LOCAL_BASE_ADDRESS                  0x80000
-#define AR6320_FW_IND_EVENT_PENDING                     1
-#define AR6320_FW_IND_INITIALIZED                       2
-#define AR6320_FW_IND_HELPER                            4
-#define AR6320_PCIE_INTR_ENABLE_ADDRESS                 0x0008
-#define AR6320_PCIE_INTR_CLR_ADDRESS                    0x0014
-#define AR6320_PCIE_INTR_FIRMWARE_MASK                  0x00000400
-#define AR6320_PCIE_INTR_CE0_MASK                       0x00000800
-#define AR6320_PCIE_INTR_CE_MASK_ALL                    0x0007f800
-#define AR6320_PCIE_INTR_CAUSE_ADDRESS                  0x000c
-#define AR6320_CPU_INTR_ADDRESS                         0x0010
-#define AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
-#define AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
-#define AR6320_SOC_RESET_CONTROL_ADDRESS                0x00000000
-#define AR6320_SOC_RESET_CONTROL_CE_RST_MASK            0x00000001
-#define AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
-#define AR6320_CORE_CTRL_ADDRESS                        0x0000
-#define AR6320_CORE_CTRL_CPU_INTR_MASK                  0x00002000
-#define AR6320_LOCAL_SCRATCH_OFFSET                     0x000000c0
-#define AR6320_CLOCK_GPIO_OFFSET                        0xffffffff
-#define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
-#define AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
-#define AR6320_SOC_CHIP_ID_ADDRESS                      0x000000f0
-#define AR6320_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
-#define AR6320_SOC_CHIP_ID_VERSION_LSB                  18
-#define AR6320_SOC_CHIP_ID_REVISION_MASK                0x00000f00
-#define AR6320_SOC_CHIP_ID_REVISION_LSB                 8
-#define AR6320_SOC_POWER_REG_OFFSET                     0x0000010c
-
-/* Copy Engine Debug */
-#define AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
-#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
-#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
-#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
-#define AR6320_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
-#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
-#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
-#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
-#define AR6320_WLAN_DEBUG_OUT_OFFSET                    0x00000110
-#define AR6320_WLAN_DEBUG_OUT_DATA_MSB                  19
-#define AR6320_WLAN_DEBUG_OUT_DATA_LSB                  0
-#define AR6320_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
-#define AR6320_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
-#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
-#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
-#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
-#define AR6320_AMBA_DEBUG_BUS_SEL_MSB                   4
-#define AR6320_AMBA_DEBUG_BUS_SEL_LSB                   0
-#define AR6320_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
-#define AR6320_CE_WRAPPER_DEBUG_OFFSET                  0x0008
-#define AR6320_CE_WRAPPER_DEBUG_SEL_MSB                 5
-#define AR6320_CE_WRAPPER_DEBUG_SEL_LSB                 0
-#define AR6320_CE_WRAPPER_DEBUG_SEL_MASK                0x0000003f
-#define AR6320_CE_DEBUG_OFFSET                          0x0054
-#define AR6320_CE_DEBUG_SEL_MSB                         5
-#define AR6320_CE_DEBUG_SEL_LSB                         0
-#define AR6320_CE_DEBUG_SEL_MASK                        0x0000003f
-/* End */
-
-/* PLL start */
-#define AR6320_EFUSE_OFFSET                             0x0000032c
-#define AR6320_EFUSE_XTAL_SEL_MSB                       10
-#define AR6320_EFUSE_XTAL_SEL_LSB                       8
-#define AR6320_EFUSE_XTAL_SEL_MASK                      0x00000700
-#define AR6320_BB_PLL_CONFIG_OFFSET                     0x000002f4
-#define AR6320_BB_PLL_CONFIG_OUTDIV_MSB                 20
-#define AR6320_BB_PLL_CONFIG_OUTDIV_LSB                 18
-#define AR6320_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
-#define AR6320_BB_PLL_CONFIG_FRAC_MSB                   17
-#define AR6320_BB_PLL_CONFIG_FRAC_LSB                   0
-#define AR6320_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
-#define AR6320_WLAN_PLL_SETTLE_TIME_MSB                 10
-#define AR6320_WLAN_PLL_SETTLE_TIME_LSB                 0
-#define AR6320_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
-#define AR6320_WLAN_PLL_SETTLE_OFFSET                   0x0018
-#define AR6320_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
-#define AR6320_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
-#define AR6320_WLAN_PLL_SETTLE_RESET                    0x00000400
-#define AR6320_WLAN_PLL_CONTROL_NOPWD_MSB               18
-#define AR6320_WLAN_PLL_CONTROL_NOPWD_LSB               18
-#define AR6320_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
-#define AR6320_WLAN_PLL_CONTROL_BYPASS_MSB              16
-#define AR6320_WLAN_PLL_CONTROL_BYPASS_LSB              16
-#define AR6320_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
-#define AR6320_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
-#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
-#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
-#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
-#define AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
-#define AR6320_WLAN_PLL_CONTROL_REFDIV_MSB              13
-#define AR6320_WLAN_PLL_CONTROL_REFDIV_LSB              10
-#define AR6320_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
-#define AR6320_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
-#define AR6320_WLAN_PLL_CONTROL_DIV_MSB                 9
-#define AR6320_WLAN_PLL_CONTROL_DIV_LSB                 0
-#define AR6320_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
-#define AR6320_WLAN_PLL_CONTROL_DIV_RESET               0x11
-#define AR6320_WLAN_PLL_CONTROL_OFFSET                  0x0014
-#define AR6320_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
-#define AR6320_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
-#define AR6320_WLAN_PLL_CONTROL_RESET                   0x00010011
-#define AR6320_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
-#define AR6320_SOC_CORE_CLK_CTRL_DIV_MSB                2
-#define AR6320_SOC_CORE_CLK_CTRL_DIV_LSB                0
-#define AR6320_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
-#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
-#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
-#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
-#define AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
-#define AR6320_RTC_SYNC_STATUS_OFFSET                   0x0244
-#define AR6320_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define AR6320_SOC_CPU_CLOCK_STANDARD_MSB               1
-#define AR6320_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define AR6320_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-/* PLL end */
-
-#define AR6320_PCIE_INTR_CE_MASK(n) \
-	(AR6320_PCIE_INTR_CE0_MASK << (n))
-#define AR6320_DRAM_BASE_ADDRESS          AR6320_TARG_DRAM_START
-#define AR6320_FW_INDICATOR_ADDRESS \
-	(AR6320_SOC_CORE_BASE_ADDRESS + AR6320_SCRATCH_3_ADDRESS)
-#define AR6320_SYSTEM_SLEEP_OFFSET        AR6320_SOC_SYSTEM_SLEEP_OFFSET
-#define AR6320_WLAN_SYSTEM_SLEEP_OFFSET   0x002c
-#define AR6320_WLAN_RESET_CONTROL_OFFSET  AR6320_SOC_RESET_CONTROL_OFFSET
-#define AR6320_CLOCK_CONTROL_OFFSET       AR6320_SOC_CLOCK_CONTROL_OFFSET
-#define AR6320_CLOCK_CONTROL_SI0_CLK_MASK AR6320_SOC_CLOCK_CONTROL_SI0_CLK_MASK
-#define AR6320_RESET_CONTROL_MBOX_RST_MASK 0x00000004
-#define AR6320_RESET_CONTROL_SI0_RST_MASK AR6320_SOC_RESET_CONTROL_SI0_RST_MASK
-#define AR6320_GPIO_BASE_ADDRESS          AR6320_WLAN_GPIO_BASE_ADDRESS
-#define AR6320_GPIO_PIN0_OFFSET           AR6320_WLAN_GPIO_PIN0_ADDRESS
-#define AR6320_GPIO_PIN1_OFFSET           AR6320_WLAN_GPIO_PIN1_ADDRESS
-#define AR6320_GPIO_PIN0_CONFIG_MASK      AR6320_WLAN_GPIO_PIN0_CONFIG_MASK
-#define AR6320_GPIO_PIN1_CONFIG_MASK      AR6320_WLAN_GPIO_PIN1_CONFIG_MASK
-#define AR6320_SI_BASE_ADDRESS            0x00050000
-#define AR6320_CPU_CLOCK_OFFSET           AR6320_SOC_CPU_CLOCK_OFFSET
-#define AR6320_LPO_CAL_OFFSET             AR6320_SOC_LPO_CAL_OFFSET
-#define AR6320_GPIO_PIN10_OFFSET          AR6320_WLAN_GPIO_PIN10_ADDRESS
-#define AR6320_GPIO_PIN11_OFFSET          AR6320_WLAN_GPIO_PIN11_ADDRESS
-#define AR6320_GPIO_PIN12_OFFSET          AR6320_WLAN_GPIO_PIN12_ADDRESS
-#define AR6320_GPIO_PIN13_OFFSET          AR6320_WLAN_GPIO_PIN13_ADDRESS
-#define AR6320_CPU_CLOCK_STANDARD_LSB     AR6320_SOC_CPU_CLOCK_STANDARD_LSB
-#define AR6320_CPU_CLOCK_STANDARD_MASK    AR6320_SOC_CPU_CLOCK_STANDARD_MASK
-#define AR6320_LPO_CAL_ENABLE_LSB         AR6320_SOC_LPO_CAL_ENABLE_LSB
-#define AR6320_LPO_CAL_ENABLE_MASK        AR6320_SOC_LPO_CAL_ENABLE_MASK
-#define AR6320_ANALOG_INTF_BASE_ADDRESS   AR6320_WLAN_ANALOG_INTF_BASE_ADDRESS
-#define AR6320_MBOX_BASE_ADDRESS                       0x00008000
-#define AR6320_INT_STATUS_ENABLE_ERROR_LSB             7
-#define AR6320_INT_STATUS_ENABLE_ERROR_MASK            0x00000080
-#define AR6320_INT_STATUS_ENABLE_CPU_LSB               6
-#define AR6320_INT_STATUS_ENABLE_CPU_MASK              0x00000040
-#define AR6320_INT_STATUS_ENABLE_COUNTER_LSB           4
-#define AR6320_INT_STATUS_ENABLE_COUNTER_MASK          0x00000010
-#define AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB         0
-#define AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK        0x0000000f
-#define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    17
-#define AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   0x00020000
-#define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     16
-#define AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    0x00010000
-#define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB       24
-#define AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK      0xff000000
-#define AR6320_INT_STATUS_ENABLE_ADDRESS               0x0828
-#define AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB           8
-#define AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK          0x0000ff00
-#define AR6320_HOST_INT_STATUS_ADDRESS                 0x0800
-#define AR6320_CPU_INT_STATUS_ADDRESS                  0x0801
-#define AR6320_ERROR_INT_STATUS_ADDRESS                0x0802
-#define AR6320_ERROR_INT_STATUS_WAKEUP_MASK            0x00040000
-#define AR6320_ERROR_INT_STATUS_WAKEUP_LSB             18
-#define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      0x00020000
-#define AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       17
-#define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK       0x00010000
-#define AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB        16
-#define AR6320_COUNT_DEC_ADDRESS                       0x0840
-#define AR6320_HOST_INT_STATUS_CPU_MASK                0x00000040
-#define AR6320_HOST_INT_STATUS_CPU_LSB                 6
-#define AR6320_HOST_INT_STATUS_ERROR_MASK              0x00000080
-#define AR6320_HOST_INT_STATUS_ERROR_LSB               7
-#define AR6320_HOST_INT_STATUS_COUNTER_MASK            0x00000010
-#define AR6320_HOST_INT_STATUS_COUNTER_LSB             4
-#define AR6320_RX_LOOKAHEAD_VALID_ADDRESS              0x0805
-#define AR6320_WINDOW_DATA_ADDRESS                     0x0874
-#define AR6320_WINDOW_READ_ADDR_ADDRESS                0x087c
-#define AR6320_WINDOW_WRITE_ADDR_ADDRESS               0x0878
-
-struct targetdef_s ar6320_targetdef = {
-	.d_RTC_SOC_BASE_ADDRESS = AR6320_RTC_SOC_BASE_ADDRESS,
-	.d_RTC_WMAC_BASE_ADDRESS = AR6320_RTC_WMAC_BASE_ADDRESS,
-	.d_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
-		AR6320_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
-		AR6320_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
-	.d_CLOCK_CONTROL_OFFSET = AR6320_CLOCK_CONTROL_OFFSET,
-	.d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320_CLOCK_CONTROL_SI0_CLK_MASK,
-	.d_RESET_CONTROL_OFFSET = AR6320_SOC_RESET_CONTROL_OFFSET,
-	.d_RESET_CONTROL_MBOX_RST_MASK = AR6320_RESET_CONTROL_MBOX_RST_MASK,
-	.d_RESET_CONTROL_SI0_RST_MASK = AR6320_RESET_CONTROL_SI0_RST_MASK,
-	.d_WLAN_RESET_CONTROL_OFFSET = AR6320_WLAN_RESET_CONTROL_OFFSET,
-	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
-		AR6320_WLAN_RESET_CONTROL_COLD_RST_MASK,
-	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
-		AR6320_WLAN_RESET_CONTROL_WARM_RST_MASK,
-	.d_GPIO_BASE_ADDRESS = AR6320_GPIO_BASE_ADDRESS,
-	.d_GPIO_PIN0_OFFSET = AR6320_GPIO_PIN0_OFFSET,
-	.d_GPIO_PIN1_OFFSET = AR6320_GPIO_PIN1_OFFSET,
-	.d_GPIO_PIN0_CONFIG_MASK = AR6320_GPIO_PIN0_CONFIG_MASK,
-	.d_GPIO_PIN1_CONFIG_MASK = AR6320_GPIO_PIN1_CONFIG_MASK,
-	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320_SI_CONFIG_BIDIR_OD_DATA_LSB,
-	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR6320_SI_CONFIG_BIDIR_OD_DATA_MASK,
-	.d_SI_CONFIG_I2C_LSB = AR6320_SI_CONFIG_I2C_LSB,
-	.d_SI_CONFIG_I2C_MASK = AR6320_SI_CONFIG_I2C_MASK,
-	.d_SI_CONFIG_POS_SAMPLE_LSB = AR6320_SI_CONFIG_POS_SAMPLE_LSB,
-	.d_SI_CONFIG_POS_SAMPLE_MASK = AR6320_SI_CONFIG_POS_SAMPLE_MASK,
-	.d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320_SI_CONFIG_INACTIVE_CLK_LSB,
-	.d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320_SI_CONFIG_INACTIVE_CLK_MASK,
-	.d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320_SI_CONFIG_INACTIVE_DATA_LSB,
-	.d_SI_CONFIG_INACTIVE_DATA_MASK = AR6320_SI_CONFIG_INACTIVE_DATA_MASK,
-	.d_SI_CONFIG_DIVIDER_LSB = AR6320_SI_CONFIG_DIVIDER_LSB,
-	.d_SI_CONFIG_DIVIDER_MASK = AR6320_SI_CONFIG_DIVIDER_MASK,
-	.d_SI_BASE_ADDRESS = AR6320_SI_BASE_ADDRESS,
-	.d_SI_CONFIG_OFFSET = AR6320_SI_CONFIG_OFFSET,
-	.d_SI_TX_DATA0_OFFSET = AR6320_SI_TX_DATA0_OFFSET,
-	.d_SI_TX_DATA1_OFFSET = AR6320_SI_TX_DATA1_OFFSET,
-	.d_SI_RX_DATA0_OFFSET = AR6320_SI_RX_DATA0_OFFSET,
-	.d_SI_RX_DATA1_OFFSET = AR6320_SI_RX_DATA1_OFFSET,
-	.d_SI_CS_OFFSET = AR6320_SI_CS_OFFSET,
-	.d_SI_CS_DONE_ERR_MASK = AR6320_SI_CS_DONE_ERR_MASK,
-	.d_SI_CS_DONE_INT_MASK = AR6320_SI_CS_DONE_INT_MASK,
-	.d_SI_CS_START_LSB = AR6320_SI_CS_START_LSB,
-	.d_SI_CS_START_MASK = AR6320_SI_CS_START_MASK,
-	.d_SI_CS_RX_CNT_LSB = AR6320_SI_CS_RX_CNT_LSB,
-	.d_SI_CS_RX_CNT_MASK = AR6320_SI_CS_RX_CNT_MASK,
-	.d_SI_CS_TX_CNT_LSB = AR6320_SI_CS_TX_CNT_LSB,
-	.d_SI_CS_TX_CNT_MASK = AR6320_SI_CS_TX_CNT_MASK,
-	.d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ,
-	.d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ,
-	.d_MBOX_BASE_ADDRESS = AR6320_MBOX_BASE_ADDRESS,
-	.d_LOCAL_SCRATCH_OFFSET = AR6320_LOCAL_SCRATCH_OFFSET,
-	.d_CPU_CLOCK_OFFSET = AR6320_CPU_CLOCK_OFFSET,
-	.d_LPO_CAL_OFFSET = AR6320_LPO_CAL_OFFSET,
-	.d_GPIO_PIN10_OFFSET = AR6320_GPIO_PIN10_OFFSET,
-	.d_GPIO_PIN11_OFFSET = AR6320_GPIO_PIN11_OFFSET,
-	.d_GPIO_PIN12_OFFSET = AR6320_GPIO_PIN12_OFFSET,
-	.d_GPIO_PIN13_OFFSET = AR6320_GPIO_PIN13_OFFSET,
-	.d_CLOCK_GPIO_OFFSET = AR6320_CLOCK_GPIO_OFFSET,
-	.d_CPU_CLOCK_STANDARD_LSB = AR6320_CPU_CLOCK_STANDARD_LSB,
-	.d_CPU_CLOCK_STANDARD_MASK = AR6320_CPU_CLOCK_STANDARD_MASK,
-	.d_LPO_CAL_ENABLE_LSB = AR6320_LPO_CAL_ENABLE_LSB,
-	.d_LPO_CAL_ENABLE_MASK = AR6320_LPO_CAL_ENABLE_MASK,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
-		AR6320_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
-	.d_ANALOG_INTF_BASE_ADDRESS = AR6320_ANALOG_INTF_BASE_ADDRESS,
-	.d_WLAN_MAC_BASE_ADDRESS = AR6320_WLAN_MAC_BASE_ADDRESS,
-	.d_FW_INDICATOR_ADDRESS = AR6320_FW_INDICATOR_ADDRESS,
-	.d_DRAM_BASE_ADDRESS = AR6320_DRAM_BASE_ADDRESS,
-	.d_SOC_CORE_BASE_ADDRESS = AR6320_SOC_CORE_BASE_ADDRESS,
-	.d_CORE_CTRL_ADDRESS = AR6320_CORE_CTRL_ADDRESS,
-	.d_CE_COUNT = AR6320_CE_COUNT,
-	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
-	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
-	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
-	.d_PCIE_INTR_ENABLE_ADDRESS = AR6320_PCIE_INTR_ENABLE_ADDRESS,
-	.d_PCIE_INTR_CLR_ADDRESS = AR6320_PCIE_INTR_CLR_ADDRESS,
-	.d_PCIE_INTR_FIRMWARE_MASK = AR6320_PCIE_INTR_FIRMWARE_MASK,
-	.d_PCIE_INTR_CE_MASK_ALL = AR6320_PCIE_INTR_CE_MASK_ALL,
-	.d_CORE_CTRL_CPU_INTR_MASK = AR6320_CORE_CTRL_CPU_INTR_MASK,
-	.d_SR_WR_INDEX_ADDRESS = AR6320_SR_WR_INDEX_ADDRESS,
-	.d_DST_WATERMARK_ADDRESS = AR6320_DST_WATERMARK_ADDRESS,
-	/* htt_rx.c */
-	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
-		AR6320_RX_MSDU_END_4_FIRST_MSDU_MASK,
-	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB,
-    .d_RX_MPDU_START_0_RETRY_LSB = AR6320_RX_MPDU_START_0_RETRY_LSB,
-    .d_RX_MPDU_START_0_RETRY_MASK = AR6320_RX_MPDU_START_0_RETRY_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_MASK = AR6320_RX_MPDU_START_0_SEQ_NUM_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320_RX_MPDU_START_0_SEQ_NUM_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_LSB = AR6320_RX_MPDU_START_2_PN_47_32_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_MASK =
-		AR6320_RX_MPDU_START_2_PN_47_32_MASK,
-    .d_RX_MPDU_START_2_TID_LSB = AR6320_RX_MPDU_START_2_TID_LSB,
-    .d_RX_MPDU_START_2_TID_MASK = AR6320_RX_MPDU_START_2_TID_MASK,
-	.d_RX_MSDU_END_1_KEY_ID_OCT_MASK =
-		AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK,
-	.d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR6320_RX_MSDU_END_1_KEY_ID_OCT_LSB,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
-		AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
-		AR6320_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
-	.d_RX_MSDU_END_4_LAST_MSDU_MASK = AR6320_RX_MSDU_END_4_LAST_MSDU_MASK,
-	.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320_RX_MSDU_END_4_LAST_MSDU_LSB,
-	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
-		AR6320_RX_ATTENTION_0_MCAST_BCAST_MASK,
-	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
-		AR6320_RX_ATTENTION_0_MCAST_BCAST_LSB,
-	.d_RX_ATTENTION_0_FRAGMENT_MASK = AR6320_RX_ATTENTION_0_FRAGMENT_MASK,
-	.d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320_RX_ATTENTION_0_FRAGMENT_LSB,
-	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
-		AR6320_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
-		AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
-		AR6320_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
-		AR6320_RX_MSDU_START_0_MSDU_LENGTH_MASK,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
-		AR6320_RX_MSDU_START_0_MSDU_LENGTH_LSB,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
-		AR6320_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
-		AR6320_RX_MSDU_START_2_DECAP_FORMAT_MASK,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
-		AR6320_RX_MSDU_START_2_DECAP_FORMAT_LSB,
-	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
-		AR6320_RX_MPDU_START_0_ENCRYPTED_MASK,
-	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
-		AR6320_RX_MPDU_START_0_ENCRYPTED_LSB,
-	.d_RX_ATTENTION_0_MORE_DATA_MASK =
-		AR6320_RX_ATTENTION_0_MORE_DATA_MASK,
-	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
-		AR6320_RX_ATTENTION_0_MSDU_DONE_MASK,
-	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
-		AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-    /* PLL start */
-	.d_EFUSE_OFFSET = AR6320_EFUSE_OFFSET,
-	.d_EFUSE_XTAL_SEL_MSB = AR6320_EFUSE_XTAL_SEL_MSB,
-	.d_EFUSE_XTAL_SEL_LSB = AR6320_EFUSE_XTAL_SEL_LSB,
-	.d_EFUSE_XTAL_SEL_MASK = AR6320_EFUSE_XTAL_SEL_MASK,
-	.d_BB_PLL_CONFIG_OFFSET = AR6320_BB_PLL_CONFIG_OFFSET,
-	.d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320_BB_PLL_CONFIG_OUTDIV_MSB,
-	.d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320_BB_PLL_CONFIG_OUTDIV_LSB,
-	.d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320_BB_PLL_CONFIG_OUTDIV_MASK,
-	.d_BB_PLL_CONFIG_FRAC_MSB = AR6320_BB_PLL_CONFIG_FRAC_MSB,
-	.d_BB_PLL_CONFIG_FRAC_LSB = AR6320_BB_PLL_CONFIG_FRAC_LSB,
-	.d_BB_PLL_CONFIG_FRAC_MASK = AR6320_BB_PLL_CONFIG_FRAC_MASK,
-	.d_WLAN_PLL_SETTLE_TIME_MSB = AR6320_WLAN_PLL_SETTLE_TIME_MSB,
-	.d_WLAN_PLL_SETTLE_TIME_LSB = AR6320_WLAN_PLL_SETTLE_TIME_LSB,
-	.d_WLAN_PLL_SETTLE_TIME_MASK = AR6320_WLAN_PLL_SETTLE_TIME_MASK,
-	.d_WLAN_PLL_SETTLE_OFFSET = AR6320_WLAN_PLL_SETTLE_OFFSET,
-	.d_WLAN_PLL_SETTLE_SW_MASK = AR6320_WLAN_PLL_SETTLE_SW_MASK,
-	.d_WLAN_PLL_SETTLE_RSTMASK = AR6320_WLAN_PLL_SETTLE_RSTMASK,
-	.d_WLAN_PLL_SETTLE_RESET = AR6320_WLAN_PLL_SETTLE_RESET,
-	.d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320_WLAN_PLL_CONTROL_NOPWD_MSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320_WLAN_PLL_CONTROL_NOPWD_LSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320_WLAN_PLL_CONTROL_NOPWD_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320_WLAN_PLL_CONTROL_BYPASS_MSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320_WLAN_PLL_CONTROL_BYPASS_LSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_MASK = AR6320_WLAN_PLL_CONTROL_BYPASS_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
-		AR6320_WLAN_PLL_CONTROL_BYPASS_RESET,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_MSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = AR6320_WLAN_PLL_CONTROL_CLK_SEL_LSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
-		AR6320_WLAN_PLL_CONTROL_CLK_SEL_MASK,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
-		AR6320_WLAN_PLL_CONTROL_CLK_SEL_RESET,
-	.d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320_WLAN_PLL_CONTROL_REFDIV_MSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320_WLAN_PLL_CONTROL_REFDIV_LSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_MASK = AR6320_WLAN_PLL_CONTROL_REFDIV_MASK,
-	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
-		AR6320_WLAN_PLL_CONTROL_REFDIV_RESET,
-	.d_WLAN_PLL_CONTROL_DIV_MSB = AR6320_WLAN_PLL_CONTROL_DIV_MSB,
-	.d_WLAN_PLL_CONTROL_DIV_LSB = AR6320_WLAN_PLL_CONTROL_DIV_LSB,
-	.d_WLAN_PLL_CONTROL_DIV_MASK = AR6320_WLAN_PLL_CONTROL_DIV_MASK,
-	.d_WLAN_PLL_CONTROL_DIV_RESET = AR6320_WLAN_PLL_CONTROL_DIV_RESET,
-	.d_WLAN_PLL_CONTROL_OFFSET = AR6320_WLAN_PLL_CONTROL_OFFSET,
-	.d_WLAN_PLL_CONTROL_SW_MASK = AR6320_WLAN_PLL_CONTROL_SW_MASK,
-	.d_WLAN_PLL_CONTROL_RSTMASK = AR6320_WLAN_PLL_CONTROL_RSTMASK,
-	.d_WLAN_PLL_CONTROL_RESET = AR6320_WLAN_PLL_CONTROL_RESET,
-	.d_SOC_CORE_CLK_CTRL_OFFSET = AR6320_SOC_CORE_CLK_CTRL_OFFSET,
-	.d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320_SOC_CORE_CLK_CTRL_DIV_MSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320_SOC_CORE_CLK_CTRL_DIV_LSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320_SOC_CORE_CLK_CTRL_DIV_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
-		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
-		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
-		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
-		AR6320_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
-	.d_RTC_SYNC_STATUS_OFFSET = AR6320_RTC_SYNC_STATUS_OFFSET,
-	.d_SOC_CPU_CLOCK_OFFSET = AR6320_SOC_CPU_CLOCK_OFFSET,
-	.d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320_SOC_CPU_CLOCK_STANDARD_MSB,
-	.d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320_SOC_CPU_CLOCK_STANDARD_LSB,
-	.d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320_SOC_CPU_CLOCK_STANDARD_MASK,
-	/* PLL end */
-	.d_SOC_POWER_REG_OFFSET = AR6320_SOC_POWER_REG_OFFSET,
-	.d_PCIE_INTR_CAUSE_ADDRESS = AR6320_PCIE_INTR_CAUSE_ADDRESS,
-	.d_SOC_RESET_CONTROL_ADDRESS = AR6320_SOC_RESET_CONTROL_ADDRESS,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
-		AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
-		AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
-	.d_SOC_RESET_CONTROL_CE_RST_MASK =
-		AR6320_SOC_RESET_CONTROL_CE_RST_MASK,
-	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
-		AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
-	.d_CPU_INTR_ADDRESS = AR6320_CPU_INTR_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
-		AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
-		AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
-	/* chip id start */
-	.d_SOC_CHIP_ID_ADDRESS = AR6320_SOC_CHIP_ID_ADDRESS,
-	.d_SOC_CHIP_ID_VERSION_MASK = AR6320_SOC_CHIP_ID_VERSION_MASK,
-	.d_SOC_CHIP_ID_VERSION_LSB = AR6320_SOC_CHIP_ID_VERSION_LSB,
-	.d_SOC_CHIP_ID_REVISION_MASK = AR6320_SOC_CHIP_ID_REVISION_MASK,
-	.d_SOC_CHIP_ID_REVISION_LSB = AR6320_SOC_CHIP_ID_REVISION_LSB,
-	/* chip id end */
-
-	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
-		AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
-	.d_WLAN_DEBUG_CONTROL_OFFSET = AR6320_WLAN_DEBUG_CONTROL_OFFSET,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
-		AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
-		AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
-		AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK,
-	.d_WLAN_DEBUG_OUT_OFFSET = AR6320_WLAN_DEBUG_OUT_OFFSET,
-	.d_WLAN_DEBUG_OUT_DATA_MSB = AR6320_WLAN_DEBUG_OUT_DATA_MSB,
-	.d_WLAN_DEBUG_OUT_DATA_LSB = AR6320_WLAN_DEBUG_OUT_DATA_LSB,
-	.d_WLAN_DEBUG_OUT_DATA_MASK = AR6320_WLAN_DEBUG_OUT_DATA_MASK,
-	.d_AMBA_DEBUG_BUS_OFFSET = AR6320_AMBA_DEBUG_BUS_OFFSET,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
-		AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
-		AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
-		AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
-	.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320_AMBA_DEBUG_BUS_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320_AMBA_DEBUG_BUS_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320_AMBA_DEBUG_BUS_SEL_MASK,
-
-};
-
-struct hostdef_s ar6320_hostdef = {
-	.d_INT_STATUS_ENABLE_ERROR_LSB = AR6320_INT_STATUS_ENABLE_ERROR_LSB,
-	.d_INT_STATUS_ENABLE_ERROR_MASK = AR6320_INT_STATUS_ENABLE_ERROR_MASK,
-	.d_INT_STATUS_ENABLE_CPU_LSB = AR6320_INT_STATUS_ENABLE_CPU_LSB,
-	.d_INT_STATUS_ENABLE_CPU_MASK = AR6320_INT_STATUS_ENABLE_CPU_MASK,
-	.d_INT_STATUS_ENABLE_COUNTER_LSB =
-		AR6320_INT_STATUS_ENABLE_COUNTER_LSB,
-	.d_INT_STATUS_ENABLE_COUNTER_MASK =
-		AR6320_INT_STATUS_ENABLE_COUNTER_MASK,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
-		AR6320_INT_STATUS_ENABLE_MBOX_DATA_LSB,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
-		AR6320_INT_STATUS_ENABLE_MBOX_DATA_MASK,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
-		AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
-		AR6320_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
-		AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
-		AR6320_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
-		AR6320_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
-		AR6320_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
-	.d_INT_STATUS_ENABLE_ADDRESS = AR6320_INT_STATUS_ENABLE_ADDRESS,
-	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
-		AR6320_CPU_INT_STATUS_ENABLE_BIT_LSB,
-	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
-		AR6320_CPU_INT_STATUS_ENABLE_BIT_MASK,
-	.d_HOST_INT_STATUS_ADDRESS = AR6320_HOST_INT_STATUS_ADDRESS,
-	.d_CPU_INT_STATUS_ADDRESS = AR6320_CPU_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_ADDRESS = AR6320_ERROR_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_WAKEUP_MASK = AR6320_ERROR_INT_STATUS_WAKEUP_MASK,
-	.d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320_ERROR_INT_STATUS_WAKEUP_LSB,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
-		AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
-		AR6320_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
-		AR6320_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
-		AR6320_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
-	.d_COUNT_DEC_ADDRESS = AR6320_COUNT_DEC_ADDRESS,
-	.d_HOST_INT_STATUS_CPU_MASK = AR6320_HOST_INT_STATUS_CPU_MASK,
-	.d_HOST_INT_STATUS_CPU_LSB = AR6320_HOST_INT_STATUS_CPU_LSB,
-	.d_HOST_INT_STATUS_ERROR_MASK = AR6320_HOST_INT_STATUS_ERROR_MASK,
-	.d_HOST_INT_STATUS_ERROR_LSB = AR6320_HOST_INT_STATUS_ERROR_LSB,
-	.d_HOST_INT_STATUS_COUNTER_MASK = AR6320_HOST_INT_STATUS_COUNTER_MASK,
-	.d_HOST_INT_STATUS_COUNTER_LSB = AR6320_HOST_INT_STATUS_COUNTER_LSB,
-	.d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320_RX_LOOKAHEAD_VALID_ADDRESS,
-	.d_WINDOW_DATA_ADDRESS = AR6320_WINDOW_DATA_ADDRESS,
-	.d_WINDOW_READ_ADDR_ADDRESS = AR6320_WINDOW_READ_ADDR_ADDRESS,
-	.d_WINDOW_WRITE_ADDR_ADDRESS = AR6320_WINDOW_WRITE_ADDR_ADDRESS,
-	.d_SOC_GLOBAL_RESET_ADDRESS = AR6320_SOC_GLOBAL_RESET_ADDRESS,
-	.d_RTC_STATE_ADDRESS = AR6320_RTC_STATE_ADDRESS,
-	.d_RTC_STATE_COLD_RESET_MASK = AR6320_RTC_STATE_COLD_RESET_MASK,
-	.d_PCIE_LOCAL_BASE_ADDRESS = AR6320_PCIE_LOCAL_BASE_ADDRESS,
-	.d_PCIE_SOC_WAKE_RESET = AR6320_PCIE_SOC_WAKE_RESET,
-	.d_PCIE_SOC_WAKE_ADDRESS = AR6320_PCIE_SOC_WAKE_ADDRESS,
-	.d_PCIE_SOC_WAKE_V_MASK = AR6320_PCIE_SOC_WAKE_V_MASK,
-	.d_RTC_STATE_V_MASK = AR6320_RTC_STATE_V_MASK,
-	.d_RTC_STATE_V_LSB = AR6320_RTC_STATE_V_LSB,
-	.d_FW_IND_EVENT_PENDING = AR6320_FW_IND_EVENT_PENDING,
-	.d_FW_IND_INITIALIZED = AR6320_FW_IND_INITIALIZED,
-	.d_FW_IND_HELPER = AR6320_FW_IND_HELPER,
-	.d_RTC_STATE_V_ON = AR6320_RTC_STATE_V_ON,
-	.d_MUX_ID_MASK = AR6320_MUX_ID_MASK,
-	.d_TRANSACTION_ID_MASK = AR6320_TRANSACTION_ID_MASK,
-#if defined(SDIO_3_0)
-	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
-		AR6320_HOST_INT_STATUS_MBOX_DATA_MASK,
-	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
-		AR6320_HOST_INT_STATUS_MBOX_DATA_LSB,
-#endif
-	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
-	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
-	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
-	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
-	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
-	.d_HOST_CE_COUNT = 8,
-	.d_ENABLE_MSI = 0,
-};
-
-
-struct ce_reg_def ar6320_ce_targetdef = {
-	/* copy_engine.c  */
-	.d_DST_WR_INDEX_ADDRESS = AR6320_DST_WR_INDEX_ADDRESS,
-	.d_SRC_WATERMARK_ADDRESS = AR6320_SRC_WATERMARK_ADDRESS,
-	.d_SRC_WATERMARK_LOW_MASK = AR6320_SRC_WATERMARK_LOW_MASK,
-	.d_SRC_WATERMARK_HIGH_MASK = AR6320_SRC_WATERMARK_HIGH_MASK,
-	.d_DST_WATERMARK_LOW_MASK = AR6320_DST_WATERMARK_LOW_MASK,
-	.d_DST_WATERMARK_HIGH_MASK = AR6320_DST_WATERMARK_HIGH_MASK,
-	.d_CURRENT_SRRI_ADDRESS = AR6320_CURRENT_SRRI_ADDRESS,
-	.d_CURRENT_DRRI_ADDRESS = AR6320_CURRENT_DRRI_ADDRESS,
-	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
-		AR6320_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
-		AR6320_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
-		AR6320_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
-		AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_ADDRESS = AR6320_HOST_IS_ADDRESS,
-	.d_HOST_IS_COPY_COMPLETE_MASK = AR6320_HOST_IS_COPY_COMPLETE_MASK,
-	.d_CE_WRAPPER_BASE_ADDRESS = AR6320_CE_WRAPPER_BASE_ADDRESS,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
-		AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
-	.d_HOST_IE_ADDRESS = AR6320_HOST_IE_ADDRESS,
-	.d_HOST_IE_COPY_COMPLETE_MASK = AR6320_HOST_IE_COPY_COMPLETE_MASK,
-	.d_SR_BA_ADDRESS = AR6320_SR_BA_ADDRESS,
-	.d_SR_SIZE_ADDRESS = AR6320_SR_SIZE_ADDRESS,
-	.d_CE_CTRL1_ADDRESS = AR6320_CE_CTRL1_ADDRESS,
-	.d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320_CE_CTRL1_DMAX_LENGTH_MASK,
-	.d_DR_BA_ADDRESS = AR6320_DR_BA_ADDRESS,
-	.d_DR_SIZE_ADDRESS = AR6320_DR_SIZE_ADDRESS,
-	.d_MISC_IE_ADDRESS = AR6320_MISC_IE_ADDRESS,
-	.d_MISC_IS_AXI_ERR_MASK = AR6320_MISC_IS_AXI_ERR_MASK,
-	.d_MISC_IS_DST_ADDR_ERR_MASK = AR6320_MISC_IS_DST_ADDR_ERR_MASK,
-	.d_MISC_IS_SRC_LEN_ERR_MASK = AR6320_MISC_IS_SRC_LEN_ERR_MASK,
-	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR6320_MISC_IS_DST_MAX_LEN_VIO_MASK,
-	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
-		AR6320_MISC_IS_DST_RING_OVERFLOW_MASK,
-	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
-		AR6320_MISC_IS_SRC_RING_OVERFLOW_MASK,
-	.d_SRC_WATERMARK_LOW_LSB = AR6320_SRC_WATERMARK_LOW_LSB,
-	.d_SRC_WATERMARK_HIGH_LSB = AR6320_SRC_WATERMARK_HIGH_LSB,
-	.d_DST_WATERMARK_LOW_LSB = AR6320_DST_WATERMARK_LOW_LSB,
-	.d_DST_WATERMARK_HIGH_LSB = AR6320_DST_WATERMARK_HIGH_LSB,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
-		AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
-		AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
-	.d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320_CE_CTRL1_DMAX_LENGTH_LSB,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
-		AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
-		AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
-		AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
-		AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_WRAPPER_DEBUG_OFFSET = AR6320_CE_WRAPPER_DEBUG_OFFSET,
-	.d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320_CE_WRAPPER_DEBUG_SEL_MSB,
-	.d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320_CE_WRAPPER_DEBUG_SEL_LSB,
-	.d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320_CE_WRAPPER_DEBUG_SEL_MASK,
-	.d_CE_DEBUG_OFFSET = AR6320_CE_DEBUG_OFFSET,
-	.d_CE_DEBUG_SEL_MSB = AR6320_CE_DEBUG_SEL_MSB,
-	.d_CE_DEBUG_SEL_LSB = AR6320_CE_DEBUG_SEL_LSB,
-	.d_CE_DEBUG_SEL_MASK = AR6320_CE_DEBUG_SEL_MASK,
-	.d_CE0_BASE_ADDRESS = AR6320_CE0_BASE_ADDRESS,
-	.d_CE1_BASE_ADDRESS = AR6320_CE1_BASE_ADDRESS,
-
-};
-
-#endif

core/hif/src/ar6320v2def.h

@@ -1,815 +0,0 @@
-/*
- * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _AR6320V2DEF_H_
-#define _AR6320V2DEF_H_
-
-/* Base Addresses */
-#define AR6320V2_RTC_SOC_BASE_ADDRESS                     0x00000800
-#define AR6320V2_RTC_WMAC_BASE_ADDRESS                    0x00001000
-#define AR6320V2_MAC_COEX_BASE_ADDRESS                    0x0000f000
-#define AR6320V2_BT_COEX_BASE_ADDRESS                     0x00002000
-#define AR6320V2_SOC_PCIE_BASE_ADDRESS                    0x00038000
-#define AR6320V2_SOC_CORE_BASE_ADDRESS                    0x0003a000
-#define AR6320V2_WLAN_UART_BASE_ADDRESS                   0x0000c000
-#define AR6320V2_WLAN_SI_BASE_ADDRESS                     0x00010000
-#define AR6320V2_WLAN_GPIO_BASE_ADDRESS                   0x00005000
-#define AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS            0x00006000
-#define AR6320V2_WLAN_MAC_BASE_ADDRESS                    0x00010000
-#define AR6320V2_EFUSE_BASE_ADDRESS                       0x00024000
-#define AR6320V2_FPGA_REG_BASE_ADDRESS                    0x00039000
-#define AR6320V2_WLAN_UART2_BASE_ADDRESS                  0x00054c00
-#define AR6320V2_CE_WRAPPER_BASE_ADDRESS                  0x00034000
-#define AR6320V2_CE0_BASE_ADDRESS                         0x00034400
-#define AR6320V2_CE1_BASE_ADDRESS                         0x00034800
-#define AR6320V2_CE2_BASE_ADDRESS                         0x00034c00
-#define AR6320V2_CE3_BASE_ADDRESS                         0x00035000
-#define AR6320V2_CE4_BASE_ADDRESS                         0x00035400
-#define AR6320V2_CE5_BASE_ADDRESS                         0x00035800
-#define AR6320V2_CE6_BASE_ADDRESS                         0x00035c00
-#define AR6320V2_CE7_BASE_ADDRESS                         0x00036000
-#define AR6320V2_DBI_BASE_ADDRESS                         0x0003c000
-#define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS       0x00007800
-
-#define AR6320V2_SCRATCH_3_ADDRESS                        0x0028
-#define AR6320V2_TARG_DRAM_START                          0x00400000
-#define AR6320V2_SOC_SYSTEM_SLEEP_OFFSET                  0x000000c0
-#define AR6320V2_SOC_RESET_CONTROL_OFFSET                 0x00000000
-#define AR6320V2_SOC_CLOCK_CONTROL_OFFSET                 0x00000028
-#define AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
-#define AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK           0x00000000
-#define AR6320V2_WLAN_GPIO_PIN0_ADDRESS                   0x00000068
-#define AR6320V2_WLAN_GPIO_PIN1_ADDRESS                   0x0000006c
-#define AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK               0x00007800
-#define AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK               0x00007800
-#define AR6320V2_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define AR6320V2_SOC_LPO_CAL_OFFSET                       0x000000e0
-#define AR6320V2_WLAN_GPIO_PIN10_ADDRESS                  0x00000090
-#define AR6320V2_WLAN_GPIO_PIN11_ADDRESS                  0x00000094
-#define AR6320V2_WLAN_GPIO_PIN12_ADDRESS                  0x00000098
-#define AR6320V2_WLAN_GPIO_PIN13_ADDRESS                  0x0000009c
-#define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-#define AR6320V2_SOC_LPO_CAL_ENABLE_LSB                   20
-#define AR6320V2_SOC_LPO_CAL_ENABLE_MASK                  0x00100000
-
-#define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
-#define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
-#define AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000008
-#define AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000004
-#define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB              18
-#define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
-#define AR6320V2_SI_CONFIG_I2C_LSB                        16
-#define AR6320V2_SI_CONFIG_I2C_MASK                       0x00010000
-#define AR6320V2_SI_CONFIG_POS_SAMPLE_LSB                 7
-#define AR6320V2_SI_CONFIG_POS_SAMPLE_MASK                0x00000080
-#define AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB               4
-#define AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
-#define AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB              5
-#define AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
-#define AR6320V2_SI_CONFIG_DIVIDER_LSB                    0
-#define AR6320V2_SI_CONFIG_DIVIDER_MASK                   0x0000000f
-#define AR6320V2_SI_CONFIG_OFFSET                         0x00000000
-#define AR6320V2_SI_TX_DATA0_OFFSET                       0x00000008
-#define AR6320V2_SI_TX_DATA1_OFFSET                       0x0000000c
-#define AR6320V2_SI_RX_DATA0_OFFSET                       0x00000010
-#define AR6320V2_SI_RX_DATA1_OFFSET                       0x00000014
-#define AR6320V2_SI_CS_OFFSET                             0x00000004
-#define AR6320V2_SI_CS_DONE_ERR_MASK                      0x00000400
-#define AR6320V2_SI_CS_DONE_INT_MASK                      0x00000200
-#define AR6320V2_SI_CS_START_LSB                          8
-#define AR6320V2_SI_CS_START_MASK                         0x00000100
-#define AR6320V2_SI_CS_RX_CNT_LSB                         4
-#define AR6320V2_SI_CS_RX_CNT_MASK                        0x000000f0
-#define AR6320V2_SI_CS_TX_CNT_LSB                         0
-#define AR6320V2_SI_CS_TX_CNT_MASK                        0x0000000f
-#define AR6320V2_CE_COUNT                                 8
-#define AR6320V2_SR_WR_INDEX_ADDRESS                      0x003c
-#define AR6320V2_DST_WATERMARK_ADDRESS                    0x0050
-#define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB             14
-#define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK            0x00004000
-#define AR6320V2_RX_MPDU_START_0_RETRY_LSB                14
-#define AR6320V2_RX_MPDU_START_0_RETRY_MASK               0x00004000
-#define AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB              16
-#define AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK             0x0fff0000
-#define AR6320V2_RX_MPDU_START_2_PN_47_32_LSB             0
-#define AR6320V2_RX_MPDU_START_2_PN_47_32_MASK            0x0000ffff
-#define AR6320V2_RX_MPDU_START_2_TID_LSB                  28
-#define AR6320V2_RX_MPDU_START_2_TID_MASK                 0xf0000000
-#define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB      16
-#define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK     0xffff0000
-#define AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB              15
-#define AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK             0x00008000
-#define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB           2
-#define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK          0x00000004
-#define AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB              13
-#define AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK             0x00002000
-#define AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK      0x08000000
-#define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB      16
-#define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK     0x00ff0000
-#define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB          0
-#define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK         0x00003fff
-
-#define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET      0x00000008
-#define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB         8
-#define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK        0x00000300
-#define AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB            13
-#define AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK           0x00002000
-#define AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK            0x00000400
-#define AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK            0x80000000
-#define AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK  0x00040000
-#define AR6320V2_DST_WR_INDEX_ADDRESS                     0x0040
-#define AR6320V2_SRC_WATERMARK_ADDRESS                    0x004c
-#define AR6320V2_SRC_WATERMARK_LOW_MASK                   0xffff0000
-#define AR6320V2_SRC_WATERMARK_HIGH_MASK                  0x0000ffff
-#define AR6320V2_DST_WATERMARK_LOW_MASK                   0xffff0000
-#define AR6320V2_DST_WATERMARK_HIGH_MASK                  0x0000ffff
-#define AR6320V2_CURRENT_SRRI_ADDRESS                     0x0044
-#define AR6320V2_CURRENT_DRRI_ADDRESS                     0x0048
-#define AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK     0x00000002
-#define AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK      0x00000004
-#define AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK     0x00000008
-#define AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK      0x00000010
-#define AR6320V2_HOST_IS_ADDRESS                          0x0030
-#define AR6320V2_HOST_IS_COPY_COMPLETE_MASK               0x00000001
-#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS     0x0000
-#define AR6320V2_HOST_IE_ADDRESS                          0x002c
-#define AR6320V2_HOST_IE_COPY_COMPLETE_MASK               0x00000001
-#define AR6320V2_SR_BA_ADDRESS                            0x0000
-#define AR6320V2_SR_SIZE_ADDRESS                          0x0004
-#define AR6320V2_CE_CTRL1_ADDRESS                         0x0010
-#define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK                0x0000ffff
-#define AR6320V2_DR_BA_ADDRESS                            0x0008
-#define AR6320V2_DR_SIZE_ADDRESS                          0x000c
-#define AR6320V2_MISC_IE_ADDRESS                          0x0034
-#define AR6320V2_MISC_IS_AXI_ERR_MASK                     0x00000400
-#define AR6320V2_MISC_IS_DST_ADDR_ERR_MASK                0x00000200
-#define AR6320V2_MISC_IS_SRC_LEN_ERR_MASK                 0x00000100
-#define AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK             0x00000080
-#define AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK           0x00000040
-#define AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK           0x00000020
-#define AR6320V2_SRC_WATERMARK_LOW_LSB                    16
-#define AR6320V2_SRC_WATERMARK_HIGH_LSB                   0
-#define AR6320V2_DST_WATERMARK_LOW_LSB                    16
-#define AR6320V2_DST_WATERMARK_HIGH_LSB                   0
-#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
-#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  8
-#define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB                 0
-#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK      0x00010000
-#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK      0x00020000
-#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB       16
-#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB       17
-#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
-#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB  5
-#define AR6320V2_SOC_GLOBAL_RESET_ADDRESS                 0x0008
-#define AR6320V2_RTC_STATE_ADDRESS                        0x0000
-#define AR6320V2_RTC_STATE_COLD_RESET_MASK                0x00002000
-#define AR6320V2_PCIE_SOC_WAKE_RESET                      0x00000000
-#define AR6320V2_PCIE_SOC_WAKE_ADDRESS                    0x0004
-#define AR6320V2_PCIE_SOC_WAKE_V_MASK                     0x00000001
-#define AR6320V2_RTC_STATE_V_MASK                         0x00000007
-#define AR6320V2_RTC_STATE_V_LSB                          0
-#define AR6320V2_RTC_STATE_V_ON                           3
-#define AR6320V2_MUX_ID_MASK                              0x0000
-#define AR6320V2_TRANSACTION_ID_MASK                      0x3fff
-#define AR6320V2_PCIE_LOCAL_BASE_ADDRESS                  0x80000
-#define AR6320V2_FW_IND_EVENT_PENDING                     1
-#define AR6320V2_FW_IND_INITIALIZED                       2
-#define AR6320V2_FW_IND_HELPER                            4
-#define AR6320V2_PCIE_INTR_ENABLE_ADDRESS                 0x0008
-#define AR6320V2_PCIE_INTR_CLR_ADDRESS                    0x0014
-#define AR6320V2_PCIE_INTR_FIRMWARE_MASK                  0x00000400
-#define AR6320V2_PCIE_INTR_CE0_MASK                       0x00000800
-#define AR6320V2_PCIE_INTR_CE_MASK_ALL                    0x0007f800
-#define AR6320V2_PCIE_INTR_CAUSE_ADDRESS                  0x000c
-#define AR6320V2_CPU_INTR_ADDRESS                         0x0010
-#define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
-#define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
-#define AR6320V2_SOC_RESET_CONTROL_ADDRESS                0x00000000
-#define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK            0x00000001
-#define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
-#define AR6320V2_CORE_CTRL_ADDRESS                        0x0000
-#define AR6320V2_CORE_CTRL_CPU_INTR_MASK                  0x00002000
-#define AR6320V2_LOCAL_SCRATCH_OFFSET                     0x000000c0
-#define AR6320V2_CLOCK_GPIO_OFFSET                        0xffffffff
-#define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
-#define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
-#define AR6320V2_SOC_CHIP_ID_ADDRESS                      0x000000f0
-#define AR6320V2_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
-#define AR6320V2_SOC_CHIP_ID_VERSION_LSB                  18
-#define AR6320V2_SOC_CHIP_ID_REVISION_MASK                0x00000f00
-#define AR6320V2_SOC_CHIP_ID_REVISION_LSB                 8
-#define AR6320V2_SOC_POWER_REG_OFFSET                     0x0000010c
-
-/* Copy Engine Debug */
-#define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
-#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
-#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
-#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
-#define AR6320V2_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
-#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
-#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
-#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
-#define AR6320V2_WLAN_DEBUG_OUT_OFFSET                    0x00000110
-#define AR6320V2_WLAN_DEBUG_OUT_DATA_MSB                  19
-#define AR6320V2_WLAN_DEBUG_OUT_DATA_LSB                  0
-#define AR6320V2_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
-#define AR6320V2_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
-#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
-#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
-#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
-#define AR6320V2_AMBA_DEBUG_BUS_SEL_MSB                   4
-#define AR6320V2_AMBA_DEBUG_BUS_SEL_LSB                   0
-#define AR6320V2_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
-#define AR6320V2_CE_WRAPPER_DEBUG_OFFSET                  0x0008
-#define AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB                 5
-#define AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB                 0
-#define AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK                0x0000003f
-#define AR6320V2_CE_DEBUG_OFFSET                          0x0054
-#define AR6320V2_CE_DEBUG_SEL_MSB                         5
-#define AR6320V2_CE_DEBUG_SEL_LSB                         0
-#define AR6320V2_CE_DEBUG_SEL_MASK                        0x0000003f
-/* End */
-
-/* PLL start */
-#define AR6320V2_EFUSE_OFFSET                             0x0000032c
-#define AR6320V2_EFUSE_XTAL_SEL_MSB                       10
-#define AR6320V2_EFUSE_XTAL_SEL_LSB                       8
-#define AR6320V2_EFUSE_XTAL_SEL_MASK                      0x00000700
-#define AR6320V2_BB_PLL_CONFIG_OFFSET                     0x000002f4
-#define AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB                 20
-#define AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB                 18
-#define AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
-#define AR6320V2_BB_PLL_CONFIG_FRAC_MSB                   17
-#define AR6320V2_BB_PLL_CONFIG_FRAC_LSB                   0
-#define AR6320V2_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
-#define AR6320V2_WLAN_PLL_SETTLE_TIME_MSB                 10
-#define AR6320V2_WLAN_PLL_SETTLE_TIME_LSB                 0
-#define AR6320V2_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
-#define AR6320V2_WLAN_PLL_SETTLE_OFFSET                   0x0018
-#define AR6320V2_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
-#define AR6320V2_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
-#define AR6320V2_WLAN_PLL_SETTLE_RESET                    0x00000400
-#define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB               18
-#define AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB               18
-#define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
-#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB              16
-#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB              16
-#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
-#define AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
-#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
-#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
-#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
-#define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
-#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB              13
-#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB              10
-#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
-#define AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
-#define AR6320V2_WLAN_PLL_CONTROL_DIV_MSB                 9
-#define AR6320V2_WLAN_PLL_CONTROL_DIV_LSB                 0
-#define AR6320V2_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
-#define AR6320V2_WLAN_PLL_CONTROL_DIV_RESET               0x11
-#define AR6320V2_WLAN_PLL_CONTROL_OFFSET                  0x0014
-#define AR6320V2_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
-#define AR6320V2_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
-#define AR6320V2_WLAN_PLL_CONTROL_RESET                   0x00010011
-#define AR6320V2_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
-#define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB                2
-#define AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB                0
-#define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
-#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
-#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
-#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
-#define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
-#define AR6320V2_RTC_SYNC_STATUS_OFFSET                   0x0244
-#define AR6320V2_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB               1
-#define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-/* PLL end */
-
-#define AR6320V2_PCIE_INTR_CE_MASK(n) \
-	(AR6320V2_PCIE_INTR_CE0_MASK << (n))
-#define AR6320V2_DRAM_BASE_ADDRESS            AR6320V2_TARG_DRAM_START
-#define AR6320V2_FW_INDICATOR_ADDRESS \
-	(AR6320V2_SOC_CORE_BASE_ADDRESS + AR6320V2_SCRATCH_3_ADDRESS)
-#define AR6320V2_SYSTEM_SLEEP_OFFSET          AR6320V2_SOC_SYSTEM_SLEEP_OFFSET
-#define AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET     0x002c
-#define AR6320V2_WLAN_RESET_CONTROL_OFFSET    AR6320V2_SOC_RESET_CONTROL_OFFSET
-#define AR6320V2_CLOCK_CONTROL_OFFSET         AR6320V2_SOC_CLOCK_CONTROL_OFFSET
-#define AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK \
-	AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK
-#define AR6320V2_RESET_CONTROL_MBOX_RST_MASK  0x00000004
-#define AR6320V2_RESET_CONTROL_SI0_RST_MASK \
-	AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK
-#define AR6320V2_GPIO_BASE_ADDRESS         AR6320V2_WLAN_GPIO_BASE_ADDRESS
-#define AR6320V2_GPIO_PIN0_OFFSET          AR6320V2_WLAN_GPIO_PIN0_ADDRESS
-#define AR6320V2_GPIO_PIN1_OFFSET          AR6320V2_WLAN_GPIO_PIN1_ADDRESS
-#define AR6320V2_GPIO_PIN0_CONFIG_MASK     AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK
-#define AR6320V2_GPIO_PIN1_CONFIG_MASK     AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK
-#define AR6320V2_SI_BASE_ADDRESS           0x00050000
-#define AR6320V2_CPU_CLOCK_OFFSET          AR6320V2_SOC_CPU_CLOCK_OFFSET
-#define AR6320V2_LPO_CAL_OFFSET            AR6320V2_SOC_LPO_CAL_OFFSET
-#define AR6320V2_GPIO_PIN10_OFFSET         AR6320V2_WLAN_GPIO_PIN10_ADDRESS
-#define AR6320V2_GPIO_PIN11_OFFSET         AR6320V2_WLAN_GPIO_PIN11_ADDRESS
-#define AR6320V2_GPIO_PIN12_OFFSET         AR6320V2_WLAN_GPIO_PIN12_ADDRESS
-#define AR6320V2_GPIO_PIN13_OFFSET         AR6320V2_WLAN_GPIO_PIN13_ADDRESS
-#define AR6320V2_CPU_CLOCK_STANDARD_LSB    AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB
-#define AR6320V2_CPU_CLOCK_STANDARD_MASK   AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK
-#define AR6320V2_LPO_CAL_ENABLE_LSB        AR6320V2_SOC_LPO_CAL_ENABLE_LSB
-#define AR6320V2_LPO_CAL_ENABLE_MASK       AR6320V2_SOC_LPO_CAL_ENABLE_MASK
-#define AR6320V2_ANALOG_INTF_BASE_ADDRESS \
-	AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS
-#define AR6320V2_MBOX_BASE_ADDRESS                       0x00008000
-#define AR6320V2_INT_STATUS_ENABLE_ERROR_LSB             7
-#define AR6320V2_INT_STATUS_ENABLE_ERROR_MASK            0x00000080
-#define AR6320V2_INT_STATUS_ENABLE_CPU_LSB               6
-#define AR6320V2_INT_STATUS_ENABLE_CPU_MASK              0x00000040
-#define AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB           4
-#define AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK          0x00000010
-#define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB         0
-#define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK        0x0000000f
-#define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    17
-#define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   0x00020000
-#define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     16
-#define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    0x00010000
-#define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB       24
-#define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK      0xff000000
-#define AR6320V2_INT_STATUS_ENABLE_ADDRESS               0x0828
-#define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB           8
-#define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK          0x0000ff00
-#define AR6320V2_HOST_INT_STATUS_ADDRESS                 0x0800
-#define AR6320V2_CPU_INT_STATUS_ADDRESS                  0x0801
-#define AR6320V2_ERROR_INT_STATUS_ADDRESS                0x0802
-#define AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK            0x00040000
-#define AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB             18
-#define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      0x00020000
-#define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       17
-#define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK       0x00010000
-#define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB        16
-#define AR6320V2_COUNT_DEC_ADDRESS                       0x0840
-#define AR6320V2_HOST_INT_STATUS_CPU_MASK                0x00000040
-#define AR6320V2_HOST_INT_STATUS_CPU_LSB                 6
-#define AR6320V2_HOST_INT_STATUS_ERROR_MASK              0x00000080
-#define AR6320V2_HOST_INT_STATUS_ERROR_LSB               7
-#define AR6320V2_HOST_INT_STATUS_COUNTER_MASK            0x00000010
-#define AR6320V2_HOST_INT_STATUS_COUNTER_LSB             4
-#define AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS              0x0805
-#define AR6320V2_WINDOW_DATA_ADDRESS                     0x0874
-#define AR6320V2_WINDOW_READ_ADDR_ADDRESS                0x087c
-#define AR6320V2_WINDOW_WRITE_ADDR_ADDRESS               0x0878
-
-struct targetdef_s ar6320v2_targetdef = {
-	.d_RTC_SOC_BASE_ADDRESS = AR6320V2_RTC_SOC_BASE_ADDRESS,
-	.d_RTC_WMAC_BASE_ADDRESS = AR6320V2_RTC_WMAC_BASE_ADDRESS,
-	.d_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
-		AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
-		AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
-	.d_CLOCK_CONTROL_OFFSET = AR6320V2_CLOCK_CONTROL_OFFSET,
-	.d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK,
-	.d_RESET_CONTROL_OFFSET = AR6320V2_SOC_RESET_CONTROL_OFFSET,
-	.d_RESET_CONTROL_MBOX_RST_MASK = AR6320V2_RESET_CONTROL_MBOX_RST_MASK,
-	.d_RESET_CONTROL_SI0_RST_MASK = AR6320V2_RESET_CONTROL_SI0_RST_MASK,
-	.d_WLAN_RESET_CONTROL_OFFSET = AR6320V2_WLAN_RESET_CONTROL_OFFSET,
-	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
-		AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK,
-	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
-		AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK,
-	.d_GPIO_BASE_ADDRESS = AR6320V2_GPIO_BASE_ADDRESS,
-	.d_GPIO_PIN0_OFFSET = AR6320V2_GPIO_PIN0_OFFSET,
-	.d_GPIO_PIN1_OFFSET = AR6320V2_GPIO_PIN1_OFFSET,
-	.d_GPIO_PIN0_CONFIG_MASK = AR6320V2_GPIO_PIN0_CONFIG_MASK,
-	.d_GPIO_PIN1_CONFIG_MASK = AR6320V2_GPIO_PIN1_CONFIG_MASK,
-	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB,
-	.d_SI_CONFIG_BIDIR_OD_DATA_MASK =
-		AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK,
-	.d_SI_CONFIG_I2C_LSB = AR6320V2_SI_CONFIG_I2C_LSB,
-	.d_SI_CONFIG_I2C_MASK = AR6320V2_SI_CONFIG_I2C_MASK,
-	.d_SI_CONFIG_POS_SAMPLE_LSB = AR6320V2_SI_CONFIG_POS_SAMPLE_LSB,
-	.d_SI_CONFIG_POS_SAMPLE_MASK = AR6320V2_SI_CONFIG_POS_SAMPLE_MASK,
-	.d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB,
-	.d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK,
-	.d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB,
-	.d_SI_CONFIG_INACTIVE_DATA_MASK =
-		AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK,
-	.d_SI_CONFIG_DIVIDER_LSB = AR6320V2_SI_CONFIG_DIVIDER_LSB,
-	.d_SI_CONFIG_DIVIDER_MASK = AR6320V2_SI_CONFIG_DIVIDER_MASK,
-	.d_SI_BASE_ADDRESS = AR6320V2_SI_BASE_ADDRESS,
-	.d_SI_CONFIG_OFFSET = AR6320V2_SI_CONFIG_OFFSET,
-	.d_SI_TX_DATA0_OFFSET = AR6320V2_SI_TX_DATA0_OFFSET,
-	.d_SI_TX_DATA1_OFFSET = AR6320V2_SI_TX_DATA1_OFFSET,
-	.d_SI_RX_DATA0_OFFSET = AR6320V2_SI_RX_DATA0_OFFSET,
-	.d_SI_RX_DATA1_OFFSET = AR6320V2_SI_RX_DATA1_OFFSET,
-	.d_SI_CS_OFFSET = AR6320V2_SI_CS_OFFSET,
-	.d_SI_CS_DONE_ERR_MASK = AR6320V2_SI_CS_DONE_ERR_MASK,
-	.d_SI_CS_DONE_INT_MASK = AR6320V2_SI_CS_DONE_INT_MASK,
-	.d_SI_CS_START_LSB = AR6320V2_SI_CS_START_LSB,
-	.d_SI_CS_START_MASK = AR6320V2_SI_CS_START_MASK,
-	.d_SI_CS_RX_CNT_LSB = AR6320V2_SI_CS_RX_CNT_LSB,
-	.d_SI_CS_RX_CNT_MASK = AR6320V2_SI_CS_RX_CNT_MASK,
-	.d_SI_CS_TX_CNT_LSB = AR6320V2_SI_CS_TX_CNT_LSB,
-	.d_SI_CS_TX_CNT_MASK = AR6320V2_SI_CS_TX_CNT_MASK,
-	.d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ,
-	.d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ,
-	.d_MBOX_BASE_ADDRESS = AR6320V2_MBOX_BASE_ADDRESS,
-	.d_LOCAL_SCRATCH_OFFSET = AR6320V2_LOCAL_SCRATCH_OFFSET,
-	.d_CPU_CLOCK_OFFSET = AR6320V2_CPU_CLOCK_OFFSET,
-	.d_LPO_CAL_OFFSET = AR6320V2_LPO_CAL_OFFSET,
-	.d_GPIO_PIN10_OFFSET = AR6320V2_GPIO_PIN10_OFFSET,
-	.d_GPIO_PIN11_OFFSET = AR6320V2_GPIO_PIN11_OFFSET,
-	.d_GPIO_PIN12_OFFSET = AR6320V2_GPIO_PIN12_OFFSET,
-	.d_GPIO_PIN13_OFFSET = AR6320V2_GPIO_PIN13_OFFSET,
-	.d_CLOCK_GPIO_OFFSET = AR6320V2_CLOCK_GPIO_OFFSET,
-	.d_CPU_CLOCK_STANDARD_LSB = AR6320V2_CPU_CLOCK_STANDARD_LSB,
-	.d_CPU_CLOCK_STANDARD_MASK = AR6320V2_CPU_CLOCK_STANDARD_MASK,
-	.d_LPO_CAL_ENABLE_LSB = AR6320V2_LPO_CAL_ENABLE_LSB,
-	.d_LPO_CAL_ENABLE_MASK = AR6320V2_LPO_CAL_ENABLE_MASK,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB =
-		AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
-		AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
-	.d_ANALOG_INTF_BASE_ADDRESS = AR6320V2_ANALOG_INTF_BASE_ADDRESS,
-	.d_WLAN_MAC_BASE_ADDRESS = AR6320V2_WLAN_MAC_BASE_ADDRESS,
-	.d_FW_INDICATOR_ADDRESS = AR6320V2_FW_INDICATOR_ADDRESS,
-	.d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS,
-	.d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS,
-	.d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS,
-	.d_CE_COUNT = AR6320V2_CE_COUNT,
-	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
-	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
-	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
-	.d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS,
-	.d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS,
-	.d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK,
-	.d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL,
-	.d_CORE_CTRL_CPU_INTR_MASK = AR6320V2_CORE_CTRL_CPU_INTR_MASK,
-	.d_SR_WR_INDEX_ADDRESS = AR6320V2_SR_WR_INDEX_ADDRESS,
-	.d_DST_WATERMARK_ADDRESS = AR6320V2_DST_WATERMARK_ADDRESS,
-	/* htt_rx.c */
-	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
-		AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK,
-	.d_RX_MSDU_END_4_FIRST_MSDU_LSB =
-		AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB,
-    .d_RX_MPDU_START_0_RETRY_MASK =
-		AR6320V2_RX_MPDU_START_0_RETRY_MASK,
-    .d_RX_MPDU_START_0_SEQ_NUM_MASK =
-		AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_MASK =
-		AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_LSB =
-		AR6320V2_RX_MPDU_START_2_PN_47_32_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_MASK =
-		AR6320V2_RX_MPDU_START_2_PN_47_32_MASK,
-    .d_RX_MPDU_START_2_TID_LSB =
-		AR6320V2_RX_MPDU_START_2_TID_LSB,
-    .d_RX_MPDU_START_2_TID_MASK =
-		AR6320V2_RX_MPDU_START_2_TID_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
-		AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
-		AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
-	.d_RX_MSDU_END_4_LAST_MSDU_MASK =
-		AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK,
-	.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB,
-	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
-		AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK,
-	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
-		AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB,
-	.d_RX_ATTENTION_0_FRAGMENT_MASK =
-		AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK,
-	.d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB,
-	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
-		AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
-		AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
-		AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
-		AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
-		AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
-		AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
-		AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
-		AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB,
-	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
-		AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK,
-	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
-		AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB,
-	.d_RX_ATTENTION_0_MORE_DATA_MASK =
-		AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK,
-	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
-		AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK,
-	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
-		AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-	/* PLL start */
-	.d_EFUSE_OFFSET = AR6320V2_EFUSE_OFFSET,
-	.d_EFUSE_XTAL_SEL_MSB = AR6320V2_EFUSE_XTAL_SEL_MSB,
-	.d_EFUSE_XTAL_SEL_LSB = AR6320V2_EFUSE_XTAL_SEL_LSB,
-	.d_EFUSE_XTAL_SEL_MASK = AR6320V2_EFUSE_XTAL_SEL_MASK,
-	.d_BB_PLL_CONFIG_OFFSET = AR6320V2_BB_PLL_CONFIG_OFFSET,
-	.d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB,
-	.d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB,
-	.d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK,
-	.d_BB_PLL_CONFIG_FRAC_MSB = AR6320V2_BB_PLL_CONFIG_FRAC_MSB,
-	.d_BB_PLL_CONFIG_FRAC_LSB = AR6320V2_BB_PLL_CONFIG_FRAC_LSB,
-	.d_BB_PLL_CONFIG_FRAC_MASK = AR6320V2_BB_PLL_CONFIG_FRAC_MASK,
-	.d_WLAN_PLL_SETTLE_TIME_MSB = AR6320V2_WLAN_PLL_SETTLE_TIME_MSB,
-	.d_WLAN_PLL_SETTLE_TIME_LSB = AR6320V2_WLAN_PLL_SETTLE_TIME_LSB,
-	.d_WLAN_PLL_SETTLE_TIME_MASK = AR6320V2_WLAN_PLL_SETTLE_TIME_MASK,
-	.d_WLAN_PLL_SETTLE_OFFSET = AR6320V2_WLAN_PLL_SETTLE_OFFSET,
-	.d_WLAN_PLL_SETTLE_SW_MASK = AR6320V2_WLAN_PLL_SETTLE_SW_MASK,
-	.d_WLAN_PLL_SETTLE_RSTMASK = AR6320V2_WLAN_PLL_SETTLE_RSTMASK,
-	.d_WLAN_PLL_SETTLE_RESET = AR6320V2_WLAN_PLL_SETTLE_RESET,
-	.d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_MASK =
-		AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
-		AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB =
-		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB =
-		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
-		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
-		AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET,
-	.d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_MASK =
-		AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK,
-	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
-		AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET,
-	.d_WLAN_PLL_CONTROL_DIV_MSB = AR6320V2_WLAN_PLL_CONTROL_DIV_MSB,
-	.d_WLAN_PLL_CONTROL_DIV_LSB = AR6320V2_WLAN_PLL_CONTROL_DIV_LSB,
-	.d_WLAN_PLL_CONTROL_DIV_MASK = AR6320V2_WLAN_PLL_CONTROL_DIV_MASK,
-	.d_WLAN_PLL_CONTROL_DIV_RESET = AR6320V2_WLAN_PLL_CONTROL_DIV_RESET,
-	.d_WLAN_PLL_CONTROL_OFFSET = AR6320V2_WLAN_PLL_CONTROL_OFFSET,
-	.d_WLAN_PLL_CONTROL_SW_MASK = AR6320V2_WLAN_PLL_CONTROL_SW_MASK,
-	.d_WLAN_PLL_CONTROL_RSTMASK = AR6320V2_WLAN_PLL_CONTROL_RSTMASK,
-	.d_WLAN_PLL_CONTROL_RESET = AR6320V2_WLAN_PLL_CONTROL_RESET,
-	.d_SOC_CORE_CLK_CTRL_OFFSET = AR6320V2_SOC_CORE_CLK_CTRL_OFFSET,
-	.d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
-		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
-		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
-		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
-		AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
-	.d_RTC_SYNC_STATUS_OFFSET = AR6320V2_RTC_SYNC_STATUS_OFFSET,
-	.d_SOC_CPU_CLOCK_OFFSET = AR6320V2_SOC_CPU_CLOCK_OFFSET,
-	.d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB,
-	.d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB,
-	.d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK,
-	/* PLL end */
-	.d_SOC_POWER_REG_OFFSET = AR6320V2_SOC_POWER_REG_OFFSET,
-	.d_PCIE_INTR_CAUSE_ADDRESS = AR6320V2_PCIE_INTR_CAUSE_ADDRESS,
-	.d_SOC_RESET_CONTROL_ADDRESS = AR6320V2_SOC_RESET_CONTROL_ADDRESS,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
-		AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
-		AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
-	.d_SOC_RESET_CONTROL_CE_RST_MASK =
-		AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK,
-	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
-		AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
-	.d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
-		AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
-		AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
-	/* chip id start */
-	.d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS,
-	.d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK,
-	.d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB,
-	.d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK,
-	.d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB,
-	/* chip id end */
-
-	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB =
-		AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB =
-		AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
-		AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
-	.d_WLAN_DEBUG_CONTROL_OFFSET = AR6320V2_WLAN_DEBUG_CONTROL_OFFSET,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
-		AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
-		AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
-		AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK,
-	.d_WLAN_DEBUG_OUT_OFFSET = AR6320V2_WLAN_DEBUG_OUT_OFFSET,
-	.d_WLAN_DEBUG_OUT_DATA_MSB = AR6320V2_WLAN_DEBUG_OUT_DATA_MSB,
-	.d_WLAN_DEBUG_OUT_DATA_LSB = AR6320V2_WLAN_DEBUG_OUT_DATA_LSB,
-	.d_WLAN_DEBUG_OUT_DATA_MASK = AR6320V2_WLAN_DEBUG_OUT_DATA_MASK,
-	.d_AMBA_DEBUG_BUS_OFFSET = AR6320V2_AMBA_DEBUG_BUS_OFFSET,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
-		AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
-		AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
-		AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
-	.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320V2_AMBA_DEBUG_BUS_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320V2_AMBA_DEBUG_BUS_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320V2_AMBA_DEBUG_BUS_SEL_MASK,
-};
-
-struct hostdef_s ar6320v2_hostdef = {
-	.d_INT_STATUS_ENABLE_ERROR_LSB = AR6320V2_INT_STATUS_ENABLE_ERROR_LSB,
-	.d_INT_STATUS_ENABLE_ERROR_MASK =
-		AR6320V2_INT_STATUS_ENABLE_ERROR_MASK,
-	.d_INT_STATUS_ENABLE_CPU_LSB = AR6320V2_INT_STATUS_ENABLE_CPU_LSB,
-	.d_INT_STATUS_ENABLE_CPU_MASK = AR6320V2_INT_STATUS_ENABLE_CPU_MASK,
-	.d_INT_STATUS_ENABLE_COUNTER_LSB =
-		AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB,
-	.d_INT_STATUS_ENABLE_COUNTER_MASK =
-		AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
-		AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
-		AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
-		AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
-		AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
-		AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
-		AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
-		AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
-		AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
-	.d_INT_STATUS_ENABLE_ADDRESS = AR6320V2_INT_STATUS_ENABLE_ADDRESS,
-	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
-		AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB,
-	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
-		AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK,
-	.d_HOST_INT_STATUS_ADDRESS = AR6320V2_HOST_INT_STATUS_ADDRESS,
-	.d_CPU_INT_STATUS_ADDRESS = AR6320V2_CPU_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_ADDRESS = AR6320V2_ERROR_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_WAKEUP_MASK =
-		AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK,
-	.d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
-		AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
-		AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
-		AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
-		AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
-	.d_COUNT_DEC_ADDRESS = AR6320V2_COUNT_DEC_ADDRESS,
-	.d_HOST_INT_STATUS_CPU_MASK = AR6320V2_HOST_INT_STATUS_CPU_MASK,
-	.d_HOST_INT_STATUS_CPU_LSB = AR6320V2_HOST_INT_STATUS_CPU_LSB,
-	.d_HOST_INT_STATUS_ERROR_MASK = AR6320V2_HOST_INT_STATUS_ERROR_MASK,
-	.d_HOST_INT_STATUS_ERROR_LSB = AR6320V2_HOST_INT_STATUS_ERROR_LSB,
-	.d_HOST_INT_STATUS_COUNTER_MASK =
-		AR6320V2_HOST_INT_STATUS_COUNTER_MASK,
-	.d_HOST_INT_STATUS_COUNTER_LSB = AR6320V2_HOST_INT_STATUS_COUNTER_LSB,
-	.d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS,
-	.d_WINDOW_DATA_ADDRESS = AR6320V2_WINDOW_DATA_ADDRESS,
-	.d_WINDOW_READ_ADDR_ADDRESS = AR6320V2_WINDOW_READ_ADDR_ADDRESS,
-	.d_WINDOW_WRITE_ADDR_ADDRESS = AR6320V2_WINDOW_WRITE_ADDR_ADDRESS,
-	.d_SOC_GLOBAL_RESET_ADDRESS = AR6320V2_SOC_GLOBAL_RESET_ADDRESS,
-	.d_RTC_STATE_ADDRESS = AR6320V2_RTC_STATE_ADDRESS,
-	.d_RTC_STATE_COLD_RESET_MASK = AR6320V2_RTC_STATE_COLD_RESET_MASK,
-	.d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS,
-	.d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET,
-	.d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS,
-	.d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK,
-	.d_RTC_STATE_V_MASK = AR6320V2_RTC_STATE_V_MASK,
-	.d_RTC_STATE_V_LSB = AR6320V2_RTC_STATE_V_LSB,
-	.d_FW_IND_EVENT_PENDING = AR6320V2_FW_IND_EVENT_PENDING,
-	.d_FW_IND_INITIALIZED = AR6320V2_FW_IND_INITIALIZED,
-	.d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER,
-	.d_RTC_STATE_V_ON = AR6320V2_RTC_STATE_V_ON,
-	.d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK,
-	.d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK,
-#if defined(SDIO_3_0)
-	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
-		AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK,
-	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
-		AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB,
-#endif
-	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
-	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
-	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
-	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
-	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
-	.d_HOST_CE_COUNT = 8,
-	.d_ENABLE_MSI = 0,
-};
-
-struct ce_reg_def ar6320v2_ce_targetdef = {
-	/* copy_engine.c  */
-	.d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS,
-	.d_SRC_WATERMARK_ADDRESS = AR6320V2_SRC_WATERMARK_ADDRESS,
-	.d_SRC_WATERMARK_LOW_MASK = AR6320V2_SRC_WATERMARK_LOW_MASK,
-	.d_SRC_WATERMARK_HIGH_MASK = AR6320V2_SRC_WATERMARK_HIGH_MASK,
-	.d_DST_WATERMARK_LOW_MASK = AR6320V2_DST_WATERMARK_LOW_MASK,
-	.d_DST_WATERMARK_HIGH_MASK = AR6320V2_DST_WATERMARK_HIGH_MASK,
-	.d_CURRENT_SRRI_ADDRESS = AR6320V2_CURRENT_SRRI_ADDRESS,
-	.d_CURRENT_DRRI_ADDRESS = AR6320V2_CURRENT_DRRI_ADDRESS,
-	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
-		AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
-		AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
-		AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
-		AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_ADDRESS = AR6320V2_HOST_IS_ADDRESS,
-	.d_HOST_IS_COPY_COMPLETE_MASK = AR6320V2_HOST_IS_COPY_COMPLETE_MASK,
-	.d_CE_WRAPPER_BASE_ADDRESS = AR6320V2_CE_WRAPPER_BASE_ADDRESS,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
-		AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
-	.d_HOST_IE_ADDRESS = AR6320V2_HOST_IE_ADDRESS,
-	.d_HOST_IE_COPY_COMPLETE_MASK = AR6320V2_HOST_IE_COPY_COMPLETE_MASK,
-	.d_SR_BA_ADDRESS = AR6320V2_SR_BA_ADDRESS,
-	.d_SR_SIZE_ADDRESS = AR6320V2_SR_SIZE_ADDRESS,
-	.d_CE_CTRL1_ADDRESS = AR6320V2_CE_CTRL1_ADDRESS,
-	.d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK,
-	.d_DR_BA_ADDRESS = AR6320V2_DR_BA_ADDRESS,
-	.d_DR_SIZE_ADDRESS = AR6320V2_DR_SIZE_ADDRESS,
-	.d_MISC_IE_ADDRESS = AR6320V2_MISC_IE_ADDRESS,
-	.d_MISC_IS_AXI_ERR_MASK = AR6320V2_MISC_IS_AXI_ERR_MASK,
-	.d_MISC_IS_DST_ADDR_ERR_MASK = AR6320V2_MISC_IS_DST_ADDR_ERR_MASK,
-	.d_MISC_IS_SRC_LEN_ERR_MASK = AR6320V2_MISC_IS_SRC_LEN_ERR_MASK,
-	.d_MISC_IS_DST_MAX_LEN_VIO_MASK =
-		AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK,
-	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
-		AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK,
-	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
-		AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK,
-	.d_SRC_WATERMARK_LOW_LSB = AR6320V2_SRC_WATERMARK_LOW_LSB,
-	.d_SRC_WATERMARK_HIGH_LSB = AR6320V2_SRC_WATERMARK_HIGH_LSB,
-	.d_DST_WATERMARK_LOW_LSB = AR6320V2_DST_WATERMARK_LOW_LSB,
-	.d_DST_WATERMARK_HIGH_LSB = AR6320V2_DST_WATERMARK_HIGH_LSB,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
-		AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
-		AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
-	.d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
-		AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
-		AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
-		AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
-		AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_WRAPPER_DEBUG_OFFSET = AR6320V2_CE_WRAPPER_DEBUG_OFFSET,
-	.d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB,
-	.d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB,
-	.d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK,
-	.d_CE_DEBUG_OFFSET = AR6320V2_CE_DEBUG_OFFSET,
-	.d_CE_DEBUG_SEL_MSB = AR6320V2_CE_DEBUG_SEL_MSB,
-	.d_CE_DEBUG_SEL_LSB = AR6320V2_CE_DEBUG_SEL_LSB,
-	.d_CE_DEBUG_SEL_MASK = AR6320V2_CE_DEBUG_SEL_MASK,
-	.d_CE0_BASE_ADDRESS = AR6320V2_CE0_BASE_ADDRESS,
-	.d_CE1_BASE_ADDRESS = AR6320V2_CE1_BASE_ADDRESS,
-
-};
-
-#endif

core/hif/src/ar9888def.h

@@ -1,590 +0,0 @@
-/*
- * Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _AR9888DEF_H_
-#define AR9888__AR9888DEF_H_
-
-/* Base Addresses */
-#define AR9888_RTC_SOC_BASE_ADDRESS                     0x00004000
-#define AR9888_RTC_WMAC_BASE_ADDRESS                    0x00005000
-#define AR9888_MAC_COEX_BASE_ADDRESS                    0x00006000
-#define AR9888_BT_COEX_BASE_ADDRESS                     0x00007000
-#define AR9888_SOC_PCIE_BASE_ADDRESS                    0x00008000
-#define AR9888_SOC_CORE_BASE_ADDRESS                    0x00009000
-#define AR9888_WLAN_UART_BASE_ADDRESS                   0x0000c000
-#define AR9888_WLAN_SI_BASE_ADDRESS                     0x00010000
-#define AR9888_WLAN_GPIO_BASE_ADDRESS                   0x00014000
-#define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS            0x0001c000
-#define AR9888_WLAN_MAC_BASE_ADDRESS                    0x00020000
-#define AR9888_EFUSE_BASE_ADDRESS                       0x00030000
-#define AR9888_FPGA_REG_BASE_ADDRESS                    0x00039000
-#define AR9888_WLAN_UART2_BASE_ADDRESS                  0x00054c00
-#define AR9888_CE_WRAPPER_BASE_ADDRESS                  0x00057000
-#define AR9888_CE0_BASE_ADDRESS                         0x00057400
-#define AR9888_CE1_BASE_ADDRESS                         0x00057800
-#define AR9888_CE2_BASE_ADDRESS                         0x00057c00
-#define AR9888_CE3_BASE_ADDRESS                         0x00058000
-#define AR9888_CE4_BASE_ADDRESS                         0x00058400
-#define AR9888_CE5_BASE_ADDRESS                         0x00058800
-#define AR9888_CE6_BASE_ADDRESS                         0x00058c00
-#define AR9888_CE7_BASE_ADDRESS                         0x00059000
-#define AR9888_DBI_BASE_ADDRESS                         0x00060000
-#define AR9888_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS       0x0006c000
-
-#define AR9888_SCRATCH_3_ADDRESS                        0x0030
-#define AR9888_TARG_DRAM_START                          0x00400000
-#define AR9888_SOC_SYSTEM_SLEEP_OFFSET                  0x000000c4
-#define AR9888_SOC_RESET_CONTROL_OFFSET                 0x00000000
-#define AR9888_SOC_CLOCK_CONTROL_OFFSET                 0x00000028
-#define AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
-#define AR9888_SOC_RESET_CONTROL_SI0_RST_MASK           0x00000001
-#define AR9888_WLAN_GPIO_BASE_ADDRESS                   0x00014000
-#define AR9888_WLAN_GPIO_PIN0_ADDRESS                   0x00000028
-#define AR9888_WLAN_GPIO_PIN1_ADDRESS                   0x0000002c
-#define AR9888_WLAN_GPIO_PIN0_CONFIG_MASK               0x00007800
-#define AR9888_WLAN_GPIO_PIN1_CONFIG_MASK               0x00007800
-#define AR9888_WLAN_SI_BASE_ADDRESS                     0x00010000
-#define AR9888_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define AR9888_SOC_LPO_CAL_OFFSET                       0x000000e0
-#define AR9888_WLAN_GPIO_PIN10_ADDRESS                  0x00000050
-#define AR9888_WLAN_GPIO_PIN11_ADDRESS                  0x00000054
-#define AR9888_WLAN_GPIO_PIN12_ADDRESS                  0x00000058
-#define AR9888_WLAN_GPIO_PIN13_ADDRESS                  0x0000005c
-#define AR9888_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define AR9888_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-#define AR9888_SOC_LPO_CAL_ENABLE_LSB                   20
-#define AR9888_SOC_LPO_CAL_ENABLE_MASK                  0x00100000
-#define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS            0x0001c000
-
-#define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB            0
-#define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK           0x00000001
-#define AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK         0x00000008
-#define AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK         0x00000004
-#define AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB              18
-#define AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK             0x00040000
-#define AR9888_SI_CONFIG_I2C_LSB                        16
-#define AR9888_SI_CONFIG_I2C_MASK                       0x00010000
-#define AR9888_SI_CONFIG_POS_SAMPLE_LSB                 7
-#define AR9888_SI_CONFIG_POS_SAMPLE_MASK                0x00000080
-#define AR9888_SI_CONFIG_INACTIVE_CLK_LSB               4
-#define AR9888_SI_CONFIG_INACTIVE_CLK_MASK              0x00000010
-#define AR9888_SI_CONFIG_INACTIVE_DATA_LSB              5
-#define AR9888_SI_CONFIG_INACTIVE_DATA_MASK             0x00000020
-#define AR9888_SI_CONFIG_DIVIDER_LSB                    0
-#define AR9888_SI_CONFIG_DIVIDER_MASK                   0x0000000f
-#define AR9888_SI_CONFIG_OFFSET                         0x00000000
-#define AR9888_SI_TX_DATA0_OFFSET                       0x00000008
-#define AR9888_SI_TX_DATA1_OFFSET                       0x0000000c
-#define AR9888_SI_RX_DATA0_OFFSET                       0x00000010
-#define AR9888_SI_RX_DATA1_OFFSET                       0x00000014
-#define AR9888_SI_CS_OFFSET                             0x00000004
-#define AR9888_SI_CS_DONE_ERR_MASK                      0x00000400
-#define AR9888_SI_CS_DONE_INT_MASK                      0x00000200
-#define AR9888_SI_CS_START_LSB                          8
-#define AR9888_SI_CS_START_MASK                         0x00000100
-#define AR9888_SI_CS_RX_CNT_LSB                         4
-#define AR9888_SI_CS_RX_CNT_MASK                        0x000000f0
-#define AR9888_SI_CS_TX_CNT_LSB                         0
-#define AR9888_SI_CS_TX_CNT_MASK                        0x0000000f
-#define AR9888_CE_COUNT                                 8
-#define AR9888_SR_WR_INDEX_ADDRESS                      0x003c
-#define AR9888_DST_WATERMARK_ADDRESS                    0x0050
-#define AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB             14
-#define AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK            0x00004000
-#define AR9888_RX_MPDU_START_0_SEQ_NUM_LSB              16
-#define AR9888_RX_MPDU_START_0_SEQ_NUM_MASK             0x0fff0000
-#define AR9888_RX_MPDU_START_2_PN_47_32_LSB             0
-#define AR9888_RX_MPDU_START_2_PN_47_32_MASK            0x0000ffff
-#define AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK            0x000000ff
-#define AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB             0
-#define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB      16
-#define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK     0xffff0000
-#define AR9888_RX_MSDU_END_4_LAST_MSDU_LSB              15
-#define AR9888_RX_MSDU_END_4_LAST_MSDU_MASK             0x00008000
-#define AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB           2
-#define AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK          0x00000004
-#define AR9888_RX_ATTENTION_0_FRAGMENT_LSB              13
-#define AR9888_RX_ATTENTION_0_FRAGMENT_MASK             0x00002000
-#define AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK      0x08000000
-#define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB      16
-#define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK     0x00ff0000
-#define AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB          0
-#define AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK         0x00003fff
-#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET      0x00000008
-#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB         8
-#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK        0x00000300
-#define AR9888_RX_MPDU_START_0_ENCRYPTED_LSB            13
-#define AR9888_RX_MPDU_START_0_ENCRYPTED_MASK           0x00002000
-#define AR9888_RX_ATTENTION_0_MORE_DATA_MASK            0x00000400
-#define AR9888_RX_ATTENTION_0_MSDU_DONE_MASK            0x80000000
-#define AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK  0x00040000
-#define AR9888_DST_WR_INDEX_ADDRESS                     0x0040
-#define AR9888_SRC_WATERMARK_ADDRESS                    0x004c
-#define AR9888_SRC_WATERMARK_LOW_MASK                   0xffff0000
-#define AR9888_SRC_WATERMARK_HIGH_MASK                  0x0000ffff
-#define AR9888_DST_WATERMARK_LOW_MASK                   0xffff0000
-#define AR9888_DST_WATERMARK_HIGH_MASK                  0x0000ffff
-#define AR9888_CURRENT_SRRI_ADDRESS                     0x0044
-#define AR9888_CURRENT_DRRI_ADDRESS                     0x0048
-#define AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK     0x00000002
-#define AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK      0x00000004
-#define AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK     0x00000008
-#define AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK      0x00000010
-#define AR9888_HOST_IS_ADDRESS                          0x0030
-#define AR9888_HOST_IS_COPY_COMPLETE_MASK               0x00000001
-#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS     0x0000
-#define AR9888_HOST_IE_ADDRESS                          0x002c
-#define AR9888_HOST_IE_COPY_COMPLETE_MASK               0x00000001
-#define AR9888_SR_BA_ADDRESS                            0x0000
-#define AR9888_SR_SIZE_ADDRESS                          0x0004
-#define AR9888_CE_CTRL1_ADDRESS                         0x0010
-#define AR9888_CE_CTRL1_DMAX_LENGTH_MASK                0x0000ffff
-#define AR9888_DR_BA_ADDRESS                            0x0008
-#define AR9888_DR_SIZE_ADDRESS                          0x000c
-#define AR9888_MISC_IE_ADDRESS                          0x0034
-#define AR9888_MISC_IS_AXI_ERR_MASK                     0x00000400
-#define AR9888_MISC_IS_DST_ADDR_ERR_MASK                0x00000200
-#define AR9888_MISC_IS_SRC_LEN_ERR_MASK                 0x00000100
-#define AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK             0x00000080
-#define AR9888_MISC_IS_DST_RING_OVERFLOW_MASK           0x00000040
-#define AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK           0x00000020
-#define AR9888_SRC_WATERMARK_LOW_LSB                    16
-#define AR9888_SRC_WATERMARK_HIGH_LSB                   0
-#define AR9888_DST_WATERMARK_LOW_LSB                    16
-#define AR9888_DST_WATERMARK_HIGH_LSB                   0
-#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
-#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  8
-#define AR9888_CE_CTRL1_DMAX_LENGTH_LSB                 0
-#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK      0x00010000
-#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK      0x00020000
-#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB       16
-#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB       17
-#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004
-#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB  2
-#define AR9888_SOC_GLOBAL_RESET_ADDRESS                 0x0008
-#define AR9888_RTC_STATE_ADDRESS                        0x0000
-#define AR9888_RTC_STATE_COLD_RESET_MASK                0x00000400
-#define AR9888_PCIE_SOC_WAKE_RESET                      0x00000000
-#define AR9888_PCIE_SOC_WAKE_ADDRESS                    0x0004
-#define AR9888_PCIE_SOC_WAKE_V_MASK                     0x00000001
-#define AR9888_RTC_STATE_V_MASK                         0x00000007
-#define AR9888_RTC_STATE_V_LSB                          0
-#define AR9888_RTC_STATE_V_ON                           3
-#define AR9888_MUX_ID_MASK                              0x0000
-#define AR9888_TRANSACTION_ID_MASK                      0x3fff
-#define AR9888_PCIE_LOCAL_BASE_ADDRESS                  0x80000
-#define AR9888_FW_IND_EVENT_PENDING                     1
-#define AR9888_FW_IND_INITIALIZED                       2
-#define AR9888_PCIE_INTR_ENABLE_ADDRESS                 0x0008
-#define AR9888_PCIE_INTR_CLR_ADDRESS                    0x0014
-#define AR9888_PCIE_INTR_FIRMWARE_MASK                  0x00000400
-#define AR9888_PCIE_INTR_CE0_MASK                       0x00000800
-#define AR9888_PCIE_INTR_CE_MASK_ALL                    0x0007f800
-#define AR9888_PCIE_INTR_CAUSE_ADDRESS                  0x000c
-#define AR9888_CPU_INTR_ADDRESS                         0x0010
-#define AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
-#define AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
-#define AR9888_SOC_RESET_CONTROL_ADDRESS                0x00000000
-#define AR9888_SOC_RESET_CONTROL_CE_RST_MASK            0x00040000
-#define AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
-#define AR9888_CORE_CTRL_ADDRESS                        0x0000
-#define AR9888_CORE_CTRL_CPU_INTR_MASK                  0x00002000
-#define AR9888_LOCAL_SCRATCH_OFFSET                     0x18
-#define AR9888_CLOCK_GPIO_OFFSET                        0xffffffff
-#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
-#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
-
-#define AR9888_PCIE_INTR_CE_MASK(n) (AR9888_PCIE_INTR_CE0_MASK << (n))
-#define AR9888_FW_EVENT_PENDING_ADDRESS \
-	(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)
-#define AR9888_DRAM_BASE_ADDRESS AR9888_TARG_DRAM_START
-#define AR9888_FW_INDICATOR_ADDRESS \
-	(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)
-#define AR9888_SYSTEM_SLEEP_OFFSET        AR9888_SOC_SYSTEM_SLEEP_OFFSET
-#define AR9888_WLAN_SYSTEM_SLEEP_OFFSET   AR9888_SOC_SYSTEM_SLEEP_OFFSET
-#define AR9888_WLAN_RESET_CONTROL_OFFSET  AR9888_SOC_RESET_CONTROL_OFFSET
-#define AR9888_CLOCK_CONTROL_OFFSET       AR9888_SOC_CLOCK_CONTROL_OFFSET
-#define AR9888_CLOCK_CONTROL_SI0_CLK_MASK AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK
-#define AR9888_RESET_CONTROL_MBOX_RST_MASK MISSING
-#define AR9888_RESET_CONTROL_SI0_RST_MASK AR9888_SOC_RESET_CONTROL_SI0_RST_MASK
-#define AR9888_GPIO_BASE_ADDRESS          AR9888_WLAN_GPIO_BASE_ADDRESS
-#define AR9888_GPIO_PIN0_OFFSET           AR9888_WLAN_GPIO_PIN0_ADDRESS
-#define AR9888_GPIO_PIN1_OFFSET           AR9888_WLAN_GPIO_PIN1_ADDRESS
-#define AR9888_GPIO_PIN0_CONFIG_MASK      AR9888_WLAN_GPIO_PIN0_CONFIG_MASK
-#define AR9888_GPIO_PIN1_CONFIG_MASK      AR9888_WLAN_GPIO_PIN1_CONFIG_MASK
-#define AR9888_SI_BASE_ADDRESS            AR9888_WLAN_SI_BASE_ADDRESS
-#define AR9888_SCRATCH_BASE_ADDRESS       AR9888_SOC_CORE_BASE_ADDRESS
-#define AR9888_CPU_CLOCK_OFFSET           AR9888_SOC_CPU_CLOCK_OFFSET
-#define AR9888_LPO_CAL_OFFSET             AR9888_SOC_LPO_CAL_OFFSET
-#define AR9888_GPIO_PIN10_OFFSET          AR9888_WLAN_GPIO_PIN10_ADDRESS
-#define AR9888_GPIO_PIN11_OFFSET          AR9888_WLAN_GPIO_PIN11_ADDRESS
-#define AR9888_GPIO_PIN12_OFFSET          AR9888_WLAN_GPIO_PIN12_ADDRESS
-#define AR9888_GPIO_PIN13_OFFSET          AR9888_WLAN_GPIO_PIN13_ADDRESS
-#define AR9888_CPU_CLOCK_STANDARD_LSB     AR9888_SOC_CPU_CLOCK_STANDARD_LSB
-#define AR9888_CPU_CLOCK_STANDARD_MASK    AR9888_SOC_CPU_CLOCK_STANDARD_MASK
-#define AR9888_LPO_CAL_ENABLE_LSB         AR9888_SOC_LPO_CAL_ENABLE_LSB
-#define AR9888_LPO_CAL_ENABLE_MASK        AR9888_SOC_LPO_CAL_ENABLE_MASK
-#define AR9888_ANALOG_INTF_BASE_ADDRESS   AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS
-#define AR9888_MBOX_BASE_ADDRESS                       MISSING
-#define AR9888_INT_STATUS_ENABLE_ERROR_LSB             MISSING
-#define AR9888_INT_STATUS_ENABLE_ERROR_MASK            MISSING
-#define AR9888_INT_STATUS_ENABLE_CPU_LSB               MISSING
-#define AR9888_INT_STATUS_ENABLE_CPU_MASK              MISSING
-#define AR9888_INT_STATUS_ENABLE_COUNTER_LSB           MISSING
-#define AR9888_INT_STATUS_ENABLE_COUNTER_MASK          MISSING
-#define AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
-#define AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
-#define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
-#define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
-#define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
-#define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
-#define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
-#define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
-#define AR9888_INT_STATUS_ENABLE_ADDRESS               MISSING
-#define AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
-#define AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
-#define AR9888_HOST_INT_STATUS_ADDRESS                 MISSING
-#define AR9888_CPU_INT_STATUS_ADDRESS                  MISSING
-#define AR9888_ERROR_INT_STATUS_ADDRESS                MISSING
-#define AR9888_ERROR_INT_STATUS_WAKEUP_MASK            MISSING
-#define AR9888_ERROR_INT_STATUS_WAKEUP_LSB             MISSING
-#define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
-#define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
-#define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
-#define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
-#define AR9888_COUNT_DEC_ADDRESS                       MISSING
-#define AR9888_HOST_INT_STATUS_CPU_MASK                MISSING
-#define AR9888_HOST_INT_STATUS_CPU_LSB                 MISSING
-#define AR9888_HOST_INT_STATUS_ERROR_MASK              MISSING
-#define AR9888_HOST_INT_STATUS_ERROR_LSB               MISSING
-#define AR9888_HOST_INT_STATUS_COUNTER_MASK            MISSING
-#define AR9888_HOST_INT_STATUS_COUNTER_LSB             MISSING
-#define AR9888_RX_LOOKAHEAD_VALID_ADDRESS              MISSING
-#define AR9888_WINDOW_DATA_ADDRESS                     MISSING
-#define AR9888_WINDOW_READ_ADDR_ADDRESS                MISSING
-#define AR9888_WINDOW_WRITE_ADDR_ADDRESS               MISSING
-
-struct targetdef_s ar9888_targetdef = {
-	.d_RTC_SOC_BASE_ADDRESS = AR9888_RTC_SOC_BASE_ADDRESS,
-	.d_RTC_WMAC_BASE_ADDRESS = AR9888_RTC_WMAC_BASE_ADDRESS,
-	.d_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
-		AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
-		AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
-	.d_CLOCK_CONTROL_OFFSET = AR9888_CLOCK_CONTROL_OFFSET,
-	.d_CLOCK_CONTROL_SI0_CLK_MASK = AR9888_CLOCK_CONTROL_SI0_CLK_MASK,
-	.d_RESET_CONTROL_OFFSET = AR9888_SOC_RESET_CONTROL_OFFSET,
-	.d_RESET_CONTROL_MBOX_RST_MASK = AR9888_RESET_CONTROL_MBOX_RST_MASK,
-	.d_RESET_CONTROL_SI0_RST_MASK = AR9888_RESET_CONTROL_SI0_RST_MASK,
-	.d_WLAN_RESET_CONTROL_OFFSET = AR9888_WLAN_RESET_CONTROL_OFFSET,
-	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
-		AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK,
-	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
-		AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK,
-	.d_GPIO_BASE_ADDRESS = AR9888_GPIO_BASE_ADDRESS,
-	.d_GPIO_PIN0_OFFSET = AR9888_GPIO_PIN0_OFFSET,
-	.d_GPIO_PIN1_OFFSET = AR9888_GPIO_PIN1_OFFSET,
-	.d_GPIO_PIN0_CONFIG_MASK = AR9888_GPIO_PIN0_CONFIG_MASK,
-	.d_GPIO_PIN1_CONFIG_MASK = AR9888_GPIO_PIN1_CONFIG_MASK,
-	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB,
-	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK,
-	.d_SI_CONFIG_I2C_LSB = AR9888_SI_CONFIG_I2C_LSB,
-	.d_SI_CONFIG_I2C_MASK = AR9888_SI_CONFIG_I2C_MASK,
-	.d_SI_CONFIG_POS_SAMPLE_LSB = AR9888_SI_CONFIG_POS_SAMPLE_LSB,
-	.d_SI_CONFIG_POS_SAMPLE_MASK = AR9888_SI_CONFIG_POS_SAMPLE_MASK,
-	.d_SI_CONFIG_INACTIVE_CLK_LSB = AR9888_SI_CONFIG_INACTIVE_CLK_LSB,
-	.d_SI_CONFIG_INACTIVE_CLK_MASK = AR9888_SI_CONFIG_INACTIVE_CLK_MASK,
-	.d_SI_CONFIG_INACTIVE_DATA_LSB = AR9888_SI_CONFIG_INACTIVE_DATA_LSB,
-	.d_SI_CONFIG_INACTIVE_DATA_MASK = AR9888_SI_CONFIG_INACTIVE_DATA_MASK,
-	.d_SI_CONFIG_DIVIDER_LSB = AR9888_SI_CONFIG_DIVIDER_LSB,
-	.d_SI_CONFIG_DIVIDER_MASK = AR9888_SI_CONFIG_DIVIDER_MASK,
-	.d_SI_BASE_ADDRESS = AR9888_SI_BASE_ADDRESS,
-	.d_SI_CONFIG_OFFSET = AR9888_SI_CONFIG_OFFSET,
-	.d_SI_TX_DATA0_OFFSET = AR9888_SI_TX_DATA0_OFFSET,
-	.d_SI_TX_DATA1_OFFSET = AR9888_SI_TX_DATA1_OFFSET,
-	.d_SI_RX_DATA0_OFFSET = AR9888_SI_RX_DATA0_OFFSET,
-	.d_SI_RX_DATA1_OFFSET = AR9888_SI_RX_DATA1_OFFSET,
-	.d_SI_CS_OFFSET = AR9888_SI_CS_OFFSET,
-	.d_SI_CS_DONE_ERR_MASK = AR9888_SI_CS_DONE_ERR_MASK,
-	.d_SI_CS_DONE_INT_MASK = AR9888_SI_CS_DONE_INT_MASK,
-	.d_SI_CS_START_LSB = AR9888_SI_CS_START_LSB,
-	.d_SI_CS_START_MASK = AR9888_SI_CS_START_MASK,
-	.d_SI_CS_RX_CNT_LSB = AR9888_SI_CS_RX_CNT_LSB,
-	.d_SI_CS_RX_CNT_MASK = AR9888_SI_CS_RX_CNT_MASK,
-	.d_SI_CS_TX_CNT_LSB = AR9888_SI_CS_TX_CNT_LSB,
-	.d_SI_CS_TX_CNT_MASK = AR9888_SI_CS_TX_CNT_MASK,
-	.d_BOARD_DATA_SZ = AR9888_BOARD_DATA_SZ,
-	.d_BOARD_EXT_DATA_SZ = AR9888_BOARD_EXT_DATA_SZ,
-	.d_MBOX_BASE_ADDRESS = AR9888_MBOX_BASE_ADDRESS,
-	.d_LOCAL_SCRATCH_OFFSET = AR9888_LOCAL_SCRATCH_OFFSET,
-	.d_CPU_CLOCK_OFFSET = AR9888_CPU_CLOCK_OFFSET,
-	.d_LPO_CAL_OFFSET = AR9888_LPO_CAL_OFFSET,
-	.d_GPIO_PIN10_OFFSET = AR9888_GPIO_PIN10_OFFSET,
-	.d_GPIO_PIN11_OFFSET = AR9888_GPIO_PIN11_OFFSET,
-	.d_GPIO_PIN12_OFFSET = AR9888_GPIO_PIN12_OFFSET,
-	.d_GPIO_PIN13_OFFSET = AR9888_GPIO_PIN13_OFFSET,
-	.d_CLOCK_GPIO_OFFSET = AR9888_CLOCK_GPIO_OFFSET,
-	.d_CPU_CLOCK_STANDARD_LSB = AR9888_CPU_CLOCK_STANDARD_LSB,
-	.d_CPU_CLOCK_STANDARD_MASK = AR9888_CPU_CLOCK_STANDARD_MASK,
-	.d_LPO_CAL_ENABLE_LSB = AR9888_LPO_CAL_ENABLE_LSB,
-	.d_LPO_CAL_ENABLE_MASK = AR9888_LPO_CAL_ENABLE_MASK,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
-		AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
-	.d_ANALOG_INTF_BASE_ADDRESS = AR9888_ANALOG_INTF_BASE_ADDRESS,
-	.d_WLAN_MAC_BASE_ADDRESS = AR9888_WLAN_MAC_BASE_ADDRESS,
-	.d_FW_INDICATOR_ADDRESS = AR9888_FW_INDICATOR_ADDRESS,
-	.d_DRAM_BASE_ADDRESS = AR9888_DRAM_BASE_ADDRESS,
-	.d_SOC_CORE_BASE_ADDRESS = AR9888_SOC_CORE_BASE_ADDRESS,
-	.d_CORE_CTRL_ADDRESS = AR9888_CORE_CTRL_ADDRESS,
-	.d_CE_COUNT = AR9888_CE_COUNT,
-	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
-	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
-	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
-	.d_PCIE_INTR_ENABLE_ADDRESS = AR9888_PCIE_INTR_ENABLE_ADDRESS,
-	.d_PCIE_INTR_CLR_ADDRESS = AR9888_PCIE_INTR_CLR_ADDRESS,
-	.d_PCIE_INTR_FIRMWARE_MASK = AR9888_PCIE_INTR_FIRMWARE_MASK,
-	.d_PCIE_INTR_CE_MASK_ALL = AR9888_PCIE_INTR_CE_MASK_ALL,
-	.d_CORE_CTRL_CPU_INTR_MASK = AR9888_CORE_CTRL_CPU_INTR_MASK,
-	.d_SR_WR_INDEX_ADDRESS = AR9888_SR_WR_INDEX_ADDRESS,
-	.d_DST_WATERMARK_ADDRESS = AR9888_DST_WATERMARK_ADDRESS,
-	/* htt_rx.c */
-	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
-		AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK,
-	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB,
-	.d_RX_MPDU_START_0_SEQ_NUM_MASK = AR9888_RX_MPDU_START_0_SEQ_NUM_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR9888_RX_MPDU_START_0_SEQ_NUM_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_LSB = AR9888_RX_MPDU_START_2_PN_47_32_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_MASK =
-		AR9888_RX_MPDU_START_2_PN_47_32_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
-		AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
-		AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
-	.d_RX_MSDU_END_1_KEY_ID_OCT_MASK =
-		AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK,
-	.d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB,
-	.d_RX_MSDU_END_4_LAST_MSDU_MASK = AR9888_RX_MSDU_END_4_LAST_MSDU_MASK,
-	.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR9888_RX_MSDU_END_4_LAST_MSDU_LSB,
-	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
-		AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK,
-	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
-		AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB,
-	.d_RX_ATTENTION_0_FRAGMENT_MASK = AR9888_RX_ATTENTION_0_FRAGMENT_MASK,
-	.d_RX_ATTENTION_0_FRAGMENT_LSB = AR9888_RX_ATTENTION_0_FRAGMENT_LSB,
-	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
-		AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
-		AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
-		AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
-		AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
-		AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
-		AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
-		AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
-		AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB,
-	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
-		AR9888_RX_MPDU_START_0_ENCRYPTED_MASK,
-	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
-		AR9888_RX_MPDU_START_0_ENCRYPTED_LSB,
-	.d_RX_ATTENTION_0_MORE_DATA_MASK =
-		AR9888_RX_ATTENTION_0_MORE_DATA_MASK,
-	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
-		AR9888_RX_ATTENTION_0_MSDU_DONE_MASK,
-	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
-		AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-
-	.d_PCIE_INTR_CAUSE_ADDRESS = AR9888_PCIE_INTR_CAUSE_ADDRESS,
-	.d_SOC_RESET_CONTROL_ADDRESS = AR9888_SOC_RESET_CONTROL_ADDRESS,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
-		AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
-		AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
-	.d_SOC_RESET_CONTROL_CE_RST_MASK =
-		AR9888_SOC_RESET_CONTROL_CE_RST_MASK,
-	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
-		AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
-	.d_CPU_INTR_ADDRESS = AR9888_CPU_INTR_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
-		AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
-		AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
-};
-
-struct hostdef_s ar9888_hostdef = {
-	.d_INT_STATUS_ENABLE_ERROR_LSB = AR9888_INT_STATUS_ENABLE_ERROR_LSB,
-	.d_INT_STATUS_ENABLE_ERROR_MASK = AR9888_INT_STATUS_ENABLE_ERROR_MASK,
-	.d_INT_STATUS_ENABLE_CPU_LSB = AR9888_INT_STATUS_ENABLE_CPU_LSB,
-	.d_INT_STATUS_ENABLE_CPU_MASK = AR9888_INT_STATUS_ENABLE_CPU_MASK,
-	.d_INT_STATUS_ENABLE_COUNTER_LSB =
-		AR9888_INT_STATUS_ENABLE_COUNTER_LSB,
-	.d_INT_STATUS_ENABLE_COUNTER_MASK =
-		AR9888_INT_STATUS_ENABLE_COUNTER_MASK,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
-		AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
-		AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
-		AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
-		AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
-		AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
-		AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
-		AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
-		AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
-	.d_INT_STATUS_ENABLE_ADDRESS = AR9888_INT_STATUS_ENABLE_ADDRESS,
-	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
-		AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB,
-	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
-		AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK,
-	.d_HOST_INT_STATUS_ADDRESS = AR9888_HOST_INT_STATUS_ADDRESS,
-	.d_CPU_INT_STATUS_ADDRESS = AR9888_CPU_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_ADDRESS = AR9888_ERROR_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_WAKEUP_MASK = AR9888_ERROR_INT_STATUS_WAKEUP_MASK,
-	.d_ERROR_INT_STATUS_WAKEUP_LSB = AR9888_ERROR_INT_STATUS_WAKEUP_LSB,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
-		AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
-		AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
-		AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
-		AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
-	.d_COUNT_DEC_ADDRESS = AR9888_COUNT_DEC_ADDRESS,
-	.d_HOST_INT_STATUS_CPU_MASK = AR9888_HOST_INT_STATUS_CPU_MASK,
-	.d_HOST_INT_STATUS_CPU_LSB = AR9888_HOST_INT_STATUS_CPU_LSB,
-	.d_HOST_INT_STATUS_ERROR_MASK = AR9888_HOST_INT_STATUS_ERROR_MASK,
-	.d_HOST_INT_STATUS_ERROR_LSB = AR9888_HOST_INT_STATUS_ERROR_LSB,
-	.d_HOST_INT_STATUS_COUNTER_MASK = AR9888_HOST_INT_STATUS_COUNTER_MASK,
-	.d_HOST_INT_STATUS_COUNTER_LSB = AR9888_HOST_INT_STATUS_COUNTER_LSB,
-	.d_RX_LOOKAHEAD_VALID_ADDRESS = AR9888_RX_LOOKAHEAD_VALID_ADDRESS,
-	.d_WINDOW_DATA_ADDRESS = AR9888_WINDOW_DATA_ADDRESS,
-	.d_WINDOW_READ_ADDR_ADDRESS = AR9888_WINDOW_READ_ADDR_ADDRESS,
-	.d_WINDOW_WRITE_ADDR_ADDRESS = AR9888_WINDOW_WRITE_ADDR_ADDRESS,
-	.d_SOC_GLOBAL_RESET_ADDRESS = AR9888_SOC_GLOBAL_RESET_ADDRESS,
-	.d_RTC_STATE_ADDRESS = AR9888_RTC_STATE_ADDRESS,
-	.d_RTC_STATE_COLD_RESET_MASK = AR9888_RTC_STATE_COLD_RESET_MASK,
-	.d_PCIE_LOCAL_BASE_ADDRESS = AR9888_PCIE_LOCAL_BASE_ADDRESS,
-	.d_PCIE_SOC_WAKE_RESET = AR9888_PCIE_SOC_WAKE_RESET,
-	.d_PCIE_SOC_WAKE_ADDRESS = AR9888_PCIE_SOC_WAKE_ADDRESS,
-	.d_PCIE_SOC_WAKE_V_MASK = AR9888_PCIE_SOC_WAKE_V_MASK,
-	.d_RTC_STATE_V_MASK = AR9888_RTC_STATE_V_MASK,
-	.d_RTC_STATE_V_LSB = AR9888_RTC_STATE_V_LSB,
-	.d_FW_IND_EVENT_PENDING = AR9888_FW_IND_EVENT_PENDING,
-	.d_FW_IND_INITIALIZED = AR9888_FW_IND_INITIALIZED,
-	.d_RTC_STATE_V_ON = AR9888_RTC_STATE_V_ON,
-	.d_MUX_ID_MASK = AR9888_MUX_ID_MASK,
-	.d_TRANSACTION_ID_MASK = AR9888_TRANSACTION_ID_MASK,
-#if defined(SDIO_3_0)
-	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
-		AR9888_HOST_INT_STATUS_MBOX_DATA_MASK,
-	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
-		AR9888_HOST_INT_STATUS_MBOX_DATA_LSB,
-#endif
-	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
-	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
-	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
-	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
-	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
-	.d_HOST_CE_COUNT = 8,
-	.d_ENABLE_MSI = 0,
-};
-
-
-struct ce_reg_def ar9888_ce_targetdef = {
-	/* copy_engine.c  */
-	.d_DST_WR_INDEX_ADDRESS = AR9888_DST_WR_INDEX_ADDRESS,
-	.d_SRC_WATERMARK_ADDRESS = AR9888_SRC_WATERMARK_ADDRESS,
-	.d_SRC_WATERMARK_LOW_MASK = AR9888_SRC_WATERMARK_LOW_MASK,
-	.d_SRC_WATERMARK_HIGH_MASK = AR9888_SRC_WATERMARK_HIGH_MASK,
-	.d_DST_WATERMARK_LOW_MASK = AR9888_DST_WATERMARK_LOW_MASK,
-	.d_DST_WATERMARK_HIGH_MASK = AR9888_DST_WATERMARK_HIGH_MASK,
-	.d_CURRENT_SRRI_ADDRESS = AR9888_CURRENT_SRRI_ADDRESS,
-	.d_CURRENT_DRRI_ADDRESS = AR9888_CURRENT_DRRI_ADDRESS,
-	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
-		AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
-		AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
-		AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
-		AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_ADDRESS = AR9888_HOST_IS_ADDRESS,
-	.d_HOST_IS_COPY_COMPLETE_MASK = AR9888_HOST_IS_COPY_COMPLETE_MASK,
-	.d_CE_WRAPPER_BASE_ADDRESS = AR9888_CE_WRAPPER_BASE_ADDRESS,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
-		AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
-	.d_HOST_IE_ADDRESS = AR9888_HOST_IE_ADDRESS,
-	.d_HOST_IE_COPY_COMPLETE_MASK = AR9888_HOST_IE_COPY_COMPLETE_MASK,
-	.d_SR_BA_ADDRESS = AR9888_SR_BA_ADDRESS,
-	.d_SR_SIZE_ADDRESS = AR9888_SR_SIZE_ADDRESS,
-	.d_CE_CTRL1_ADDRESS = AR9888_CE_CTRL1_ADDRESS,
-	.d_CE_CTRL1_DMAX_LENGTH_MASK = AR9888_CE_CTRL1_DMAX_LENGTH_MASK,
-	.d_DR_BA_ADDRESS = AR9888_DR_BA_ADDRESS,
-	.d_DR_SIZE_ADDRESS = AR9888_DR_SIZE_ADDRESS,
-	.d_MISC_IE_ADDRESS = AR9888_MISC_IE_ADDRESS,
-	.d_MISC_IS_AXI_ERR_MASK = AR9888_MISC_IS_AXI_ERR_MASK,
-	.d_MISC_IS_DST_ADDR_ERR_MASK = AR9888_MISC_IS_DST_ADDR_ERR_MASK,
-	.d_MISC_IS_SRC_LEN_ERR_MASK = AR9888_MISC_IS_SRC_LEN_ERR_MASK,
-	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK,
-	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
-		AR9888_MISC_IS_DST_RING_OVERFLOW_MASK,
-	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
-		AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK,
-	.d_SRC_WATERMARK_LOW_LSB = AR9888_SRC_WATERMARK_LOW_LSB,
-	.d_SRC_WATERMARK_HIGH_LSB = AR9888_SRC_WATERMARK_HIGH_LSB,
-	.d_DST_WATERMARK_LOW_LSB = AR9888_DST_WATERMARK_LOW_LSB,
-	.d_DST_WATERMARK_HIGH_LSB = AR9888_DST_WATERMARK_HIGH_LSB,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
-		AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
-		AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
-	.d_CE_CTRL1_DMAX_LENGTH_LSB = AR9888_CE_CTRL1_DMAX_LENGTH_LSB,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
-		AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
-		AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
-		AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
-		AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-	.d_CE0_BASE_ADDRESS = AR9888_CE0_BASE_ADDRESS,
-	.d_CE1_BASE_ADDRESS = AR9888_CE1_BASE_ADDRESS,
-
-};
-#endif

core/hif/src/ath_procfs.c

@@ -1,199 +0,0 @@
-/*
- * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#if defined(CONFIG_ATH_PROCFS_DIAG_SUPPORT)
-#include <linux/module.h>       /* Specifically, a module */
-#include <linux/kernel.h>       /* We're doing kernel work */
-#include <linux/version.h>      /* We're doing kernel work */
-#include <linux/proc_fs.h>      /* Necessary because we use the proc fs */
-#include <asm/uaccess.h>        /* for copy_from_user */
-#include "ol_if_athvar.h"
-#include "hif.h"
-#if defined(HIF_PCI)
-#include "if_pci.h"
-#elif defined(HIF_USB)
-#include "if_usb.h"
-#elif defined(HIF_SDIO)
-#include "if_ath_sdio.h"
-#endif
-#include "cds_api.h"
-#include "hif_debug.h"
-
-#define PROCFS_NAME             "athdiagpfs"
-#define PROCFS_DIR              "cld"
-
-/**
- * This structure hold information about the /proc file
- *
- */
-static struct proc_dir_entry *proc_file, *proc_dir;
-
-static void *get_hif_hdl_from_file(struct file *file)
-{
-	struct ol_softc *scn;
-
-	scn = (struct ol_softc *)PDE_DATA(file_inode(file));
-	return (void *)scn;
-}
-
-static ssize_t ath_procfs_diag_read(struct file *file, char __user *buf,
-				    size_t count, loff_t *pos)
-{
-	hif_handle_t hif_hdl;
-	int rv;
-	uint8_t *read_buffer = NULL;
-
-	read_buffer = cdf_mem_malloc(count);
-	if (NULL == read_buffer) {
-		HIF_ERROR("%s: cdf_mem_alloc failed", __func__);
-		return -ENOMEM;
-	}
-
-	hif_hdl = get_hif_hdl_from_file(file);
-	HIF_DBG("rd buff 0x%p cnt %zu offset 0x%x buf 0x%p",
-		 read_buffer, count, (int)*pos, buf);
-
-	if ((count == 4) && ((((uint32_t) (*pos)) & 3) == 0)) {
-		/* reading a word? */
-		rv = hif_diag_read_access(hif_hdl, (uint32_t)(*pos),
-					  (uint32_t *)read_buffer);
-	} else {
-		rv = hif_diag_read_mem(hif_hdl, (uint32_t)(*pos),
-				       (uint8_t *)read_buffer, count);
-	}
-
-	if (copy_to_user(buf, read_buffer, count)) {
-		cdf_mem_free(read_buffer);
-		HIF_ERROR("%s: copy_to_user error in /proc/%s",
-			__func__, PROCFS_NAME);
-		return -EFAULT;
-	} else
-		cdf_mem_free(read_buffer);
-
-	if (rv == 0) {
-		return count;
-	} else {
-		return -EIO;
-	}
-}
-
-static ssize_t ath_procfs_diag_write(struct file *file,
-				     const char __user *buf,
-				     size_t count, loff_t *pos)
-{
-	hif_handle_t hif_hdl;
-	int rv;
-	uint8_t *write_buffer = NULL;
-
-	write_buffer = cdf_mem_malloc(count);
-	if (NULL == write_buffer) {
-		HIF_ERROR("%s: cdf_mem_alloc failed", __func__);
-		return -ENOMEM;
-	}
-	if (copy_from_user(write_buffer, buf, count)) {
-		cdf_mem_free(write_buffer);
-		HIF_ERROR("%s: copy_to_user error in /proc/%s",
-			__func__, PROCFS_NAME);
-		return -EFAULT;
-	}
-
-	hif_hdl = get_hif_hdl_from_file(file);
-	HIF_DBG("wr buff 0x%p buf 0x%p cnt %zu offset 0x%x value 0x%x",
-		 write_buffer, buf, count,
-		 (int)*pos, *((uint32_t *) write_buffer));
-
-	if ((count == 4) && ((((uint32_t) (*pos)) & 3) == 0)) {
-		/* reading a word? */
-		uint32_t value = *((uint32_t *)write_buffer);
-		rv = hif_diag_write_access(hif_hdl, (uint32_t)(*pos), value);
-	} else {
-		rv = hif_diag_write_mem(hif_hdl, (uint32_t)(*pos),
-					(uint8_t *)write_buffer, count);
-	}
-
-	cdf_mem_free(write_buffer);
-	if (rv == 0) {
-		return count;
-	} else {
-		return -EIO;
-	}
-}
-
-static const struct file_operations athdiag_fops = {
-	.read = ath_procfs_diag_read,
-	.write = ath_procfs_diag_write,
-};
-
-/**
-   *This function is called when the module is loaded
- *
- */
-int athdiag_procfs_init(void *scn)
-{
-	proc_dir = proc_mkdir(PROCFS_DIR, NULL);
-	if (proc_dir == NULL) {
-		remove_proc_entry(PROCFS_DIR, NULL);
-		HIF_ERROR("%s: Error: Could not initialize /proc/%s",
-			__func__, PROCFS_DIR);
-		return -ENOMEM;
-	}
-
-	proc_file = proc_create_data(PROCFS_NAME,
-				     S_IRUSR | S_IWUSR, proc_dir,
-				     &athdiag_fops, (void *)scn);
-	if (proc_file == NULL) {
-		remove_proc_entry(PROCFS_NAME, proc_dir);
-		HIF_ERROR("%s: Could not initialize /proc/%s",
-			__func__, PROCFS_NAME);
-		return -ENOMEM;
-	}
-
-	HIF_DBG("/proc/%s/%s created", PROCFS_DIR, PROCFS_NAME);
-	return 0;               /* everything is ok */
-}
-
-/**
-   *This function is called when the module is unloaded
- *
- */
-void athdiag_procfs_remove(void)
-{
-	if (proc_dir != NULL) {
-		remove_proc_entry(PROCFS_NAME, proc_dir);
-		HIF_DBG("/proc/%s/%s removed", PROCFS_DIR, PROCFS_NAME);
-		remove_proc_entry(PROCFS_DIR, NULL);
-		HIF_DBG("/proc/%s removed", PROCFS_DIR);
-		proc_dir = NULL;
-	}
-}
-#else
-int athdiag_procfs_init(void *scn)
-{
-	return 0;
-}
-void athdiag_procfs_remove(void) {}
-#endif

core/hif/src/ce/ce_api.h

@@ -1,477 +0,0 @@
-/*
- * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __COPY_ENGINE_API_H__
-#define __COPY_ENGINE_API_H__
-
-#include "ce_main.h"
-/* TBDXXX: Use int return values for consistency with Target */
-
-/* TBDXXX: Perhaps merge Host/Target-->common */
-
-/*
- * Copy Engine support: low-level Target-side Copy Engine API.
- * This is a hardware access layer used by code that understands
- * how to use copy engines.
- */
-
-/*
- * A "struct CE_handle *" serves as an opaque pointer-sized
- * handle to a specific copy engine.
- */
-struct CE_handle;
-
-/*
- * "Send Completion" callback type for Send Completion Notification.
- *
- * If a Send Completion callback is registered and one or more sends
- * have completed, the callback is invoked.
- *
- * per_ce_send_context is a context supplied by the calling layer
- * (via ce_send_cb_register). It is associated with a copy engine.
- *
- * per_transfer_send_context is context supplied by the calling layer
- * (via the "send" call).  It may be different for each invocation
- * of send.
- *
- * The buffer parameter is the first byte sent of the first buffer
- * sent (if more than one buffer).
- *
- * nbytes is the number of bytes of that buffer that were sent.
- *
- * transfer_id matches the value used when the buffer or
- * buf_list was sent.
- *
- * Implementation note: Pops 1 completed send buffer from Source ring
- */
-typedef void (*ce_send_cb)(struct CE_handle *copyeng,
-			   void *per_ce_send_context,
-			   void *per_transfer_send_context,
-			   cdf_dma_addr_t buffer,
-			   unsigned int nbytes,
-			   unsigned int transfer_id,
-			   unsigned int sw_index,
-			   unsigned int hw_index,
-			   uint32_t toeplitz_hash_result);
-
-/*
- * "Buffer Received" callback type for Buffer Received Notification.
- *
- * Implementation note: Pops 1 completed recv buffer from Dest ring
- */
-typedef void (*CE_recv_cb)(struct CE_handle *copyeng,
-		   void *per_CE_recv_context,
-		   void *per_transfer_recv_context,
-		   cdf_dma_addr_t buffer,
-		   unsigned int nbytes,
-		   unsigned int transfer_id,
-		   unsigned int flags);
-
-/*
- * Copy Engine Watermark callback type.
- *
- * Allows upper layers to be notified when watermarks are reached:
- *   space is available and/or running short in a source ring
- *   buffers are exhausted and/or abundant in a destination ring
- *
- * The flags parameter indicates which condition triggered this
- * callback.  See CE_WM_FLAG_*.
- *
- * Watermark APIs are provided to allow upper layers "batch"
- * descriptor processing and to allow upper layers to
- * throttle/unthrottle.
- */
-typedef void (*CE_watermark_cb)(struct CE_handle *copyeng,
-				void *per_CE_wm_context, unsigned int flags);
-
-#define CE_WM_FLAG_SEND_HIGH   1
-#define CE_WM_FLAG_SEND_LOW    2
-#define CE_WM_FLAG_RECV_HIGH   4
-#define CE_WM_FLAG_RECV_LOW    8
-
-/* A list of buffers to be gathered and sent */
-struct ce_sendlist;
-
-/* Copy Engine settable attributes */
-struct CE_attr;
-
-/*==================Send=====================================================*/
-
-/* ce_send flags */
-/* disable ring's byte swap, even if the default policy is to swap */
-#define CE_SEND_FLAG_SWAP_DISABLE        1
-
-/*
- * Queue a source buffer to be sent to an anonymous destination buffer.
- *   copyeng         - which copy engine to use
- *   buffer          - address of buffer
- *   nbytes          - number of bytes to send
- *   transfer_id     - arbitrary ID; reflected to destination
- *   flags           - CE_SEND_FLAG_* values
- * Returns 0 on success; otherwise an error status.
- *
- * Note: If no flags are specified, use CE's default data swap mode.
- *
- * Implementation note: pushes 1 buffer to Source ring
- */
-int ce_send(struct CE_handle *copyeng,
-		void *per_transfer_send_context,
-		cdf_dma_addr_t buffer,
-		unsigned int nbytes,
-		unsigned int transfer_id,
-		unsigned int flags,
-		unsigned int user_flags);
-
-#ifdef WLAN_FEATURE_FASTPATH
-int ce_send_fast(struct CE_handle *copyeng, cdf_nbuf_t *msdus,
-		 unsigned int num_msdus, unsigned int transfer_id);
-
-#endif
-void ce_pkt_dl_len_set(void *hif_sc, unsigned int pkt_download_len);
-
-/*
- * Register a Send Callback function.
- * This function is called as soon as the contents of a Send
- * have reached the destination, unless disable_interrupts is
- * requested.  In this case, the callback is invoked when the
- * send status is polled, shortly after the send completes.
- */
-void ce_send_cb_register(struct CE_handle *copyeng,
-			 ce_send_cb fn_ptr,
-			 void *per_ce_send_context, int disable_interrupts);
-
-/*
- * Return the size of a SendList. This allows the caller to allocate
- * a SendList while the SendList structure remains opaque.
- */
-unsigned int ce_sendlist_sizeof(void);
-
-/* Initialize a sendlist */
-void ce_sendlist_init(struct ce_sendlist *sendlist);
-
-/* Append a simple buffer (address/length) to a sendlist. */
-int ce_sendlist_buf_add(struct ce_sendlist *sendlist,
-		cdf_dma_addr_t buffer,
-		unsigned int nbytes,
-		uint32_t flags, /* OR-ed with internal flags */
-		uint32_t user_flags);
-
-/*
- * Queue a "sendlist" of buffers to be sent using gather to a single
- * anonymous destination buffer
- *   copyeng         - which copy engine to use
- *   sendlist        - list of simple buffers to send using gather
- *   transfer_id     - arbitrary ID; reflected to destination
- * Returns 0 on success; otherwise an error status.
- *
- * Implemenation note: Pushes multiple buffers with Gather to Source ring.
- */
-int ce_sendlist_send(struct CE_handle *copyeng,
-		void *per_transfer_send_context,
-		struct ce_sendlist *sendlist,
-		unsigned int transfer_id);
-
-/*==================Recv=====================================================*/
-
-/*
- * Make a buffer available to receive. The buffer must be at least of a
- * minimal size appropriate for this copy engine (src_sz_max attribute).
- *   copyeng                    - which copy engine to use
- *   per_transfer_recv_context  - context passed back to caller's recv_cb
- *   buffer                     - address of buffer in CE space
- * Returns 0 on success; otherwise an error status.
- *
- * Implemenation note: Pushes a buffer to Dest ring.
- */
-int ce_recv_buf_enqueue(struct CE_handle *copyeng,
-			void *per_transfer_recv_context,
-			cdf_dma_addr_t buffer);
-
-/*
- * Register a Receive Callback function.
- * This function is called as soon as data is received
- * from the source.
- */
-void ce_recv_cb_register(struct CE_handle *copyeng,
-			 CE_recv_cb fn_ptr,
-			 void *per_CE_recv_context,
-			 int disable_interrupts);
-
-/*==================CE Watermark=============================================*/
-
-/*
- * Register a Watermark Callback function.
- * This function is called as soon as a watermark level
- * is crossed.  A Watermark Callback function is free to
- * handle received data "en masse"; but then some coordination
- * is required with a registered Receive Callback function.
- * [Suggestion: Either handle Receives in a Receive Callback
- * or en masse in a Watermark Callback; but not both.]
- */
-void ce_watermark_cb_register(struct CE_handle *copyeng,
-			  CE_watermark_cb fn_ptr,
-			  void *per_CE_wm_context);
-
-/*
- * Set low/high watermarks for the send/source side of a copy engine.
- *
- * Typically, the destination side CPU manages watermarks for
- * the receive side and the source side CPU manages watermarks
- * for the send side.
- *
- * A low watermark of 0 is never hit (so the watermark function
- * will never be called for a Low Watermark condition).
- *
- * A high watermark equal to nentries is never hit (so the
- * watermark function will never be called for a High Watermark
- * condition).
- */
-void ce_send_watermarks_set(struct CE_handle *copyeng,
-			    unsigned int low_alert_nentries,
-			    unsigned int high_alert_nentries);
-
-/* Set low/high watermarks for the receive/destination side of copy engine. */
-void ce_recv_watermarks_set(struct CE_handle *copyeng,
-			    unsigned int low_alert_nentries,
-			    unsigned int high_alert_nentries);
-
-/*
- * Return the number of entries that can be queued
- * to a ring at an instant in time.
- *
- * For source ring, does not imply that destination-side
- * buffers are available; merely indicates descriptor space
- * in the source ring.
- *
- * For destination ring, does not imply that previously
- * received buffers have been processed; merely indicates
- * descriptor space in destination ring.
- *
- * Mainly for use with CE Watermark callback.
- */
-unsigned int ce_send_entries_avail(struct CE_handle *copyeng);
-unsigned int ce_recv_entries_avail(struct CE_handle *copyeng);
-
-/*
- * Return the number of entries in the ring that are ready
- * to be processed by software.
- *
- * For source ring, the number of descriptors that have
- * been completed and can now be overwritten with new send
- * descriptors.
- *
- * For destination ring, the number of descriptors that
- * are available to be processed (newly received buffers).
- */
-unsigned int ce_send_entries_done(struct CE_handle *copyeng);
-unsigned int ce_recv_entries_done(struct CE_handle *copyeng);
-
-/* recv flags */
-/* Data is byte-swapped */
-#define CE_RECV_FLAG_SWAPPED            1
-
-void ce_enable_msi(struct ol_softc *scn,
-		   unsigned int CE_id,
-		   uint32_t msi_addr_lo,
-		   uint32_t msi_addr_hi,
-		   uint32_t msi_data);
-/*
- * Supply data for the next completed unprocessed receive descriptor.
- *
- * For use
- *    with CE Watermark callback,
- *    in a recv_cb function when processing buf_lists
- *    in a recv_cb function in order to mitigate recv_cb's.
- *
- * Implemenation note: Pops buffer from Dest ring.
- */
-int ce_completed_recv_next(struct CE_handle *copyeng,
-			   void **per_CE_contextp,
-			   void **per_transfer_contextp,
-			   cdf_dma_addr_t *bufferp,
-			   unsigned int *nbytesp,
-			   unsigned int *transfer_idp,
-			   unsigned int *flagsp);
-
-/*
- * Supply data for the next completed unprocessed send descriptor.
- *
- * For use
- *    with CE Watermark callback
- *    in a send_cb function in order to mitigate send_cb's.
- *
- * Implementation note: Pops 1 completed send buffer from Source ring
- */
-int ce_completed_send_next(struct CE_handle *copyeng,
-			   void **per_CE_contextp,
-			   void **per_transfer_contextp,
-			   cdf_dma_addr_t *bufferp,
-			   unsigned int *nbytesp,
-			   unsigned int *transfer_idp,
-			   unsigned int *sw_idx,
-			   unsigned int *hw_idx,
-			   uint32_t *toeplitz_hash_result);
-
-/*==================CE Engine Initialization=================================*/
-
-/* Initialize an instance of a CE */
-struct CE_handle *ce_init(struct ol_softc *scn,
-			  unsigned int CE_id, struct CE_attr *attr);
-
-/*==================CE Engine Shutdown=======================================*/
-/*
- * Support clean shutdown by allowing the caller to revoke
- * receive buffers.  Target DMA must be stopped before using
- * this API.
- */
-CDF_STATUS
-ce_revoke_recv_next(struct CE_handle *copyeng,
-		    void **per_CE_contextp,
-		    void **per_transfer_contextp,
-		    cdf_dma_addr_t *bufferp);
-
-/*
- * Support clean shutdown by allowing the caller to cancel
- * pending sends.  Target DMA must be stopped before using
- * this API.
- */
-CDF_STATUS
-ce_cancel_send_next(struct CE_handle *copyeng,
-		    void **per_CE_contextp,
-		    void **per_transfer_contextp,
-		    cdf_dma_addr_t *bufferp,
-		    unsigned int *nbytesp,
-		    unsigned int *transfer_idp,
-		    uint32_t *toeplitz_hash_result);
-
-void ce_fini(struct CE_handle *copyeng);
-
-/*==================CE Interrupt Handlers====================================*/
-void ce_per_engine_service_any(int irq, struct ol_softc *scn);
-int ce_per_engine_service(struct ol_softc *scn, unsigned int CE_id);
-void ce_per_engine_servicereap(struct ol_softc *scn, unsigned int CE_id);
-
-/*===================CE cmpl interrupt Enable/Disable =======================*/
-void ce_disable_any_copy_compl_intr_nolock(struct ol_softc *scn);
-void ce_enable_any_copy_compl_intr_nolock(struct ol_softc *scn);
-
-/* API to check if any of the copy engine pipes has
- * pending frames for prcoessing
- */
-bool ce_get_rx_pending(struct ol_softc *scn);
-
-/* CE_attr.flags values */
-#define CE_ATTR_NO_SNOOP             0x01 /* Use NonSnooping PCIe accesses? */
-#define CE_ATTR_BYTE_SWAP_DATA       0x02 /* Byte swap data words */
-#define CE_ATTR_SWIZZLE_DESCRIPTORS  0x04 /* Swizzle descriptors? */
-#define CE_ATTR_DISABLE_INTR         0x08 /* no interrupt on copy completion */
-#define CE_ATTR_ENABLE_POLL          0x10 /* poll for residue descriptors */
-
-/* Attributes of an instance of a Copy Engine */
-struct CE_attr {
-	unsigned int flags;         /* CE_ATTR_* values */
-	unsigned int priority;      /* TBD */
-	unsigned int src_nentries;  /* #entries in source ring -
-				     * Must be a power of 2 */
-	unsigned int src_sz_max;    /* Max source send size for this CE.
-				     * This is also the minimum size of
-				     * a destination buffer. */
-	unsigned int dest_nentries; /* #entries in destination ring -
-				     * Must be a power of 2 */
-	void *reserved;             /* Future use */
-};
-
-/*
- * When using sendlist_send to transfer multiple buffer fragments, the
- * transfer context of each fragment, except last one, will be filled
- * with CE_SENDLIST_ITEM_CTXT. CE_completed_send will return success for
- * each fragment done with send and the transfer context would be
- * CE_SENDLIST_ITEM_CTXT. Upper layer could use this to identify the
- * status of a send completion.
- */
-#define CE_SENDLIST_ITEM_CTXT   ((void *)0xcecebeef)
-
-/*
- * This is an opaque type that is at least large enough to hold
- * a sendlist. A sendlist can only be accessed through CE APIs,
- * but this allows a sendlist to be allocated on the run-time
- * stack.  TBDXXX: un-opaque would be simpler...
- */
-struct ce_sendlist {
-	unsigned int word[62];
-};
-
-#define ATH_ISR_NOSCHED  0x0000  /* Do not schedule bottom half/DPC */
-#define ATH_ISR_SCHED    0x0001  /* Schedule the bottom half for execution */
-#define ATH_ISR_NOTMINE  0x0002  /* for shared IRQ's */
-
-#ifdef IPA_OFFLOAD
-void ce_ipa_get_resource(struct CE_handle *ce,
-			 cdf_dma_addr_t *ce_sr_base_paddr,
-			 uint32_t *ce_sr_ring_size,
-			 cdf_dma_addr_t *ce_reg_paddr);
-#else
-/**
- * ce_ipa_get_resource() - get uc resource on copyengine
- * @ce: copyengine context
- * @ce_sr_base_paddr: copyengine source ring base physical address
- * @ce_sr_ring_size: copyengine source ring size
- * @ce_reg_paddr: copyengine register physical address
- *
- * Copy engine should release resource to micro controller
- * Micro controller needs
- *  - Copy engine source descriptor base address
- *  - Copy engine source descriptor size
- *  - PCI BAR address to access copy engine regiser
- *
- * Return: None
- */
-static inline void ce_ipa_get_resource(struct CE_handle *ce,
-			 cdf_dma_addr_t *ce_sr_base_paddr,
-			 uint32_t *ce_sr_ring_size,
-			 cdf_dma_addr_t *ce_reg_paddr)
-{
-	return;
-}
-#endif /* IPA_OFFLOAD */
-
-static inline void ce_pkt_error_count_incr(
-	struct HIF_CE_state *_hif_state,
-	enum ol_ath_hif_pkt_ecodes _hif_ecode)
-{
-	if (_hif_ecode == HIF_PIPE_NO_RESOURCE)
-		(_hif_state->scn->pkt_stats.hif_pipe_no_resrc_count)
-		+= 1;
-}
-
-bool ce_check_rx_pending(struct ol_softc *scn, int ce_id);
-#if defined(FEATURE_LRO)
-void ce_lro_flush_cb_register(struct ol_softc *scn,
-	 void (handler)(void *), void *data);
-void ce_lro_flush_cb_deregister(struct ol_softc *scn);
-#endif
-#endif /* __COPY_ENGINE_API_H__ */

core/hif/src/ce/ce_assignment.h

@@ -1,301 +0,0 @@
-/*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-/*
- * Implementation of the Host-side Host InterFace (HIF) API
- * for a Host/Target interconnect using Copy Engines over PCIe.
- */
-
-#ifndef __HIF_PCI_INTERNAL_H__
-#define __HIF_PCI_INTERNAL_H__
-
-#define HIF_PCI_DEBUG   ATH_DEBUG_MAKE_MODULE_MASK(0)
-#define HIF_PCI_IPA_UC_ASSIGNED_CE  5
-
-#if defined(DEBUG)
-static ATH_DEBUG_MASK_DESCRIPTION g_hif_debug_description[] = {
-	{HIF_PCI_DEBUG, "hif_pci"},
-};
-
-ATH_DEBUG_INSTANTIATE_MODULE_VAR(hif, "hif", "PCIe Host Interface",
-				ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_INFO,
-				ATH_DEBUG_DESCRIPTION_COUNT
-					 (g_hif_debug_description),
-				 g_hif_debug_description);
-#endif
-
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-spinlock_t pcie_access_log_lock;
-unsigned int pcie_access_log_seqnum = 0;
-HIF_ACCESS_LOG pcie_access_log[PCIE_ACCESS_LOG_NUM];
-static void hif_target_dump_access_log(void);
-#endif
-
-/*
- * Host software's Copy Engine configuration.
- * This table is derived from the CE_PCI TABLE, above.
- */
-#ifdef BIG_ENDIAN_HOST
-#define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA
-#else
-#define CE_ATTR_FLAGS 0
-#endif
-
-/* Maximum number of Copy Engine's supported */
-#define CE_HTT_H2T_MSG_SRC_NENTRIES 2048
-
-#define DIAG_CE_ID           7
-#define EPPING_CE_FLAGS_POLL \
-	(CE_ATTR_DISABLE_INTR|CE_ATTR_ENABLE_POLL|CE_ATTR_FLAGS)
-#ifdef QCA_WIFI_3_0
-static struct CE_attr host_ce_config_wlan[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
-	/* target->host HTT + HTC control */
-	{ /* CE1 */ CE_ATTR_FLAGS, 0, 0,  2048, 512, NULL,},
-	/* target->host WMI */
-	{ /* CE2 */ CE_ATTR_FLAGS, 0, 0,  2048, 32, NULL,},
-	/* host->target WMI */
-	{ /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
-	/* host->target HTT */
-	{ /* CE4 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
-		CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
-	/* ipa_uc->target HTC control */
-	{ /* CE5 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
-		1024, 512, 0, NULL,},
-	/* Target autonomous HIF_memcpy */
-	{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
-	/* ce_diag, the Diagnostic Window */
-	{ /* CE7 */ (CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,
-		2, DIAG_TRANSFER_LIMIT, 2, NULL,},
-	/* Target to uMC */
-	{ /* CE8 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
-	/*The following CEs are not being used yet */
-	{ /* CE9 */ CE_ATTR_FLAGS, 0, 0,  0, 0, NULL,},
-	{ /* CE10 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
-	{ /* CE11 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
-};
-
-static struct CE_pipe_config target_ce_config_wlan[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ 0, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
-	/* target->host HTT */
-	{ /* CE1 */ 1, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
-	/* target->host WMI  + HTC control */
-	{ /* CE2 */ 2, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
-	/* host->target WMI */
-	{ /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
-	/* host->target HTT */
-	{ /* CE4 */ 4, PIPEDIR_OUT, 256, 256,
-		(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
-	/* NB: 50% of src nentries, since tx has 2 frags */
-	/* ipa_uc->target */
-	{ /* CE5 */ 5, PIPEDIR_OUT, 1024,   64,
-		(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
-	/* Reserved for target autonomous HIF_memcpy */
-	{ /* CE6 */ 6, PIPEDIR_INOUT, 32, 4096, CE_ATTR_FLAGS, 0,},
-	/* CE7 used only by Host */
-	{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0,
-		(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
-	/* CE8 used only by IPA */
-	{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,},
-	/*The following CEs are not being used yet*/
-	{ /* CE9 */ 9, PIPEDIR_IN,  0, 0, CE_ATTR_FLAGS, 0,},
-	{ /* CE10 */ 9, PIPEDIR_IN,  0, 0, CE_ATTR_FLAGS, 0,},
-	{ /* CE11 */ 9, PIPEDIR_IN,  0, 0, CE_ATTR_FLAGS, 0,},
-};
-
-static struct CE_attr host_ce_config_wlan_epping_poll[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 2048, 0, NULL,},
-	/* target->host EP-ping */
-	{ /* CE1 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
-	/* target->host EP-ping */
-	{ /* CE2 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
-	/* host->target EP-ping */
-	{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* host->target EP-ping */
-	{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* EP-ping heartbeat */
-	{ /* CE5 */ CE_ATTR_FLAGS, 0, 0,   2048, 128, NULL,},
-	/* unused */
-	{ /* CE6 */ CE_ATTR_FLAGS, 0, 0,   0, 0, NULL,},
-	/* ce_diag, the Diagnostic Window */
-	{ /* CE7 */ CE_ATTR_FLAGS, 0, 2,   DIAG_TRANSFER_LIMIT, 2, NULL,},
-};
-
-static struct CE_attr host_ce_config_wlan_epping_irq[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ CE_ATTR_FLAGS, 0,  16, 2048, 0, NULL,},
-	/* target->host EP-ping */
-	{ /* CE1 */ CE_ATTR_FLAGS, 0,   0, 2048, 128, NULL,},
-	/* target->host EP-ping */
-	{ /* CE2 */ CE_ATTR_FLAGS, 0,   0, 2048, 128, NULL,},
-	/* host->target EP-ping */
-	{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* host->target EP-ping */
-	{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* EP-ping heartbeat */
-	{ /* CE5 */ CE_ATTR_FLAGS, 0,   0, 2048, 128, NULL,},
-	/* unused */
-	{ /* CE6 */ CE_ATTR_FLAGS, 0,   0, 0, 0, NULL,},
-	/* ce_diag, the Diagnostic Window */
-	{ /* CE7 */ CE_ATTR_FLAGS, 0,   2, DIAG_TRANSFER_LIMIT, 2, NULL,},
-};
-/*
- * EP-ping firmware's CE configuration
- */
-static struct CE_pipe_config target_ce_config_wlan_epping[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ 0, PIPEDIR_OUT,  16, 2048, CE_ATTR_FLAGS, 0,},
-	/* target->host EP-ping */
-	{ /* CE1 */ 1, PIPEDIR_IN,  128, 2048, CE_ATTR_FLAGS, 0,},
-	/* target->host EP-ping */
-	{ /* CE2 */ 2, PIPEDIR_IN,  128, 2048, CE_ATTR_FLAGS, 0,},
-	/* host->target EP-ping */
-	{ /* CE3 */ 3, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
-	/* host->target EP-ping */
-	{ /* CE4 */ 4, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
-	/* EP-ping heartbeat */
-	{ /* CE5 */ 5, PIPEDIR_IN,  128, 2048, CE_ATTR_FLAGS, 0,},
-	/* unused */
-	{ /* CE6 */ 6, PIPEDIR_INOUT, 0, 0, CE_ATTR_FLAGS, 0,},
-	/* CE7 used only by Host */
-	{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0, 0, 0,},
-	/* CE8 used only by IPA */
-	{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,}
-};
-#else
-static struct CE_attr host_ce_config_wlan[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ CE_ATTR_FLAGS, 0, 16,  256, 0, NULL,},
-	/* target->host HTT + HTC control */
-	{ /* CE1 */ CE_ATTR_FLAGS, 0, 0,  2048, 512, NULL,},
-	/* target->host WMI */
-	{ /* CE2 */ CE_ATTR_FLAGS, 0, 0,  2048, 32, NULL,},
-	/* host->target WMI */
-	{ /* CE3 */ CE_ATTR_FLAGS, 0, 32, 2048, 0, NULL,},
-	/* host->target HTT */
-	{ /* CE4 */ CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR, 0,
-		CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
-	/* ipa_uc->target HTC control */
-	{ /* CE5 */ CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR, 0,
-		1024, 512, 0, NULL,},
-	/* Target autonomous HIF_memcpy */
-	{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
-	/* ce_diag, the Diagnostic Window */
-	{ /* CE7 */ CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR,
-		0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
-};
-
-static struct CE_pipe_config target_ce_config_wlan[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ 0, PIPEDIR_OUT, 32,  256, CE_ATTR_FLAGS, 0,},
-	/* target->host HTT + HTC control */
-	{ /* CE1 */ 1, PIPEDIR_IN, 32,  2048, CE_ATTR_FLAGS, 0,},
-	/* target->host WMI */
-	{ /* CE2 */ 2, PIPEDIR_IN, 32,  2048, CE_ATTR_FLAGS, 0,},
-	/* host->target WMI */
-	{ /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
-	/* host->target HTT */
-	{ /* CE4 */ 4, PIPEDIR_OUT, 256, 256, CE_ATTR_FLAGS, 0,},
-	/* NB: 50% of src nentries, since tx has 2 frags */
-	/* ipa_uc->target HTC control */
-	{ /* CE5 */ 5, PIPEDIR_OUT, 1024,   64, CE_ATTR_FLAGS, 0,},
-	/* Reserved for target autonomous HIF_memcpy */
-	{ /* CE6 */ 6, PIPEDIR_INOUT, 32, 4096, CE_ATTR_FLAGS, 0,},
-	/* CE7 used only by Host */
-	{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0, 0, 0,},
-	/* CE8 used only by IPA */
-	{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,}
-};
-
-static struct CE_attr host_ce_config_wlan_epping_poll[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 256, 0, NULL,},
-	/* target->host EP-ping */
-	{ /* CE1 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
-	/* target->host EP-ping */
-	{ /* CE2 */ EPPING_CE_FLAGS_POLL, 0, 0, 2048, 128, NULL,},
-	/* host->target EP-ping */
-	{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* host->target EP-ping */
-	{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* EP-ping heartbeat */
-	{ /* CE5 */ CE_ATTR_FLAGS, 0, 0,   2048, 128, NULL,},
-	/* unused */
-	{ /* CE6 */ CE_ATTR_FLAGS, 0, 0,   0, 0, NULL,},
-	/* ce_diag, the Diagnostic Window */
-	{ /* CE7 */ CE_ATTR_FLAGS, 0, 2,   DIAG_TRANSFER_LIMIT, 2, NULL,},
-};
-static struct CE_attr host_ce_config_wlan_epping_irq[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ CE_ATTR_FLAGS, 0, 16, 256, 0, NULL,},
-	/* target->host EP-ping */
-	{ /* CE1 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
-	/* target->host EP-ping */
-	{ /* CE2 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
-	/* host->target EP-ping */
-	{ /* CE3 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* host->target EP-ping */
-	{ /* CE4 */ CE_ATTR_FLAGS, 0, 128, 2048, 0, NULL,},
-	/* EP-ping heartbeat */
-	{ /* CE5 */ CE_ATTR_FLAGS, 0, 0, 2048, 128, NULL,},
-	/* unused */
-	{ /* CE6 */ CE_ATTR_FLAGS, 0, 0, 0, 0, NULL,},
-	/* ce_diag, the Diagnostic Window */
-	{ /* CE7 */ CE_ATTR_FLAGS, 0, 2, DIAG_TRANSFER_LIMIT, 2, NULL,},
-};
-/*
- * EP-ping firmware's CE configuration
- */
-static struct CE_pipe_config target_ce_config_wlan_epping[] = {
-	/* host->target HTC control and raw streams */
-	{ /* CE0 */ 0, PIPEDIR_OUT, 16,   256, CE_ATTR_FLAGS, 0,},
-	/* target->host EP-ping */
-	{ /* CE1 */ 1, PIPEDIR_IN, 128,  2048, CE_ATTR_FLAGS, 0,},
-	/* target->host EP-ping */
-	{ /* CE2 */ 2, PIPEDIR_IN, 128,  2048, CE_ATTR_FLAGS, 0,},
-	/* host->target EP-ping */
-	{ /* CE3 */ 3, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
-	/* host->target EP-ping */
-	{ /* CE4 */ 4, PIPEDIR_OUT, 128, 2048, CE_ATTR_FLAGS, 0,},
-	/* EP-ping heartbeat */
-	{ /* CE5 */ 5, PIPEDIR_IN, 128,  2048, CE_ATTR_FLAGS, 0,},
-	/* unused */
-	{ /* CE6 */ 6, PIPEDIR_INOUT, 0, 0, CE_ATTR_FLAGS, 0,},
-	/* CE7 used only by Host */
-	{ /* CE7 */ 7, PIPEDIR_INOUT_H2H, 0, 0, 0, 0,},
-	/* CE8 used only by IPA */
-	{ /* CE8 */ 8, PIPEDIR_IN, 32, 2048, CE_ATTR_FLAGS, 0,}
-};
-#endif
-
-static struct CE_attr *host_ce_config = host_ce_config_wlan;
-static struct CE_pipe_config *target_ce_config = target_ce_config_wlan;
-static int target_ce_config_sz = sizeof(target_ce_config_wlan);
-#endif /* __HIF_PCI_INTERNAL_H__ */

core/hif/src/ce/ce_bmi.c

@@ -1,292 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include <osdep.h>
-#include "a_types.h"
-#include "athdefs.h"
-#include "osapi_linux.h"
-#include "targcfg.h"
-#include "cdf_lock.h"
-#include "cdf_status.h"
-#include <cdf_atomic.h>         /* cdf_atomic_read */
-#include <targaddrs.h>
-#include <bmi_msg.h>
-#include "hif_io32.h"
-#include <hif.h>
-#include "regtable.h"
-#define ATH_MODULE_NAME hif
-#include <a_debug.h>
-#include "hif_main.h"
-#include "ce_api.h"
-#include "cdf_trace.h"
-#include "cds_api.h"
-#ifdef CONFIG_CNSS
-#include <net/cnss.h>
-#else
-#include "cnss_stub.h"
-#endif
-#include "epping_main.h"
-#include "hif_debug.h"
-
-/* Track a BMI transaction that is in progress */
-#ifndef BIT
-#define BIT(n) (1 << (n))
-#endif
-
-enum {
-	BMI_REQ_SEND_DONE = BIT(0),   /* the bmi tx completion */
-	BMI_RESP_RECV_DONE = BIT(1),  /* the bmi respond is received */
-};
-
-struct BMI_transaction {
-	struct HIF_CE_state *hif_state;
-	cdf_semaphore_t bmi_transaction_sem;
-	uint8_t *bmi_request_host;        /* Req BMI msg in Host addr space */
-	cdf_dma_addr_t bmi_request_CE;    /* Req BMI msg in CE addr space */
-	uint32_t bmi_request_length;      /* Length of BMI request */
-	uint8_t *bmi_response_host;       /* Rsp BMI msg in Host addr space */
-	cdf_dma_addr_t bmi_response_CE;   /* Rsp BMI msg in CE addr space */
-	unsigned int bmi_response_length; /* Length of received response */
-	unsigned int bmi_timeout_ms;
-	uint32_t bmi_transaction_flags;   /* flags for the transcation */
-};
-
-/*
- * send/recv completion functions for BMI.
- * NB: The "net_buf" parameter is actually just a
- * straight buffer, not an sk_buff.
- */
-void hif_bmi_send_done(struct CE_handle *copyeng, void *ce_context,
-		  void *transfer_context, cdf_dma_addr_t data,
-		  unsigned int nbytes,
-		  unsigned int transfer_id, unsigned int sw_index,
-		  unsigned int hw_index, uint32_t toeplitz_hash_result)
-{
-	struct BMI_transaction *transaction =
-		(struct BMI_transaction *)transfer_context;
-	struct ol_softc *scn = transaction->hif_state->scn;
-
-#ifdef BMI_RSP_POLLING
-	/*
-	 * Fix EV118783, Release a semaphore after sending
-	 * no matter whether a response is been expecting now.
-	 */
-	cdf_semaphore_release(scn->cdf_dev,
-			      &transaction->bmi_transaction_sem);
-#else
-	/*
-	 * If a response is anticipated, we'll complete the
-	 * transaction if the response has been received.
-	 * If no response is anticipated, complete the
-	 * transaction now.
-	 */
-	transaction->bmi_transaction_flags |= BMI_REQ_SEND_DONE;
-
-	/* resp is't needed or has already been received,
-	 * never assume resp comes later then this */
-	if (!transaction->bmi_response_CE ||
-	    (transaction->bmi_transaction_flags & BMI_RESP_RECV_DONE)) {
-		cdf_semaphore_release(scn->cdf_dev,
-				      &transaction->bmi_transaction_sem);
-	}
-#endif
-}
-
-#ifndef BMI_RSP_POLLING
-void hif_bmi_recv_data(struct CE_handle *copyeng, void *ce_context,
-		  void *transfer_context, cdf_dma_addr_t data,
-		  unsigned int nbytes,
-		  unsigned int transfer_id, unsigned int flags)
-{
-	struct BMI_transaction *transaction =
-		(struct BMI_transaction *)transfer_context;
-	struct ol_softc *scn = transaction->hif_state->scn;
-
-	transaction->bmi_response_length = nbytes;
-	transaction->bmi_transaction_flags |= BMI_RESP_RECV_DONE;
-
-	/* when both send/recv are done, the sem can be released */
-	if (transaction->bmi_transaction_flags & BMI_REQ_SEND_DONE) {
-		cdf_semaphore_release(scn->cdf_dev,
-				      &transaction->bmi_transaction_sem);
-	}
-}
-#endif
-
-CDF_STATUS hif_exchange_bmi_msg(struct ol_softc *scn,
-		     uint8_t *bmi_request,
-		     uint32_t request_length,
-		     uint8_t *bmi_response,
-		     uint32_t *bmi_response_lengthp, uint32_t TimeoutMS)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	struct HIF_CE_pipe_info *send_pipe_info =
-		&(hif_state->pipe_info[BMI_CE_NUM_TO_TARG]);
-	struct CE_handle *ce_send_hdl = send_pipe_info->ce_hdl;
-	cdf_dma_addr_t CE_request, CE_response = 0;
-	struct BMI_transaction *transaction = NULL;
-	int status = CDF_STATUS_SUCCESS;
-	struct HIF_CE_pipe_info *recv_pipe_info =
-		&(hif_state->pipe_info[BMI_CE_NUM_TO_HOST]);
-	struct CE_handle *ce_recv = recv_pipe_info->ce_hdl;
-	unsigned int mux_id = 0;
-	unsigned int transaction_id = 0xffff;
-	unsigned int user_flags = 0;
-#ifdef BMI_RSP_POLLING
-	cdf_dma_addr_t buf;
-	unsigned int completed_nbytes, id, flags;
-	int i;
-#endif
-
-	transaction =
-		(struct BMI_transaction *)cdf_mem_malloc(sizeof(*transaction));
-	if (unlikely(!transaction)) {
-		HIF_ERROR("%s: no memory", __func__);
-		return CDF_STATUS_E_NOMEM;
-	}
-	transaction_id = (mux_id & MUX_ID_MASK) |
-		(transaction_id & TRANSACTION_ID_MASK);
-#ifdef QCA_WIFI_3_0
-	user_flags &= DESC_DATA_FLAG_MASK;
-#endif
-	A_TARGET_ACCESS_LIKELY(scn);
-
-	/* Initialize bmi_transaction_sem to block */
-	cdf_semaphore_init(&transaction->bmi_transaction_sem);
-	cdf_semaphore_acquire(scn->cdf_dev, &transaction->bmi_transaction_sem);
-
-	transaction->hif_state = hif_state;
-	transaction->bmi_request_host = bmi_request;
-	transaction->bmi_request_length = request_length;
-	transaction->bmi_response_length = 0;
-	transaction->bmi_timeout_ms = TimeoutMS;
-	transaction->bmi_transaction_flags = 0;
-
-	/*
-	 * CE_request = dma_map_single(dev,
-	 * (void *)bmi_request, request_length, DMA_TO_DEVICE);
-	 */
-	CE_request = scn->bmi_cmd_da;
-	transaction->bmi_request_CE = CE_request;
-
-	if (bmi_response) {
-
-		/*
-		 * CE_response = dma_map_single(dev, bmi_response,
-		 * BMI_DATASZ_MAX, DMA_FROM_DEVICE);
-		 */
-		CE_response = scn->bmi_rsp_da;
-		transaction->bmi_response_host = bmi_response;
-		transaction->bmi_response_CE = CE_response;
-		/* dma_cache_sync(dev, bmi_response,
-		    BMI_DATASZ_MAX, DMA_FROM_DEVICE); */
-		cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev,
-					       CE_response,
-					       BMI_DATASZ_MAX,
-					       DMA_FROM_DEVICE);
-		ce_recv_buf_enqueue(ce_recv, transaction,
-				    transaction->bmi_response_CE);
-		/* NB: see HIF_BMI_recv_done */
-	} else {
-		transaction->bmi_response_host = NULL;
-		transaction->bmi_response_CE = 0;
-	}
-
-	/* dma_cache_sync(dev, bmi_request, request_length, DMA_TO_DEVICE); */
-	cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev, CE_request,
-				       request_length, DMA_TO_DEVICE);
-
-	status =
-		ce_send(ce_send_hdl, transaction,
-			CE_request, request_length,
-			transaction_id, 0, user_flags);
-	ASSERT(status == CDF_STATUS_SUCCESS);
-	/* NB: see hif_bmi_send_done */
-
-	/* TBDXXX: handle timeout */
-
-	/* Wait for BMI request/response transaction to complete */
-	/* Always just wait for BMI request here if
-	 * BMI_RSP_POLLING is defined */
-	while (cdf_semaphore_acquire
-		       (scn->cdf_dev, &transaction->bmi_transaction_sem)) {
-		/*need some break out condition(time out?) */
-	}
-
-	if (bmi_response) {
-#ifdef BMI_RSP_POLLING
-		/* Fix EV118783, do not wait a semaphore for the BMI response
-		 * since the relative interruption may be lost.
-		 * poll the BMI response instead.
-		 */
-		i = 0;
-		while (ce_completed_recv_next(
-			    ce_recv, NULL, NULL, &buf,
-			    &completed_nbytes, &id,
-			    &flags) != CDF_STATUS_SUCCESS) {
-			if (i++ > BMI_RSP_TO_MILLISEC) {
-				HIF_ERROR("%s:error, can't get bmi response\n",
-					__func__);
-				status = CDF_STATUS_E_BUSY;
-				break;
-			}
-			OS_DELAY(1000);
-		}
-
-		if ((status == CDF_STATUS_SUCCESS) && bmi_response_lengthp)
-			*bmi_response_lengthp = completed_nbytes;
-#else
-		if ((status == CDF_STATUS_SUCCESS) && bmi_response_lengthp) {
-			*bmi_response_lengthp =
-				transaction->bmi_response_length;
-		}
-#endif
-
-	}
-
-	/* dma_unmap_single(dev, transaction->bmi_request_CE,
-		request_length, DMA_TO_DEVICE); */
-	/* bus_unmap_single(scn->sc_osdev,
-		 transaction->bmi_request_CE,
-		request_length, BUS_DMA_TODEVICE); */
-
-	if (status != CDF_STATUS_SUCCESS) {
-		cdf_dma_addr_t unused_buffer;
-		unsigned int unused_nbytes;
-		unsigned int unused_id;
-		unsigned int toeplitz_hash_result;
-
-		ce_cancel_send_next(ce_send_hdl,
-			NULL, NULL, &unused_buffer,
-			&unused_nbytes, &unused_id,
-			&toeplitz_hash_result);
-	}
-
-	A_TARGET_ACCESS_UNLIKELY(scn);
-	cdf_mem_free(transaction);
-	return status;
-}

core/hif/src/ce/ce_bmi.h

@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __CE_BMI_H__
-#define __CE_BMI_H__
-
-#include <cdf_atomic.h>         /* cdf_atomic_read */
-#include "cdf_lock.h"
-#include "ce_api.h"
-#include "cepci.h"
-
-void hif_bmi_recv_data(struct CE_handle *copyeng, void *ce_context,
-		  void *transfer_context, cdf_dma_addr_t data,
-		  unsigned int nbytes,
-		  unsigned int transfer_id, unsigned int flags);
-void hif_bmi_send_done(struct CE_handle *copyeng, void *ce_context,
-		  void *transfer_context, cdf_dma_addr_t data,
-		  unsigned int nbytes,
-		  unsigned int transfer_id, unsigned int sw_index,
-		  unsigned int hw_index, uint32_t toeplitz_hash_result);
-#endif /* __CE_BMI_H__ */

core/hif/src/ce/ce_diag.c

@@ -1,456 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include <osdep.h>
-#include "a_types.h"
-#include "athdefs.h"
-#include "osapi_linux.h"
-#include "targcfg.h"
-#include "cdf_lock.h"
-#include "cdf_status.h"
-#include <cdf_atomic.h>         /* cdf_atomic_read */
-#include <targaddrs.h>
-#include <bmi_msg.h>
-#include "hif_io32.h"
-#include <hif.h>
-#include <htc_services.h>
-#include "regtable.h"
-#include <a_debug.h>
-#include "hif_main.h"
-#include "ce_api.h"
-#include "cdf_trace.h"
-#include "cds_api.h"
-#ifdef CONFIG_CNSS
-#include <net/cnss.h>
-#endif
-#include "hif_debug.h"
-#include "epping_main.h"
-#include "cds_concurrency.h"
-
-void hif_dump_target_memory(struct ol_softc *scn, void *ramdump_base,
-			    uint32_t address, uint32_t size)
-{
-	uint32_t loc = address;
-	uint32_t val = 0;
-	uint32_t j = 0;
-	u8 *temp = ramdump_base;
-
-	A_TARGET_ACCESS_BEGIN(scn);
-	while (j < size) {
-		val = hif_read32_mb(scn->mem + loc + j);
-		cdf_mem_copy(temp, &val, 4);
-		j += 4;
-		temp += 4;
-	}
-	A_TARGET_ACCESS_END(scn);
-}
-/*
- * TBDXXX: Should be a function call specific to each Target-type.
- * This convoluted macro converts from Target CPU Virtual Address
- * Space to CE Address Space. As part of this process, we
- * conservatively fetch the current PCIE_BAR. MOST of the time,
- * this should match the upper bits of PCI space for this device;
- * but that's not guaranteed.
- */
-#ifdef QCA_WIFI_3_0
-#define TARG_CPU_SPACE_TO_CE_SPACE(pci_addr, addr) \
-	(scn->mem_pa + addr)
-#else
-#define TARG_CPU_SPACE_TO_CE_SPACE(pci_addr, addr) \
-	(((hif_read32_mb((pci_addr) + \
-	(SOC_CORE_BASE_ADDRESS|CORE_CTRL_ADDRESS)) & 0x7ff) << 21) \
-	 | 0x100000 | ((addr) & 0xfffff))
-#endif
-/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
-#define DIAG_ACCESS_CE_TIMEOUT_MS 10
-
-/*
- * Diagnostic read/write access is provided for startup/config/debug usage.
- * Caller must guarantee proper alignment, when applicable, and single user
- * at any moment.
- */
-
-CDF_STATUS
-hif_diag_read_mem(struct ol_softc *scn, uint32_t address, uint8_t *data,
-		  int nbytes)
-{
-	struct HIF_CE_state *hif_state;
-	CDF_STATUS status = CDF_STATUS_SUCCESS;
-	cdf_dma_addr_t buf;
-	unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
-	unsigned int id;
-	unsigned int flags;
-	struct CE_handle *ce_diag;
-	cdf_dma_addr_t CE_data;      /* Host buffer address in CE space */
-	cdf_dma_addr_t CE_data_base = 0;
-	void *data_buf = NULL;
-	int i;
-	unsigned int mux_id = 0;
-	unsigned int transaction_id = 0xffff;
-	cdf_dma_addr_t ce_phy_addr = address;
-	unsigned int toeplitz_hash_result;
-	unsigned int user_flags = 0;
-
-	hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-
-	transaction_id = (mux_id & MUX_ID_MASK) |
-		 (transaction_id & TRANSACTION_ID_MASK);
-#ifdef QCA_WIFI_3_0
-	user_flags &= DESC_DATA_FLAG_MASK;
-#endif
-
-	/* This code cannot handle reads to non-memory space. Redirect to the
-	 * register read fn but preserve the multi word read capability of
-	 * this fn
-	 */
-	if (address < DRAM_BASE_ADDRESS) {
-
-		if ((address & 0x3) || ((uintptr_t) data & 0x3))
-			return CDF_STATUS_E_INVAL;
-
-		while ((nbytes >= 4) &&
-		       (CDF_STATUS_SUCCESS == (status =
-				 hif_diag_read_access(scn, address,
-				       (uint32_t *)data)))) {
-
-			nbytes -= sizeof(uint32_t);
-			address += sizeof(uint32_t);
-			data += sizeof(uint32_t);
-
-		}
-
-		return status;
-	}
-	ce_diag = hif_state->ce_diag;
-
-	A_TARGET_ACCESS_LIKELY(scn);
-
-	/*
-	 * Allocate a temporary bounce buffer to hold caller's data
-	 * to be DMA'ed from Target. This guarantees
-	 *   1) 4-byte alignment
-	 *   2) Buffer in DMA-able space
-	 */
-	orig_nbytes = nbytes;
-	data_buf = cdf_os_mem_alloc_consistent(scn->cdf_dev,
-				    orig_nbytes, &CE_data_base, 0);
-	if (!data_buf) {
-		status = CDF_STATUS_E_NOMEM;
-		goto done;
-	}
-	cdf_mem_set(data_buf, orig_nbytes, 0);
-	cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev, CE_data_base,
-				       orig_nbytes, DMA_FROM_DEVICE);
-
-	remaining_bytes = orig_nbytes;
-	CE_data = CE_data_base;
-	while (remaining_bytes) {
-		nbytes = min(remaining_bytes, DIAG_TRANSFER_LIMIT);
-		{
-			status = ce_recv_buf_enqueue(ce_diag, NULL, CE_data);
-			if (status != CDF_STATUS_SUCCESS)
-				goto done;
-		}
-
-		{	/* Request CE to send from Target(!)
-			 * address to Host buffer */
-			/*
-			 * The address supplied by the caller is in the
-			 * Target CPU virtual address space.
-			 *
-			 * In order to use this address with the diagnostic CE,
-			 * convert it from
-			 *    Target CPU virtual address space
-			 * to
-			 *    CE address space
-			 */
-			A_TARGET_ACCESS_BEGIN_RET(scn);
-			ce_phy_addr =
-				TARG_CPU_SPACE_TO_CE_SPACE(scn->mem, address);
-			A_TARGET_ACCESS_END_RET(scn);
-
-			status =
-				ce_send(ce_diag, NULL, ce_phy_addr, nbytes,
-					transaction_id, 0, user_flags);
-			if (status != CDF_STATUS_SUCCESS)
-				goto done;
-		}
-
-		i = 0;
-		while (ce_completed_send_next(ce_diag, NULL, NULL, &buf,
-				&completed_nbytes, &id, NULL, NULL,
-				&toeplitz_hash_result) != CDF_STATUS_SUCCESS) {
-			cdf_mdelay(1);
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
-				status = CDF_STATUS_E_BUSY;
-				goto done;
-			}
-		}
-		if (nbytes != completed_nbytes) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-		if (buf != ce_phy_addr) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-
-		i = 0;
-		while (ce_completed_recv_next
-				(ce_diag, NULL, NULL, &buf,
-				&completed_nbytes, &id,
-				 &flags) != CDF_STATUS_SUCCESS) {
-			cdf_mdelay(1);
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
-				status = CDF_STATUS_E_BUSY;
-				goto done;
-			}
-		}
-		if (nbytes != completed_nbytes) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-		if (buf != CE_data) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-
-		remaining_bytes -= nbytes;
-		address += nbytes;
-		CE_data += nbytes;
-	}
-
-done:
-	A_TARGET_ACCESS_UNLIKELY(scn);
-
-	if (status == CDF_STATUS_SUCCESS)
-		cdf_mem_copy(data, data_buf, orig_nbytes);
-	else
-		HIF_ERROR("%s failure (0x%x)", __func__, address);
-
-	if (data_buf)
-		cdf_os_mem_free_consistent(scn->cdf_dev, orig_nbytes,
-				    data_buf, CE_data_base, 0);
-
-	return status;
-}
-
-/* Read 4-byte aligned data from Target memory or register */
-CDF_STATUS hif_diag_read_access(struct ol_softc *scn,
-				uint32_t address, uint32_t *data)
-{
-	struct HIF_CE_state *hif_state;
-
-	hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	if (address >= DRAM_BASE_ADDRESS) {
-		/* Assume range doesn't cross this boundary */
-		return hif_diag_read_mem(scn, address, (uint8_t *) data,
-					 sizeof(uint32_t));
-	} else {
-		A_TARGET_ACCESS_BEGIN_RET(scn);
-		*data = A_TARGET_READ(scn, address);
-		A_TARGET_ACCESS_END_RET(scn);
-
-		return CDF_STATUS_SUCCESS;
-	}
-}
-
-CDF_STATUS hif_diag_write_mem(struct ol_softc *scn,
-			      uint32_t address, uint8_t *data, int nbytes)
-{
-	struct HIF_CE_state *hif_state;
-	CDF_STATUS status = CDF_STATUS_SUCCESS;
-	cdf_dma_addr_t buf;
-	unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
-	unsigned int id;
-	unsigned int flags;
-	struct CE_handle *ce_diag;
-	void *data_buf = NULL;
-	cdf_dma_addr_t CE_data;      /* Host buffer address in CE space */
-	cdf_dma_addr_t CE_data_base = 0;
-	int i;
-	unsigned int mux_id = 0;
-	unsigned int transaction_id = 0xffff;
-	cdf_dma_addr_t ce_phy_addr = address;
-	unsigned int toeplitz_hash_result;
-	unsigned int user_flags = 0;
-
-	hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	ce_diag = hif_state->ce_diag;
-	transaction_id = (mux_id & MUX_ID_MASK) |
-		(transaction_id & TRANSACTION_ID_MASK);
-#ifdef QCA_WIFI_3_0
-	user_flags &= DESC_DATA_FLAG_MASK;
-#endif
-
-	A_TARGET_ACCESS_LIKELY(scn);
-
-	/*
-	 * Allocate a temporary bounce buffer to hold caller's data
-	 * to be DMA'ed to Target. This guarantees
-	 *   1) 4-byte alignment
-	 *   2) Buffer in DMA-able space
-	 */
-	orig_nbytes = nbytes;
-	data_buf = cdf_os_mem_alloc_consistent(scn->cdf_dev,
-				    orig_nbytes, &CE_data_base, 0);
-	if (!data_buf) {
-		status = A_NO_MEMORY;
-		goto done;
-	}
-
-	/* Copy caller's data to allocated DMA buf */
-	cdf_mem_copy(data_buf, data, orig_nbytes);
-	cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev, CE_data_base,
-				       orig_nbytes, DMA_TO_DEVICE);
-
-	/*
-	 * The address supplied by the caller is in the
-	 * Target CPU virtual address space.
-	 *
-	 * In order to use this address with the diagnostic CE,
-	 * convert it from
-	 *    Target CPU virtual address space
-	 * to
-	 *    CE address space
-	 */
-	A_TARGET_ACCESS_BEGIN_RET(scn);
-	ce_phy_addr = TARG_CPU_SPACE_TO_CE_SPACE(scn->mem, address);
-	A_TARGET_ACCESS_END_RET(scn);
-
-	remaining_bytes = orig_nbytes;
-	CE_data = CE_data_base;
-	while (remaining_bytes) {
-		nbytes = min(remaining_bytes, DIAG_TRANSFER_LIMIT);
-
-		{   /* Set up to receive directly into Target(!) address */
-			status = ce_recv_buf_enqueue(ce_diag,
-						NULL, ce_phy_addr);
-			if (status != CDF_STATUS_SUCCESS)
-				goto done;
-		}
-
-		{
-			/*
-			 * Request CE to send caller-supplied data that
-			 * was copied to bounce buffer to Target(!) address.
-			 */
-			status =
-				ce_send(ce_diag, NULL,
-					(cdf_dma_addr_t) CE_data, nbytes,
-					transaction_id, 0, user_flags);
-			if (status != CDF_STATUS_SUCCESS)
-				goto done;
-		}
-
-		i = 0;
-		while (ce_completed_send_next(ce_diag, NULL, NULL, &buf,
-			    &completed_nbytes, &id,
-			    NULL, NULL, &toeplitz_hash_result) !=
-			    CDF_STATUS_SUCCESS) {
-			cdf_mdelay(1);
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
-				status = CDF_STATUS_E_BUSY;
-				goto done;
-			}
-		}
-
-		if (nbytes != completed_nbytes) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-
-		if (buf != CE_data) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-
-		i = 0;
-		while (ce_completed_recv_next
-			(ce_diag, NULL, NULL, &buf,
-			&completed_nbytes, &id,
-			&flags) != CDF_STATUS_SUCCESS) {
-			cdf_mdelay(1);
-			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
-				status = CDF_STATUS_E_BUSY;
-				goto done;
-			}
-		}
-
-		if (nbytes != completed_nbytes) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-
-		if (buf != ce_phy_addr) {
-			status = CDF_STATUS_E_FAILURE;
-			goto done;
-		}
-
-		remaining_bytes -= nbytes;
-		address += nbytes;
-		CE_data += nbytes;
-	}
-
-done:
-	A_TARGET_ACCESS_UNLIKELY(scn);
-
-	if (data_buf) {
-		cdf_os_mem_free_consistent(scn->cdf_dev, orig_nbytes,
-				    data_buf, CE_data_base, 0);
-	}
-
-	if (status != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s failure (0x%llu)", __func__,
-			(uint64_t)ce_phy_addr);
-	}
-
-	return status;
-}
-
-/* Write 4B data to Target memory or register */
-CDF_STATUS
-hif_diag_write_access(struct ol_softc *scn, uint32_t address, uint32_t data)
-{
-	struct HIF_CE_state *hif_state;
-
-	hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	if (address >= DRAM_BASE_ADDRESS) {
-		/* Assume range doesn't cross this boundary */
-		uint32_t data_buf = data;
-
-		return hif_diag_write_mem(scn, address,
-					  (uint8_t *) &data_buf,
-					  sizeof(uint32_t));
-	} else {
-		A_TARGET_ACCESS_BEGIN_RET(scn);
-		A_TARGET_WRITE(scn, address, data);
-		A_TARGET_ACCESS_END_RET(scn);
-
-		return CDF_STATUS_SUCCESS;
-	}
-}

core/hif/src/ce/ce_internal.h

@@ -1,365 +0,0 @@
-/*
- * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-#ifndef __COPY_ENGINE_INTERNAL_H__
-#define __COPY_ENGINE_INTERNAL_H__
-
-#include <hif.h>                /* A_TARGET_WRITE */
-
-/* Copy Engine operational state */
-enum CE_op_state {
-	CE_UNUSED,
-	CE_PAUSED,
-	CE_RUNNING,
-};
-
-enum ol_ath_hif_ce_ecodes {
-	CE_RING_DELTA_FAIL = 0
-};
-
-struct CE_src_desc;
-
-/* Copy Engine Ring internal state */
-struct CE_ring_state {
-
-	/* Number of entries in this ring; must be power of 2 */
-	unsigned int nentries;
-	unsigned int nentries_mask;
-
-	/*
-	 * For dest ring, this is the next index to be processed
-	 * by software after it was/is received into.
-	 *
-	 * For src ring, this is the last descriptor that was sent
-	 * and completion processed by software.
-	 *
-	 * Regardless of src or dest ring, this is an invariant
-	 * (modulo ring size):
-	 *     write index >= read index >= sw_index
-	 */
-	unsigned int sw_index;
-	unsigned int write_index;       /* cached copy */
-	/*
-	 * For src ring, this is the next index not yet processed by HW.
-	 * This is a cached copy of the real HW index (read index), used
-	 * for avoiding reading the HW index register more often than
-	 * necessary.
-	 * This extends the invariant:
-	 *     write index >= read index >= hw_index >= sw_index
-	 *
-	 * For dest ring, this is currently unused.
-	 */
-	unsigned int hw_index;  /* cached copy */
-
-	/* Start of DMA-coherent area reserved for descriptors */
-	void *base_addr_owner_space_unaligned;  /* Host address space */
-	cdf_dma_addr_t base_addr_CE_space_unaligned; /* CE address space */
-
-	/*
-	 * Actual start of descriptors.
-	 * Aligned to descriptor-size boundary.
-	 * Points into reserved DMA-coherent area, above.
-	 */
-	void *base_addr_owner_space;    /* Host address space */
-	cdf_dma_addr_t base_addr_CE_space;   /* CE address space */
-	/*
-	 * Start of shadow copy of descriptors, within regular memory.
-	 * Aligned to descriptor-size boundary.
-	 */
-	char *shadow_base_unaligned;
-	struct CE_src_desc *shadow_base;
-
-	unsigned int low_water_mark_nentries;
-	unsigned int high_water_mark_nentries;
-	void **per_transfer_context;
-	OS_DMA_MEM_CONTEXT(ce_dmacontext) /* OS Specific DMA context */
-};
-
-/* Copy Engine internal state */
-struct CE_state {
-	struct ol_softc *scn;
-	unsigned int id;
-	unsigned int attr_flags;  /* CE_ATTR_* */
-	uint32_t ctrl_addr;       /* relative to BAR */
-	enum CE_op_state state;
-
-#ifdef WLAN_FEATURE_FASTPATH
-	u_int32_t download_len; /* pkt download length for source ring */
-#endif /* WLAN_FEATURE_FASTPATH */
-
-	ce_send_cb send_cb;
-	void *send_context;
-
-	CE_recv_cb recv_cb;
-	void *recv_context;
-
-	/* misc_cbs - are any callbacks besides send and recv enabled? */
-	uint8_t misc_cbs;
-
-	CE_watermark_cb watermark_cb;
-	void *wm_context;
-
-	/*Record the state of the copy compl interrupt */
-	int disable_copy_compl_intr;
-
-	unsigned int src_sz_max;
-	struct CE_ring_state *src_ring;
-	struct CE_ring_state *dest_ring;
-	atomic_t rx_pending;
-
-	cdf_spinlock_t ce_index_lock;
-	bool force_break;	/* Flag to indicate whether to
-				 * break out the DPC context */
-
-	unsigned int receive_count;	/* count Num Of Receive Buffers
-					 * handled for one interrupt
-					 * DPC routine */
-	/* epping */
-	bool timer_inited;
-	cdf_softirq_timer_t poll_timer;
-	void (*lro_flush_cb)(void *);
-	void *lro_data;
-};
-
-/* Descriptor rings must be aligned to this boundary */
-#define CE_DESC_RING_ALIGN 8
-
-#ifdef QCA_WIFI_3_0
-#define HIF_CE_DESC_ADDR_TO_DMA(desc) \
-	(cdf_dma_addr_t)(((uint64_t)(desc)->buffer_addr + \
-	((uint64_t)((desc)->buffer_addr_hi & 0x1F) << 32)))
-#else
-#define HIF_CE_DESC_ADDR_TO_DMA(desc) \
-	(cdf_dma_addr_t)((desc)->buffer_addr)
-#endif
-
-#ifdef QCA_WIFI_3_0
-struct CE_src_desc {
-	uint32_t buffer_addr:32;
-#if _BYTE_ORDER == _BIG_ENDIAN
-	uint32_t gather:1,
-		enable_11h:1,
-		meta_data_low:2, /* fw_metadata_low */
-		packet_result_offset:12,
-		toeplitz_hash_enable:1,
-		addr_y_search_disable:1,
-		addr_x_search_disable:1,
-		misc_int_disable:1,
-		target_int_disable:1,
-		host_int_disable:1,
-		dest_byte_swap:1,
-		byte_swap:1,
-		type:2,
-		tx_classify:1,
-		buffer_addr_hi:5;
-		uint32_t meta_data:16, /* fw_metadata_high */
-		nbytes:16;       /* length in register map */
-#else
-	uint32_t buffer_addr_hi:5,
-		tx_classify:1,
-		type:2,
-		byte_swap:1,          /* src_byte_swap */
-		dest_byte_swap:1,
-		host_int_disable:1,
-		target_int_disable:1,
-		misc_int_disable:1,
-		addr_x_search_disable:1,
-		addr_y_search_disable:1,
-		toeplitz_hash_enable:1,
-		packet_result_offset:12,
-		meta_data_low:2, /* fw_metadata_low */
-		enable_11h:1,
-		gather:1;
-		uint32_t nbytes:16, /* length in register map */
-		meta_data:16; /* fw_metadata_high */
-#endif
-	uint32_t toeplitz_hash_result:32;
-};
-
-struct CE_dest_desc {
-	uint32_t buffer_addr:32;
-#if _BYTE_ORDER == _BIG_ENDIAN
-	uint32_t gather:1,
-		enable_11h:1,
-		meta_data_low:2, /* fw_metadata_low */
-		packet_result_offset:12,
-		toeplitz_hash_enable:1,
-		addr_y_search_disable:1,
-		addr_x_search_disable:1,
-		misc_int_disable:1,
-		target_int_disable:1,
-		host_int_disable:1,
-		byte_swap:1,
-		src_byte_swap:1,
-		type:2,
-		tx_classify:1,
-		buffer_addr_hi:5;
-		uint32_t meta_data:16, /* fw_metadata_high */
-		nbytes:16;          /* length in register map */
-#else
-	uint32_t buffer_addr_hi:5,
-		tx_classify:1,
-		type:2,
-		src_byte_swap:1,
-		byte_swap:1,         /* dest_byte_swap */
-		host_int_disable:1,
-		target_int_disable:1,
-		misc_int_disable:1,
-		addr_x_search_disable:1,
-		addr_y_search_disable:1,
-		toeplitz_hash_enable:1,
-		packet_result_offset:12,
-		meta_data_low:2, /* fw_metadata_low */
-		enable_11h:1,
-		gather:1;
-		uint32_t nbytes:16, /* length in register map */
-		meta_data:16;    /* fw_metadata_high */
-#endif
-	uint32_t toeplitz_hash_result:32;
-};
-#else
-struct CE_src_desc {
-	uint32_t buffer_addr;
-#if _BYTE_ORDER == _BIG_ENDIAN
-	uint32_t  meta_data:14,
-		byte_swap:1,
-		gather:1,
-		nbytes:16;
-#else
-
-		uint32_t nbytes:16,
-		gather:1,
-		byte_swap:1,
-		meta_data:14;
-#endif
-};
-
-struct CE_dest_desc {
-	uint32_t buffer_addr;
-#if _BYTE_ORDER == _BIG_ENDIAN
-	uint32_t  meta_data:14,
-		byte_swap:1,
-		gather:1,
-		nbytes:16;
-#else
-	uint32_t nbytes:16,
-		gather:1,
-		byte_swap:1,
-		meta_data:14;
-#endif
-};
-#endif /* QCA_WIFI_3_0 */
-
-#define CE_SENDLIST_ITEMS_MAX 12
-
-/**
- * union ce_desc - unified data type for ce descriptors
- *
- * Both src and destination descriptors follow the same format.
- * They use different data structures for different access symantics.
- * Here we provice a unifying data type.
- */
-union ce_desc {
-	struct CE_src_desc src_desc;
-	struct CE_dest_desc dest_desc;
-};
-
-/**
- * enum hif_ce_event_type - HIF copy engine event type
- * @HIF_RX_DESC_POST: event recorded before updating write index of RX ring.
- * @HIF_RX_DESC_COMPLETION: event recorded before updating sw index of RX ring.
- * @HIF_TX_GATHER_DESC_POST: post gather desc. (no write index update)
- * @HIF_TX_DESC_POST: event recorded before updating write index of TX ring.
- * @HIF_TX_DESC_COMPLETION: event recorded before updating sw index of TX ring.
- * @HIF_IRQ_EVENT: event recorded in the irq before scheduling the bh
- * @HIF_CE_TASKLET_ENTRY: records the start of the ce_tasklet
- * @HIF_CE_TASKLET_RESCHEDULE: records the rescheduling of the wlan_tasklet
- * @HIF_CE_TASKLET_EXIT: records the exit of the wlan tasklet without reschedule
- * @HIF_CE_REAP_ENTRY: records when we process completion outside of a bh
- * @HIF_CE_REAP_EXIT:  records when we process completion outside of a bh
- */
-enum hif_ce_event_type {
-	HIF_RX_DESC_POST,
-	HIF_RX_DESC_COMPLETION,
-	HIF_TX_GATHER_DESC_POST,
-	HIF_TX_DESC_POST,
-	HIF_TX_DESC_COMPLETION,
-	HIF_IRQ_EVENT,
-	HIF_CE_TASKLET_ENTRY,
-	HIF_CE_TASKLET_RESCHEDULE,
-	HIF_CE_TASKLET_EXIT,
-	HIF_CE_REAP_ENTRY,
-	HIF_CE_REAP_EXIT,
-};
-
-void ce_init_ce_desc_event_log(int ce_id, int size);
-void hif_record_ce_desc_event(int ce_id, enum hif_ce_event_type type,
-		union ce_desc *descriptor, void *memory, int index);
-
-enum ce_sendlist_type_e {
-	CE_SIMPLE_BUFFER_TYPE,
-	/* TBDXXX: CE_RX_DESC_LIST, */
-};
-
-/*
- * There's a public "ce_sendlist" and a private "ce_sendlist_s".
- * The former is an opaque structure with sufficient space
- * to hold the latter.  The latter is the actual structure
- * definition and it is only used internally.  The opaque version
- * of the structure allows callers to allocate an instance on the
- * run-time stack without knowing any of the details of the
- * structure layout.
- */
-struct ce_sendlist_s {
-	unsigned int num_items;
-	struct ce_sendlist_item {
-		enum ce_sendlist_type_e send_type;
-		dma_addr_t data;        /* e.g. buffer or desc list */
-		union {
-			unsigned int nbytes;    /* simple buffer */
-			unsigned int ndesc;     /* Rx descriptor list */
-		} u;
-		/* flags: externally-specified flags;
-		 * OR-ed with internal flags */
-		uint32_t flags;
-		uint32_t user_flags;
-	} item[CE_SENDLIST_ITEMS_MAX];
-};
-
-#ifdef WLAN_FEATURE_FASTPATH
-void ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl);
-#endif
-
-/* which ring of a CE? */
-#define CE_RING_SRC  0
-#define CE_RING_DEST 1
-
-#define CDC_WAR_MAGIC_STR   0xceef0000
-#define CDC_WAR_DATA_CE     4
-
-/* Additional internal-only ce_send flags */
-#define CE_SEND_FLAG_GATHER             0x00010000      /* Use Gather */
-#endif /* __COPY_ENGINE_INTERNAL_H__ */

core/hif/src/ce/ce_main.c

@@ -1,2462 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-#include <osdep.h>
-#include "a_types.h"
-#include "athdefs.h"
-#include "osapi_linux.h"
-#include "targcfg.h"
-#include "cdf_lock.h"
-#include "cdf_status.h"
-#include <cdf_atomic.h>         /* cdf_atomic_read */
-#include <targaddrs.h>
-#include <bmi_msg.h>
-#include "hif_io32.h"
-#include <hif.h>
-#include "regtable.h"
-#define ATH_MODULE_NAME hif
-#include <a_debug.h>
-#include "hif_main.h"
-#ifdef HIF_PCI
-#include "ce_bmi.h"
-#endif
-#include "ce_api.h"
-#include "cdf_trace.h"
-#include "cds_api.h"
-#ifdef CONFIG_CNSS
-#include <net/cnss.h>
-#endif
-#include "epping_main.h"
-#include "hif_debug.h"
-#include "ce_internal.h"
-#include "ce_reg.h"
-#include "ce_assignment.h"
-#include "ce_tasklet.h"
-#ifdef HIF_PCI
-#include "icnss_stub.h"
-#else
-#include <soc/qcom/icnss.h>
-#endif
-#include "qwlan_version.h"
-#include "cds_concurrency.h"
-
-#define CE_POLL_TIMEOUT 10      /* ms */
-
-/* Forward references */
-static int hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info);
-
-/*
- * Fix EV118783, poll to check whether a BMI response comes
- * other than waiting for the interruption which may be lost.
- */
-/* #define BMI_RSP_POLLING */
-#define BMI_RSP_TO_MILLISEC  1000
-
-
-static int hif_post_recv_buffers(struct ol_softc *scn);
-static void hif_config_rri_on_ddr(struct ol_softc *scn);
-
-static void ce_poll_timeout(void *arg)
-{
-	struct CE_state *CE_state = (struct CE_state *)arg;
-	if (CE_state->timer_inited) {
-		ce_per_engine_service(CE_state->scn, CE_state->id);
-		cdf_softirq_timer_mod(&CE_state->poll_timer, CE_POLL_TIMEOUT);
-	}
-}
-
-static unsigned int roundup_pwr2(unsigned int n)
-{
-	int i;
-	unsigned int test_pwr2;
-
-	if (!(n & (n - 1)))
-		return n; /* already a power of 2 */
-
-	test_pwr2 = 4;
-	for (i = 0; i < 29; i++) {
-		if (test_pwr2 > n)
-			return test_pwr2;
-		test_pwr2 = test_pwr2 << 1;
-	}
-
-	CDF_ASSERT(0); /* n too large */
-	return 0;
-}
-
-/*
- * Initialize a Copy Engine based on caller-supplied attributes.
- * This may be called once to initialize both source and destination
- * rings or it may be called twice for separate source and destination
- * initialization. It may be that only one side or the other is
- * initialized by software/firmware.
- *
- * This should be called durring the initialization sequence before
- * interupts are enabled, so we don't have to worry about thread safety.
- */
-struct CE_handle *ce_init(struct ol_softc *scn,
-			  unsigned int CE_id, struct CE_attr *attr)
-{
-	struct CE_state *CE_state;
-	uint32_t ctrl_addr;
-	unsigned int nentries;
-	cdf_dma_addr_t base_addr;
-	bool malloc_CE_state = false;
-	bool malloc_src_ring = false;
-
-	CDF_ASSERT(CE_id < scn->ce_count);
-	ctrl_addr = CE_BASE_ADDRESS(CE_id);
-	CE_state = scn->ce_id_to_state[CE_id];
-
-	if (!CE_state) {
-		CE_state =
-		    (struct CE_state *)cdf_mem_malloc(sizeof(*CE_state));
-		if (!CE_state) {
-			HIF_ERROR("%s: CE_state has no mem", __func__);
-			return NULL;
-		}
-		malloc_CE_state = true;
-		cdf_mem_zero(CE_state, sizeof(*CE_state));
-		scn->ce_id_to_state[CE_id] = CE_state;
-		cdf_spinlock_init(&CE_state->ce_index_lock);
-
-		CE_state->id = CE_id;
-		CE_state->ctrl_addr = ctrl_addr;
-		CE_state->state = CE_RUNNING;
-		CE_state->attr_flags = attr->flags;
-	}
-	CE_state->scn = scn;
-
-	cdf_atomic_init(&CE_state->rx_pending);
-	if (attr == NULL) {
-		/* Already initialized; caller wants the handle */
-		return (struct CE_handle *)CE_state;
-	}
-
-#ifdef ADRASTEA_SHADOW_REGISTERS
-	HIF_ERROR("%s: Using Shadow Registers instead of CE Registers\n",
-		  __func__);
-#endif
-
-	if (CE_state->src_sz_max)
-		CDF_ASSERT(CE_state->src_sz_max == attr->src_sz_max);
-	else
-		CE_state->src_sz_max = attr->src_sz_max;
-
-	ce_init_ce_desc_event_log(CE_id,
-			attr->src_nentries + attr->dest_nentries);
-
-	/* source ring setup */
-	nentries = attr->src_nentries;
-	if (nentries) {
-		struct CE_ring_state *src_ring;
-		unsigned CE_nbytes;
-		char *ptr;
-		uint64_t dma_addr;
-		nentries = roundup_pwr2(nentries);
-		if (CE_state->src_ring) {
-			CDF_ASSERT(CE_state->src_ring->nentries == nentries);
-		} else {
-			CE_nbytes = sizeof(struct CE_ring_state)
-				    + (nentries * sizeof(void *));
-			ptr = cdf_mem_malloc(CE_nbytes);
-			if (!ptr) {
-				/* cannot allocate src ring. If the
-				 * CE_state is allocated locally free
-				 * CE_State and return error.
-				 */
-				HIF_ERROR("%s: src ring has no mem", __func__);
-				if (malloc_CE_state) {
-					/* allocated CE_state locally */
-					scn->ce_id_to_state[CE_id] = NULL;
-					cdf_mem_free(CE_state);
-					malloc_CE_state = false;
-				}
-				return NULL;
-			} else {
-				/* we can allocate src ring.
-				 * Mark that the src ring is
-				 * allocated locally
-				 */
-				malloc_src_ring = true;
-			}
-			cdf_mem_zero(ptr, CE_nbytes);
-
-			src_ring = CE_state->src_ring =
-					   (struct CE_ring_state *)ptr;
-			ptr += sizeof(struct CE_ring_state);
-			src_ring->nentries = nentries;
-			src_ring->nentries_mask = nentries - 1;
-			A_TARGET_ACCESS_BEGIN_RET_PTR(scn);
-			src_ring->hw_index =
-				CE_SRC_RING_READ_IDX_GET(scn, ctrl_addr);
-			src_ring->sw_index = src_ring->hw_index;
-			src_ring->write_index =
-				CE_SRC_RING_WRITE_IDX_GET(scn, ctrl_addr);
-			A_TARGET_ACCESS_END_RET_PTR(scn);
-			src_ring->low_water_mark_nentries = 0;
-			src_ring->high_water_mark_nentries = nentries;
-			src_ring->per_transfer_context = (void **)ptr;
-
-			/* Legacy platforms that do not support cache
-			 * coherent DMA are unsupported
-			 */
-			src_ring->base_addr_owner_space_unaligned =
-				cdf_os_mem_alloc_consistent(scn->cdf_dev,
-						(nentries *
-						sizeof(struct CE_src_desc) +
-						CE_DESC_RING_ALIGN),
-						&base_addr, 0);
-			if (src_ring->base_addr_owner_space_unaligned
-					== NULL) {
-				HIF_ERROR("%s: src ring has no DMA mem",
-					  __func__);
-				goto error_no_dma_mem;
-			}
-			src_ring->base_addr_CE_space_unaligned = base_addr;
-
-			if (src_ring->
-			    base_addr_CE_space_unaligned & (CE_DESC_RING_ALIGN
-							- 1)) {
-				src_ring->base_addr_CE_space =
-					(src_ring->base_addr_CE_space_unaligned
-					+ CE_DESC_RING_ALIGN -
-					 1) & ~(CE_DESC_RING_ALIGN - 1);
-
-				src_ring->base_addr_owner_space =
-					(void
-					 *)(((size_t) src_ring->
-					     base_addr_owner_space_unaligned +
-					     CE_DESC_RING_ALIGN -
-					     1) & ~(CE_DESC_RING_ALIGN - 1));
-			} else {
-				src_ring->base_addr_CE_space =
-					src_ring->base_addr_CE_space_unaligned;
-				src_ring->base_addr_owner_space =
-					src_ring->
-					base_addr_owner_space_unaligned;
-			}
-			/*
-			 * Also allocate a shadow src ring in
-			 * regular mem to use for faster access.
-			 */
-			src_ring->shadow_base_unaligned =
-				cdf_mem_malloc(nentries *
-					       sizeof(struct CE_src_desc) +
-					       CE_DESC_RING_ALIGN);
-			if (src_ring->shadow_base_unaligned == NULL) {
-				HIF_ERROR("%s: src ring no shadow_base mem",
-					  __func__);
-				goto error_no_dma_mem;
-			}
-			src_ring->shadow_base = (struct CE_src_desc *)
-				(((size_t) src_ring->shadow_base_unaligned +
-				CE_DESC_RING_ALIGN - 1) &
-				 ~(CE_DESC_RING_ALIGN - 1));
-
-			A_TARGET_ACCESS_BEGIN_RET_PTR(scn);
-			dma_addr = src_ring->base_addr_CE_space;
-			CE_SRC_RING_BASE_ADDR_SET(scn, ctrl_addr,
-				 (uint32_t)(dma_addr & 0xFFFFFFFF));
-#ifdef WLAN_ENABLE_QCA6180
-			{
-				uint32_t tmp;
-				tmp = CE_SRC_RING_BASE_ADDR_HIGH_GET(
-				   scn, ctrl_addr);
-				tmp &= ~0x1F;
-				dma_addr = ((dma_addr >> 32) & 0x1F)|tmp;
-				CE_SRC_RING_BASE_ADDR_HIGH_SET(scn,
-					 ctrl_addr, (uint32_t)dma_addr);
-			}
-#endif
-			CE_SRC_RING_SZ_SET(scn, ctrl_addr, nentries);
-			CE_SRC_RING_DMAX_SET(scn, ctrl_addr, attr->src_sz_max);
-#ifdef BIG_ENDIAN_HOST
-			/* Enable source ring byte swap for big endian host */
-			CE_SRC_RING_BYTE_SWAP_SET(scn, ctrl_addr, 1);
-#endif
-			CE_SRC_RING_LOWMARK_SET(scn, ctrl_addr, 0);
-			CE_SRC_RING_HIGHMARK_SET(scn, ctrl_addr, nentries);
-			A_TARGET_ACCESS_END_RET_PTR(scn);
-		}
-	}
-
-	/* destination ring setup */
-	nentries = attr->dest_nentries;
-	if (nentries) {
-		struct CE_ring_state *dest_ring;
-		unsigned CE_nbytes;
-		char *ptr;
-		uint64_t dma_addr;
-
-		nentries = roundup_pwr2(nentries);
-		if (CE_state->dest_ring) {
-			CDF_ASSERT(CE_state->dest_ring->nentries == nentries);
-		} else {
-			CE_nbytes = sizeof(struct CE_ring_state)
-				    + (nentries * sizeof(void *));
-			ptr = cdf_mem_malloc(CE_nbytes);
-			if (!ptr) {
-				/* cannot allocate dst ring. If the CE_state
-				 * or src ring is allocated locally free
-				 * CE_State and src ring and return error.
-				 */
-				HIF_ERROR("%s: dest ring has no mem",
-					  __func__);
-				if (malloc_src_ring) {
-					cdf_mem_free(CE_state->src_ring);
-					CE_state->src_ring = NULL;
-					malloc_src_ring = false;
-				}
-				if (malloc_CE_state) {
-					/* allocated CE_state locally */
-					scn->ce_id_to_state[CE_id] = NULL;
-					cdf_mem_free(CE_state);
-					malloc_CE_state = false;
-				}
-				return NULL;
-			}
-			cdf_mem_zero(ptr, CE_nbytes);
-
-			dest_ring = CE_state->dest_ring =
-					    (struct CE_ring_state *)ptr;
-			ptr += sizeof(struct CE_ring_state);
-			dest_ring->nentries = nentries;
-			dest_ring->nentries_mask = nentries - 1;
-			A_TARGET_ACCESS_BEGIN_RET_PTR(scn);
-			dest_ring->sw_index =
-				CE_DEST_RING_READ_IDX_GET(scn, ctrl_addr);
-			dest_ring->write_index =
-				CE_DEST_RING_WRITE_IDX_GET(scn, ctrl_addr);
-			A_TARGET_ACCESS_END_RET_PTR(scn);
-			dest_ring->low_water_mark_nentries = 0;
-			dest_ring->high_water_mark_nentries = nentries;
-			dest_ring->per_transfer_context = (void **)ptr;
-
-			/* Legacy platforms that do not support cache
-			 * coherent DMA are unsupported */
-			dest_ring->base_addr_owner_space_unaligned =
-				cdf_os_mem_alloc_consistent(scn->cdf_dev,
-						(nentries *
-						sizeof(struct CE_dest_desc) +
-						CE_DESC_RING_ALIGN),
-						&base_addr, 0);
-			if (dest_ring->base_addr_owner_space_unaligned
-				== NULL) {
-				HIF_ERROR("%s: dest ring has no DMA mem",
-					  __func__);
-				goto error_no_dma_mem;
-			}
-			dest_ring->base_addr_CE_space_unaligned = base_addr;
-
-			/* Correctly initialize memory to 0 to
-			 * prevent garbage data crashing system
-			 * when download firmware
-			 */
-			cdf_mem_zero(dest_ring->base_addr_owner_space_unaligned,
-				  nentries * sizeof(struct CE_dest_desc) +
-				  CE_DESC_RING_ALIGN);
-
-			if (dest_ring->
-			    base_addr_CE_space_unaligned & (CE_DESC_RING_ALIGN -
-							    1)) {
-
-				dest_ring->base_addr_CE_space =
-					(dest_ring->
-					 base_addr_CE_space_unaligned +
-					 CE_DESC_RING_ALIGN -
-					 1) & ~(CE_DESC_RING_ALIGN - 1);
-
-				dest_ring->base_addr_owner_space =
-					(void
-					 *)(((size_t) dest_ring->
-					     base_addr_owner_space_unaligned +
-					     CE_DESC_RING_ALIGN -
-					     1) & ~(CE_DESC_RING_ALIGN - 1));
-			} else {
-				dest_ring->base_addr_CE_space =
-					dest_ring->base_addr_CE_space_unaligned;
-				dest_ring->base_addr_owner_space =
-					dest_ring->
-					base_addr_owner_space_unaligned;
-			}
-
-			A_TARGET_ACCESS_BEGIN_RET_PTR(scn);
-			dma_addr = dest_ring->base_addr_CE_space;
-			CE_DEST_RING_BASE_ADDR_SET(scn, ctrl_addr,
-				 (uint32_t)(dma_addr & 0xFFFFFFFF));
-#ifdef WLAN_ENABLE_QCA6180
-			{
-				uint32_t tmp;
-				tmp = CE_DEST_RING_BASE_ADDR_HIGH_GET(scn,
-						ctrl_addr);
-				tmp &= ~0x1F;
-				dma_addr = ((dma_addr >> 32) & 0x1F)|tmp;
-				CE_DEST_RING_BASE_ADDR_HIGH_SET(scn,
-					ctrl_addr, (uint32_t)dma_addr);
-			}
-#endif
-			CE_DEST_RING_SZ_SET(scn, ctrl_addr, nentries);
-#ifdef BIG_ENDIAN_HOST
-			/* Enable Dest ring byte swap for big endian host */
-			CE_DEST_RING_BYTE_SWAP_SET(scn, ctrl_addr, 1);
-#endif
-			CE_DEST_RING_LOWMARK_SET(scn, ctrl_addr, 0);
-			CE_DEST_RING_HIGHMARK_SET(scn, ctrl_addr, nentries);
-			A_TARGET_ACCESS_END_RET_PTR(scn);
-
-			/* epping */
-			/* poll timer */
-			if ((CE_state->attr_flags & CE_ATTR_ENABLE_POLL)) {
-				cdf_softirq_timer_init(scn->cdf_dev,
-						       &CE_state->poll_timer,
-						       ce_poll_timeout,
-						       CE_state,
-						       CDF_TIMER_TYPE_SW);
-				CE_state->timer_inited = true;
-				cdf_softirq_timer_mod(&CE_state->poll_timer,
-						      CE_POLL_TIMEOUT);
-			}
-		}
-	}
-
-	/* Enable CE error interrupts */
-	A_TARGET_ACCESS_BEGIN_RET_PTR(scn);
-	CE_ERROR_INTR_ENABLE(scn, ctrl_addr);
-	A_TARGET_ACCESS_END_RET_PTR(scn);
-
-	return (struct CE_handle *)CE_state;
-
-error_no_dma_mem:
-	ce_fini((struct CE_handle *)CE_state);
-	return NULL;
-}
-
-#ifdef WLAN_FEATURE_FASTPATH
-/**
- * ce_h2t_tx_ce_cleanup() Place holder function for H2T CE cleanup.
- * No processing is required inside this function.
- * @ce_hdl: Cope engine handle
- * Using an assert, this function makes sure that,
- * the TX CE has been processed completely.
- *
- * This is called while dismantling CE structures. No other thread
- * should be using these structures while dismantling is occuring
- * therfore no locking is needed.
- *
- * Return: none
- */
-void
-ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl)
-{
-	struct CE_state *ce_state = (struct CE_state *)ce_hdl;
-	struct CE_ring_state *src_ring = ce_state->src_ring;
-	struct ol_softc *sc = ce_state->scn;
-	uint32_t sw_index, write_index;
-
-	if (sc->fastpath_mode_on && (ce_state->id == CE_HTT_H2T_MSG)) {
-		HIF_INFO("%s %d Fastpath mode ON, Cleaning up HTT Tx CE\n",
-			  __func__, __LINE__);
-		sw_index = src_ring->sw_index;
-		write_index = src_ring->sw_index;
-
-		/* At this point Tx CE should be clean */
-		cdf_assert_always(sw_index == write_index);
-	}
-}
-#else
-void ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl)
-{
-}
-#endif /* WLAN_FEATURE_FASTPATH */
-
-void ce_fini(struct CE_handle *copyeng)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	unsigned int CE_id = CE_state->id;
-	struct ol_softc *scn = CE_state->scn;
-
-	CE_state->state = CE_UNUSED;
-	scn->ce_id_to_state[CE_id] = NULL;
-	if (CE_state->src_ring) {
-		/* Cleanup the HTT Tx ring */
-		ce_h2t_tx_ce_cleanup(copyeng);
-
-		if (CE_state->src_ring->shadow_base_unaligned)
-			cdf_mem_free(CE_state->src_ring->shadow_base_unaligned);
-		if (CE_state->src_ring->base_addr_owner_space_unaligned)
-			cdf_os_mem_free_consistent(scn->cdf_dev,
-					    (CE_state->src_ring->nentries *
-					     sizeof(struct CE_src_desc) +
-					     CE_DESC_RING_ALIGN),
-					    CE_state->src_ring->
-					    base_addr_owner_space_unaligned,
-					    CE_state->src_ring->
-					    base_addr_CE_space, 0);
-		cdf_mem_free(CE_state->src_ring);
-	}
-	if (CE_state->dest_ring) {
-		if (CE_state->dest_ring->base_addr_owner_space_unaligned)
-			cdf_os_mem_free_consistent(scn->cdf_dev,
-					    (CE_state->dest_ring->nentries *
-					     sizeof(struct CE_dest_desc) +
-					     CE_DESC_RING_ALIGN),
-					    CE_state->dest_ring->
-					    base_addr_owner_space_unaligned,
-					    CE_state->dest_ring->
-					    base_addr_CE_space, 0);
-		cdf_mem_free(CE_state->dest_ring);
-
-		/* epping */
-		if (CE_state->timer_inited) {
-			CE_state->timer_inited = false;
-			cdf_softirq_timer_free(&CE_state->poll_timer);
-		}
-	}
-	cdf_mem_free(CE_state);
-}
-
-void hif_detach_htc(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-
-	cdf_mem_zero(&hif_state->msg_callbacks_pending,
-		  sizeof(hif_state->msg_callbacks_pending));
-	cdf_mem_zero(&hif_state->msg_callbacks_current,
-		  sizeof(hif_state->msg_callbacks_current));
-}
-
-/* Send the first nbytes bytes of the buffer */
-CDF_STATUS
-hif_send_head(struct ol_softc *scn,
-	      uint8_t pipe, unsigned int transfer_id, unsigned int nbytes,
-	      cdf_nbuf_t nbuf, unsigned int data_attr)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]);
-	struct CE_handle *ce_hdl = pipe_info->ce_hdl;
-	int bytes = nbytes, nfrags = 0;
-	struct ce_sendlist sendlist;
-	int status, i = 0;
-	unsigned int mux_id = 0;
-
-	CDF_ASSERT(nbytes <= cdf_nbuf_len(nbuf));
-
-	transfer_id =
-		(mux_id & MUX_ID_MASK) |
-		(transfer_id & TRANSACTION_ID_MASK);
-	data_attr &= DESC_DATA_FLAG_MASK;
-	/*
-	 * The common case involves sending multiple fragments within a
-	 * single download (the tx descriptor and the tx frame header).
-	 * So, optimize for the case of multiple fragments by not even
-	 * checking whether it's necessary to use a sendlist.
-	 * The overhead of using a sendlist for a single buffer download
-	 * is not a big deal, since it happens rarely (for WMI messages).
-	 */
-	ce_sendlist_init(&sendlist);
-	do {
-		uint32_t frag_paddr;
-		int frag_bytes;
-
-		frag_paddr = cdf_nbuf_get_frag_paddr_lo(nbuf, nfrags);
-		frag_bytes = cdf_nbuf_get_frag_len(nbuf, nfrags);
-		/*
-		 * Clear the packet offset for all but the first CE desc.
-		 */
-		if (i++ > 0)
-			data_attr &= ~CDF_CE_TX_PKT_OFFSET_BIT_M;
-
-		status = ce_sendlist_buf_add(&sendlist, frag_paddr,
-				    frag_bytes >
-				    bytes ? bytes : frag_bytes,
-				    cdf_nbuf_get_frag_is_wordstream
-				    (nbuf,
-				    nfrags) ? 0 :
-				    CE_SEND_FLAG_SWAP_DISABLE,
-				    data_attr);
-		if (status != CDF_STATUS_SUCCESS) {
-			HIF_ERROR("%s: error, frag_num %d larger than limit",
-				__func__, nfrags);
-			return status;
-		}
-		bytes -= frag_bytes;
-		nfrags++;
-	} while (bytes > 0);
-
-	/* Make sure we have resources to handle this request */
-	cdf_spin_lock_bh(&pipe_info->completion_freeq_lock);
-	if (pipe_info->num_sends_allowed < nfrags) {
-		cdf_spin_unlock_bh(&pipe_info->completion_freeq_lock);
-		ce_pkt_error_count_incr(hif_state, HIF_PIPE_NO_RESOURCE);
-		return CDF_STATUS_E_RESOURCES;
-	}
-	pipe_info->num_sends_allowed -= nfrags;
-	cdf_spin_unlock_bh(&pipe_info->completion_freeq_lock);
-
-	if (cdf_unlikely(ce_hdl == NULL)) {
-		HIF_ERROR("%s: error CE handle is null", __func__);
-		return A_ERROR;
-	}
-
-	NBUF_UPDATE_TX_PKT_COUNT(nbuf, NBUF_TX_PKT_HIF);
-	DPTRACE(cdf_dp_trace(nbuf, CDF_DP_TRACE_HIF_PACKET_PTR_RECORD,
-				(uint8_t *)(cdf_nbuf_data(nbuf)),
-				sizeof(cdf_nbuf_data(nbuf))));
-	status = ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id);
-	CDF_ASSERT(status == CDF_STATUS_SUCCESS);
-
-	return status;
-}
-
-void hif_send_complete_check(struct ol_softc *scn, uint8_t pipe, int force)
-{
-	if (!force) {
-		int resources;
-		/*
-		 * Decide whether to actually poll for completions, or just
-		 * wait for a later chance. If there seem to be plenty of
-		 * resources left, then just wait, since checking involves
-		 * reading a CE register, which is a relatively expensive
-		 * operation.
-		 */
-		resources = hif_get_free_queue_number(scn, pipe);
-		/*
-		 * If at least 50% of the total resources are still available,
-		 * don't bother checking again yet.
-		 */
-		if (resources > (host_ce_config[pipe].src_nentries >> 1)) {
-			return;
-		}
-	}
-#ifdef  ATH_11AC_TXCOMPACT
-	ce_per_engine_servicereap(scn, pipe);
-#else
-	ce_per_engine_service(scn, pipe);
-#endif
-}
-
-uint16_t hif_get_free_queue_number(struct ol_softc *scn, uint8_t pipe)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]);
-	uint16_t rv;
-
-	cdf_spin_lock_bh(&pipe_info->completion_freeq_lock);
-	rv = pipe_info->num_sends_allowed;
-	cdf_spin_unlock_bh(&pipe_info->completion_freeq_lock);
-	return rv;
-}
-
-/* Called by lower (CE) layer when a send to Target completes. */
-void
-hif_pci_ce_send_done(struct CE_handle *copyeng, void *ce_context,
-		     void *transfer_context, cdf_dma_addr_t CE_data,
-		     unsigned int nbytes, unsigned int transfer_id,
-		     unsigned int sw_index, unsigned int hw_index,
-		     unsigned int toeplitz_hash_result)
-{
-	struct HIF_CE_pipe_info *pipe_info =
-		(struct HIF_CE_pipe_info *)ce_context;
-	struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state;
-	unsigned int sw_idx = sw_index, hw_idx = hw_index;
-	struct hif_msg_callbacks *msg_callbacks =
-		&hif_state->msg_callbacks_current;
-
-	do {
-		/*
-		 * The upper layer callback will be triggered
-		 * when last fragment is complteted.
-		 */
-		if (transfer_context != CE_SENDLIST_ITEM_CTXT) {
-			if (hif_state->scn->target_status
-					== OL_TRGET_STATUS_RESET)
-				cdf_nbuf_free(transfer_context);
-			else
-				msg_callbacks->txCompletionHandler(
-					msg_callbacks->Context,
-					transfer_context, transfer_id,
-					toeplitz_hash_result);
-		}
-
-		cdf_spin_lock(&pipe_info->completion_freeq_lock);
-		pipe_info->num_sends_allowed++;
-		cdf_spin_unlock(&pipe_info->completion_freeq_lock);
-	} while (ce_completed_send_next(copyeng,
-			&ce_context, &transfer_context,
-			&CE_data, &nbytes, &transfer_id,
-			&sw_idx, &hw_idx,
-			&toeplitz_hash_result) == CDF_STATUS_SUCCESS);
-}
-
-/**
- * hif_ce_do_recv(): send message from copy engine to upper layers
- * @msg_callbacks: structure containing callback and callback context
- * @netbuff: skb containing message
- * @nbytes: number of bytes in the message
- * @pipe_info: used for the pipe_number info
- *
- * Checks the packet length, configures the lenght in the netbuff,
- * and calls the upper layer callback.
- *
- * return: None
- */
-static inline void hif_ce_do_recv(struct hif_msg_callbacks *msg_callbacks,
-		cdf_nbuf_t netbuf, int nbytes,
-		struct HIF_CE_pipe_info *pipe_info) {
-	if (nbytes <= pipe_info->buf_sz) {
-		cdf_nbuf_set_pktlen(netbuf, nbytes);
-		msg_callbacks->
-			rxCompletionHandler(msg_callbacks->Context,
-					netbuf, pipe_info->pipe_num);
-	} else {
-		HIF_ERROR("%s: Invalid Rx msg buf:%p nbytes:%d",
-				__func__, netbuf, nbytes);
-		cdf_nbuf_free(netbuf);
-	}
-}
-
-/* Called by lower (CE) layer when data is received from the Target. */
-void
-hif_pci_ce_recv_data(struct CE_handle *copyeng, void *ce_context,
-		     void *transfer_context, cdf_dma_addr_t CE_data,
-		     unsigned int nbytes, unsigned int transfer_id,
-		     unsigned int flags)
-{
-	struct HIF_CE_pipe_info *pipe_info =
-		(struct HIF_CE_pipe_info *)ce_context;
-	struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state;
-	struct CE_state *ce_state = (struct CE_state *) copyeng;
-	struct ol_softc *scn = hif_state->scn;
-	struct hif_msg_callbacks *msg_callbacks =
-		&hif_state->msg_callbacks_current;
-
-	do {
-		hif_pm_runtime_mark_last_busy(scn->hif_sc->dev);
-		cdf_nbuf_unmap_single(scn->cdf_dev,
-				      (cdf_nbuf_t) transfer_context,
-				      CDF_DMA_FROM_DEVICE);
-
-		atomic_inc(&pipe_info->recv_bufs_needed);
-		hif_post_recv_buffers_for_pipe(pipe_info);
-		if (hif_state->scn->target_status == OL_TRGET_STATUS_RESET)
-			cdf_nbuf_free(transfer_context);
-		else
-			hif_ce_do_recv(msg_callbacks, transfer_context,
-				nbytes, pipe_info);
-
-		/* Set up force_break flag if num of receices reaches
-		 * MAX_NUM_OF_RECEIVES */
-		ce_state->receive_count++;
-		if (cdf_unlikely(hif_max_num_receives_reached(
-				ce_state->receive_count))) {
-			ce_state->force_break = 1;
-			break;
-		}
-	} while (ce_completed_recv_next(copyeng, &ce_context, &transfer_context,
-					&CE_data, &nbytes, &transfer_id,
-					&flags) == CDF_STATUS_SUCCESS);
-
-}
-
-/* TBDXXX: Set CE High Watermark; invoke txResourceAvailHandler in response */
-
-void
-hif_post_init(struct ol_softc *scn, void *unused,
-	      struct hif_msg_callbacks *callbacks)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-	spin_lock_init(&pcie_access_log_lock);
-#endif
-	/* Save callbacks for later installation */
-	cdf_mem_copy(&hif_state->msg_callbacks_pending, callbacks,
-		 sizeof(hif_state->msg_callbacks_pending));
-
-}
-
-int hif_completion_thread_startup(struct HIF_CE_state *hif_state)
-{
-	struct CE_handle *ce_diag = hif_state->ce_diag;
-	int pipe_num;
-	struct ol_softc *scn = hif_state->scn;
-	struct hif_msg_callbacks *hif_msg_callbacks =
-		&hif_state->msg_callbacks_current;
-
-	/* daemonize("hif_compl_thread"); */
-
-	if (scn->ce_count == 0) {
-		HIF_ERROR("%s: Invalid ce_count\n", __func__);
-		return -EINVAL;
-	}
-
-	if (!hif_msg_callbacks ||
-			!hif_msg_callbacks->rxCompletionHandler ||
-			!hif_msg_callbacks->txCompletionHandler) {
-		HIF_ERROR("%s: no completion handler registered", __func__);
-		return -EFAULT;
-	}
-
-	A_TARGET_ACCESS_LIKELY(scn);
-	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
-		struct CE_attr attr;
-		struct HIF_CE_pipe_info *pipe_info;
-
-		pipe_info = &hif_state->pipe_info[pipe_num];
-		if (pipe_info->ce_hdl == ce_diag) {
-			continue;       /* Handle Diagnostic CE specially */
-		}
-		attr = host_ce_config[pipe_num];
-		if (attr.src_nentries) {
-			/* pipe used to send to target */
-			HIF_INFO_MED("%s: pipe_num:%d pipe_info:0x%p",
-					 __func__, pipe_num, pipe_info);
-			ce_send_cb_register(pipe_info->ce_hdl,
-					    hif_pci_ce_send_done, pipe_info,
-					    attr.flags & CE_ATTR_DISABLE_INTR);
-			pipe_info->num_sends_allowed = attr.src_nentries - 1;
-		}
-		if (attr.dest_nentries) {
-			/* pipe used to receive from target */
-			ce_recv_cb_register(pipe_info->ce_hdl,
-					    hif_pci_ce_recv_data, pipe_info,
-					    attr.flags & CE_ATTR_DISABLE_INTR);
-		}
-
-		if (attr.src_nentries)
-			cdf_spinlock_init(&pipe_info->completion_freeq_lock);
-	}
-
-	A_TARGET_ACCESS_UNLIKELY(scn);
-	return 0;
-}
-
-/*
- * Install pending msg callbacks.
- *
- * TBDXXX: This hack is needed because upper layers install msg callbacks
- * for use with HTC before BMI is done; yet this HIF implementation
- * needs to continue to use BMI msg callbacks. Really, upper layers
- * should not register HTC callbacks until AFTER BMI phase.
- */
-static void hif_msg_callbacks_install(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-
-	cdf_mem_copy(&hif_state->msg_callbacks_current,
-		 &hif_state->msg_callbacks_pending,
-		 sizeof(hif_state->msg_callbacks_pending));
-}
-
-void
-hif_get_default_pipe(struct ol_softc *scn, uint8_t *ULPipe, uint8_t *DLPipe)
-{
-	int ul_is_polled, dl_is_polled;
-
-	(void)hif_map_service_to_pipe(scn, HTC_CTRL_RSVD_SVC,
-		ULPipe, DLPipe, &ul_is_polled, &dl_is_polled);
-}
-
-/**
- * hif_dump_pipe_debug_count() - Log error count
- * @scn: ol_softc pointer.
- *
- * Output the pipe error counts of each pipe to log file
- *
- * Return: N/A
- */
-void hif_dump_pipe_debug_count(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state;
-	int pipe_num;
-
-	if (scn == NULL) {
-		HIF_ERROR("%s scn is NULL", __func__);
-		return;
-	}
-	hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	if (hif_state == NULL) {
-		HIF_ERROR("%s hif_state is NULL", __func__);
-		return;
-	}
-	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
-		struct HIF_CE_pipe_info *pipe_info;
-
-	pipe_info = &hif_state->pipe_info[pipe_num];
-
-	if (pipe_info->nbuf_alloc_err_count > 0 ||
-			pipe_info->nbuf_dma_err_count > 0 ||
-			pipe_info->nbuf_ce_enqueue_err_count)
-		HIF_ERROR(
-			"%s: pipe_id = %d, recv_bufs_needed = %d, nbuf_alloc_err_count = %u, nbuf_dma_err_count = %u, nbuf_ce_enqueue_err_count = %u",
-			__func__, pipe_info->pipe_num,
-			atomic_read(&pipe_info->recv_bufs_needed),
-			pipe_info->nbuf_alloc_err_count,
-			pipe_info->nbuf_dma_err_count,
-			pipe_info->nbuf_ce_enqueue_err_count);
-	}
-}
-
-static int hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info)
-{
-	struct CE_handle *ce_hdl;
-	cdf_size_t buf_sz;
-	struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state;
-	struct ol_softc *scn = hif_state->scn;
-	CDF_STATUS ret;
-	uint32_t bufs_posted = 0;
-
-	buf_sz = pipe_info->buf_sz;
-	if (buf_sz == 0) {
-		/* Unused Copy Engine */
-		return 0;
-	}
-
-	ce_hdl = pipe_info->ce_hdl;
-
-	cdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock);
-	while (atomic_read(&pipe_info->recv_bufs_needed) > 0) {
-		cdf_dma_addr_t CE_data;      /* CE space buffer address */
-		cdf_nbuf_t nbuf;
-		int status;
-
-		atomic_dec(&pipe_info->recv_bufs_needed);
-		cdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock);
-
-		nbuf = cdf_nbuf_alloc(scn->cdf_dev, buf_sz, 0, 4, false);
-		if (!nbuf) {
-			cdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock);
-			pipe_info->nbuf_alloc_err_count++;
-			cdf_spin_unlock_bh(
-				&pipe_info->recv_bufs_needed_lock);
-			HIF_ERROR(
-				"%s buf alloc error [%d] needed %d, nbuf_alloc_err_count = %u",
-				 __func__, pipe_info->pipe_num,
-				 atomic_read(&pipe_info->recv_bufs_needed),
-				pipe_info->nbuf_alloc_err_count);
-			atomic_inc(&pipe_info->recv_bufs_needed);
-			return 1;
-		}
-
-		/*
-		 * cdf_nbuf_peek_header(nbuf, &data, &unused);
-		 * CE_data = dma_map_single(dev, data, buf_sz, );
-		 * DMA_FROM_DEVICE);
-		 */
-		ret =
-			cdf_nbuf_map_single(scn->cdf_dev, nbuf,
-					    CDF_DMA_FROM_DEVICE);
-
-		if (unlikely(ret != CDF_STATUS_SUCCESS)) {
-			cdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock);
-			pipe_info->nbuf_dma_err_count++;
-			cdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock);
-			HIF_ERROR(
-				"%s buf alloc error [%d] needed %d, nbuf_dma_err_count = %u",
-				 __func__, pipe_info->pipe_num,
-				 atomic_read(&pipe_info->recv_bufs_needed),
-				pipe_info->nbuf_dma_err_count);
-			cdf_nbuf_free(nbuf);
-			atomic_inc(&pipe_info->recv_bufs_needed);
-			return 1;
-		}
-
-		CE_data = cdf_nbuf_get_frag_paddr_lo(nbuf, 0);
-
-		cdf_os_mem_dma_sync_single_for_device(scn->cdf_dev, CE_data,
-					       buf_sz, DMA_FROM_DEVICE);
-		status = ce_recv_buf_enqueue(ce_hdl, (void *)nbuf, CE_data);
-		CDF_ASSERT(status == CDF_STATUS_SUCCESS);
-		if (status != EOK) {
-			cdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock);
-			pipe_info->nbuf_ce_enqueue_err_count++;
-			cdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock);
-			HIF_ERROR(
-				"%s buf alloc error [%d] needed %d, nbuf_alloc_err_count = %u",
-				__func__, pipe_info->pipe_num,
-				atomic_read(&pipe_info->recv_bufs_needed),
-				pipe_info->nbuf_ce_enqueue_err_count);
-			atomic_inc(&pipe_info->recv_bufs_needed);
-			cdf_nbuf_free(nbuf);
-			return 1;
-		}
-
-		cdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock);
-		bufs_posted++;
-	}
-	pipe_info->nbuf_alloc_err_count =
-		(pipe_info->nbuf_alloc_err_count > bufs_posted)?
-		pipe_info->nbuf_alloc_err_count - bufs_posted : 0;
-	pipe_info->nbuf_dma_err_count =
-		(pipe_info->nbuf_dma_err_count > bufs_posted)?
-		pipe_info->nbuf_dma_err_count - bufs_posted : 0;
-	pipe_info->nbuf_ce_enqueue_err_count =
-		(pipe_info->nbuf_ce_enqueue_err_count > bufs_posted)?
-	     pipe_info->nbuf_ce_enqueue_err_count - bufs_posted : 0;
-
-	cdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock);
-
-	return 0;
-}
-
-/*
- * Try to post all desired receive buffers for all pipes.
- * Returns 0 if all desired buffers are posted,
- * non-zero if were were unable to completely
- * replenish receive buffers.
- */
-static int hif_post_recv_buffers(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	int pipe_num, rv = 0;
-
-	A_TARGET_ACCESS_LIKELY(scn);
-	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
-		struct HIF_CE_pipe_info *pipe_info;
-
-		pipe_info = &hif_state->pipe_info[pipe_num];
-		if (hif_post_recv_buffers_for_pipe(pipe_info)) {
-			rv = 1;
-			goto done;
-		}
-	}
-
-done:
-	A_TARGET_ACCESS_UNLIKELY(scn);
-
-	return rv;
-}
-
-CDF_STATUS hif_start(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-
-	hif_msg_callbacks_install(scn);
-
-	if (hif_completion_thread_startup(hif_state))
-		return CDF_STATUS_E_FAILURE;
-
-	/* Post buffers once to start things off. */
-	(void)hif_post_recv_buffers(scn);
-
-	hif_state->started = true;
-
-	return CDF_STATUS_SUCCESS;
-}
-
-#ifdef WLAN_FEATURE_FASTPATH
-/**
- * hif_enable_fastpath() Update that we have enabled fastpath mode
- * @hif_device: HIF context
- *
- * For use in data path
- *
- * Retrun: void
- */
-void
-hif_enable_fastpath(struct ol_softc *hif_device)
-{
-	HIF_INFO("Enabling fastpath mode\n");
-	hif_device->fastpath_mode_on = 1;
-}
-#endif /* WLAN_FEATURE_FASTPATH */
-
-void hif_recv_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info)
-{
-	struct ol_softc *scn;
-	struct CE_handle *ce_hdl;
-	uint32_t buf_sz;
-	struct HIF_CE_state *hif_state;
-	cdf_nbuf_t netbuf;
-	cdf_dma_addr_t CE_data;
-	void *per_CE_context;
-
-	buf_sz = pipe_info->buf_sz;
-	if (buf_sz == 0) {
-		/* Unused Copy Engine */
-		return;
-	}
-
-	hif_state = pipe_info->HIF_CE_state;
-	if (!hif_state->started) {
-		return;
-	}
-
-	scn = hif_state->scn;
-	ce_hdl = pipe_info->ce_hdl;
-
-	if (scn->cdf_dev == NULL) {
-		return;
-	}
-	while (ce_revoke_recv_next
-		       (ce_hdl, &per_CE_context, (void **)&netbuf,
-			&CE_data) == CDF_STATUS_SUCCESS) {
-		cdf_nbuf_unmap_single(scn->cdf_dev, netbuf,
-				      CDF_DMA_FROM_DEVICE);
-		cdf_nbuf_free(netbuf);
-	}
-}
-
-void hif_send_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info)
-{
-	struct CE_handle *ce_hdl;
-	struct HIF_CE_state *hif_state;
-	cdf_nbuf_t netbuf;
-	void *per_CE_context;
-	cdf_dma_addr_t CE_data;
-	unsigned int nbytes;
-	unsigned int id;
-	uint32_t buf_sz;
-	uint32_t toeplitz_hash_result;
-
-	buf_sz = pipe_info->buf_sz;
-	if (buf_sz == 0) {
-		/* Unused Copy Engine */
-		return;
-	}
-
-	hif_state = pipe_info->HIF_CE_state;
-	if (!hif_state->started) {
-		return;
-	}
-
-	ce_hdl = pipe_info->ce_hdl;
-
-	while (ce_cancel_send_next
-		       (ce_hdl, &per_CE_context,
-		       (void **)&netbuf, &CE_data, &nbytes,
-		       &id, &toeplitz_hash_result) == CDF_STATUS_SUCCESS) {
-		if (netbuf != CE_SENDLIST_ITEM_CTXT) {
-			/*
-			 * Packets enqueued by htt_h2t_ver_req_msg() and
-			 * htt_h2t_rx_ring_cfg_msg_ll() have already been
-			 * freed in htt_htc_misc_pkt_pool_free() in
-			 * wlantl_close(), so do not free them here again
-			 * by checking whether it's the endpoint
-			 * which they are queued in.
-			 */
-			if (id == hif_state->scn->htc_endpoint)
-				return;
-			/* Indicate the completion to higer
-			 * layer to free the buffer */
-			hif_state->msg_callbacks_current.
-			txCompletionHandler(hif_state->
-					    msg_callbacks_current.Context,
-					    netbuf, id, toeplitz_hash_result);
-		}
-	}
-}
-
-/*
- * Cleanup residual buffers for device shutdown:
- *    buffers that were enqueued for receive
- *    buffers that were to be sent
- * Note: Buffers that had completed but which were
- * not yet processed are on a completion queue. They
- * are handled when the completion thread shuts down.
- */
-void hif_buffer_cleanup(struct HIF_CE_state *hif_state)
-{
-	int pipe_num;
-
-	for (pipe_num = 0; pipe_num < hif_state->scn->ce_count; pipe_num++) {
-		struct HIF_CE_pipe_info *pipe_info;
-
-		pipe_info = &hif_state->pipe_info[pipe_num];
-		hif_recv_buffer_cleanup_on_pipe(pipe_info);
-		hif_send_buffer_cleanup_on_pipe(pipe_info);
-	}
-}
-
-void hif_flush_surprise_remove(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	hif_buffer_cleanup(hif_state);
-}
-
-void hif_stop(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	int pipe_num;
-
-	scn->hif_init_done = false;
-
-	/*
-	 * At this point, asynchronous threads are stopped,
-	 * The Target should not DMA nor interrupt, Host code may
-	 * not initiate anything more.  So we just need to clean
-	 * up Host-side state.
-	 */
-
-	if (scn->athdiag_procfs_inited) {
-		athdiag_procfs_remove();
-		scn->athdiag_procfs_inited = false;
-	}
-
-	hif_buffer_cleanup(hif_state);
-
-	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
-		struct HIF_CE_pipe_info *pipe_info;
-
-		pipe_info = &hif_state->pipe_info[pipe_num];
-		if (pipe_info->ce_hdl) {
-			ce_fini(pipe_info->ce_hdl);
-			pipe_info->ce_hdl = NULL;
-			pipe_info->buf_sz = 0;
-		}
-	}
-
-	if (hif_state->sleep_timer_init) {
-		cdf_softirq_timer_cancel(&hif_state->sleep_timer);
-		cdf_softirq_timer_free(&hif_state->sleep_timer);
-		hif_state->sleep_timer_init = false;
-	}
-
-	hif_state->started = false;
-}
-
-#define ADRASTEA_SRC_WR_INDEX_OFFSET 0x3C
-#define ADRASTEA_DST_WR_INDEX_OFFSET 0x40
-
-
-static struct shadow_reg_cfg target_shadow_reg_cfg_map[] = {
-	{ 0, ADRASTEA_SRC_WR_INDEX_OFFSET},
-	{ 3, ADRASTEA_SRC_WR_INDEX_OFFSET},
-	{ 4, ADRASTEA_SRC_WR_INDEX_OFFSET},
-	{ 5, ADRASTEA_SRC_WR_INDEX_OFFSET},
-	{ 7, ADRASTEA_SRC_WR_INDEX_OFFSET},
-	{ 1, ADRASTEA_DST_WR_INDEX_OFFSET},
-	{ 2, ADRASTEA_DST_WR_INDEX_OFFSET},
-	{ 7, ADRASTEA_DST_WR_INDEX_OFFSET},
-	{ 8, ADRASTEA_DST_WR_INDEX_OFFSET},
-};
-
-
-
-/* CE_PCI TABLE */
-/*
- * NOTE: the table below is out of date, though still a useful reference.
- * Refer to target_service_to_ce_map and hif_map_service_to_pipe for the actual
- * mapping of HTC services to HIF pipes.
- */
-/*
- * This authoritative table defines Copy Engine configuration and the mapping
- * of services/endpoints to CEs.  A subset of this information is passed to
- * the Target during startup as a prerequisite to entering BMI phase.
- * See:
- *    target_service_to_ce_map - Target-side mapping
- *    hif_map_service_to_pipe      - Host-side mapping
- *    target_ce_config         - Target-side configuration
- *    host_ce_config           - Host-side configuration
-   ============================================================================
-   Purpose    | Service / Endpoint   | CE   | Dire | Xfer     | Xfer
- |                      |      | ctio | Size     | Frequency
- |                      |      | n    |          |
-   ============================================================================
-   tx         | HTT_DATA (downlink)  | CE 0 | h->t | medium - | very frequent
-   descriptor |                      |      |      | O(100B)  | and regular
-   download   |                      |      |      |          |
-   ----------------------------------------------------------------------------
-   rx         | HTT_DATA (uplink)    | CE 1 | t->h | small -  | frequent and
-   indication |                      |      |      | O(10B)   | regular
-   upload     |                      |      |      |          |
-   ----------------------------------------------------------------------------
-   MSDU       | DATA_BK (uplink)     | CE 2 | t->h | large -  | rare
-   upload     |                      |      |      | O(1000B) | (frequent
-   e.g. noise |                      |      |      |          | during IP1.0
-   packets    |                      |      |      |          | testing)
-   ----------------------------------------------------------------------------
-   MSDU       | DATA_BK (downlink)   | CE 3 | h->t | large -  | very rare
-   download   |                      |      |      | O(1000B) | (frequent
-   e.g.       |                      |      |      |          | during IP1.0
-   misdirecte |                      |      |      |          | testing)
-   d EAPOL    |                      |      |      |          |
-   packets    |                      |      |      |          |
-   ----------------------------------------------------------------------------
-   n/a        | DATA_BE, DATA_VI     | CE 2 | t->h |          | never(?)
- | DATA_VO (uplink)     |      |      |          |
-   ----------------------------------------------------------------------------
-   n/a        | DATA_BE, DATA_VI     | CE 3 | h->t |          | never(?)
- | DATA_VO (downlink)   |      |      |          |
-   ----------------------------------------------------------------------------
-   WMI events | WMI_CONTROL (uplink) | CE 4 | t->h | medium - | infrequent
- |                      |      |      | O(100B)  |
-   ----------------------------------------------------------------------------
-   WMI        | WMI_CONTROL          | CE 5 | h->t | medium - | infrequent
-   messages   | (downlink)           |      |      | O(100B)  |
- |                      |      |      |          |
-   ----------------------------------------------------------------------------
-   n/a        | HTC_CTRL_RSVD,       | CE 1 | t->h |          | never(?)
- | HTC_RAW_STREAMS      |      |      |          |
- | (uplink)             |      |      |          |
-   ----------------------------------------------------------------------------
-   n/a        | HTC_CTRL_RSVD,       | CE 0 | h->t |          | never(?)
- | HTC_RAW_STREAMS      |      |      |          |
- | (downlink)           |      |      |          |
-   ----------------------------------------------------------------------------
-   diag       | none (raw CE)        | CE 7 | t<>h |    4     | Diag Window
- |                      |      |      |          | infrequent
-   ============================================================================
- */
-
-/*
- * Map from service/endpoint to Copy Engine.
- * This table is derived from the CE_PCI TABLE, above.
- * It is passed to the Target at startup for use by firmware.
- */
-static struct service_to_pipe target_service_to_ce_map_wlan[] = {
-	{
-		WMI_DATA_VO_SVC,
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		3,
-	},
-	{
-		WMI_DATA_VO_SVC,
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		2,
-	},
-	{
-		WMI_DATA_BK_SVC,
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		3,
-	},
-	{
-		WMI_DATA_BK_SVC,
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		2,
-	},
-	{
-		WMI_DATA_BE_SVC,
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		3,
-	},
-	{
-		WMI_DATA_BE_SVC,
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		2,
-	},
-	{
-		WMI_DATA_VI_SVC,
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		3,
-	},
-	{
-		WMI_DATA_VI_SVC,
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		2,
-	},
-	{
-		WMI_CONTROL_SVC,
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		3,
-	},
-	{
-		WMI_CONTROL_SVC,
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		2,
-	},
-	{
-		HTC_CTRL_RSVD_SVC,
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		0,              /* could be moved to 3 (share with WMI) */
-	},
-	{
-		HTC_CTRL_RSVD_SVC,
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		2,
-	},
-	{
-		HTC_RAW_STREAMS_SVC, /* not currently used */
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		0,
-	},
-	{
-		HTC_RAW_STREAMS_SVC, /* not currently used */
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		2,
-	},
-	{
-		HTT_DATA_MSG_SVC,
-		PIPEDIR_OUT,    /* out = UL = host -> target */
-		4,
-	},
-	{
-		HTT_DATA_MSG_SVC,
-		PIPEDIR_IN,     /* in = DL = target -> host */
-		1,
-	},
-	{
-		WDI_IPA_TX_SVC,
-		PIPEDIR_OUT,    /* in = DL = target -> host */
-		5,
-	},
-	/* (Additions here) */
-
-	{                       /* Must be last */
-		0,
-		0,
-		0,
-	},
-};
-
-static struct service_to_pipe *target_service_to_ce_map =
-	target_service_to_ce_map_wlan;
-static int target_service_to_ce_map_sz = sizeof(target_service_to_ce_map_wlan);
-
-static struct shadow_reg_cfg *target_shadow_reg_cfg = target_shadow_reg_cfg_map;
-static int shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map);
-
-static struct service_to_pipe target_service_to_ce_map_wlan_epping[] = {
-	{WMI_DATA_VO_SVC, PIPEDIR_OUT, 3,},     /* out = UL = host -> target */
-	{WMI_DATA_VO_SVC, PIPEDIR_IN, 2,},      /* in = DL = target -> host */
-	{WMI_DATA_BK_SVC, PIPEDIR_OUT, 4,},     /* out = UL = host -> target */
-	{WMI_DATA_BK_SVC, PIPEDIR_IN, 1,},      /* in = DL = target -> host */
-	{WMI_DATA_BE_SVC, PIPEDIR_OUT, 3,},     /* out = UL = host -> target */
-	{WMI_DATA_BE_SVC, PIPEDIR_IN, 2,},      /* in = DL = target -> host */
-	{WMI_DATA_VI_SVC, PIPEDIR_OUT, 3,},     /* out = UL = host -> target */
-	{WMI_DATA_VI_SVC, PIPEDIR_IN, 2,},      /* in = DL = target -> host */
-	{WMI_CONTROL_SVC, PIPEDIR_OUT, 3,},     /* out = UL = host -> target */
-	{WMI_CONTROL_SVC, PIPEDIR_IN, 2,},      /* in = DL = target -> host */
-	{HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0,},   /* out = UL = host -> target */
-	{HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2,},    /* in = DL = target -> host */
-	{HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */
-	{HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2,},  /* in = DL = target -> host */
-	{HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4,},    /* out = UL = host -> target */
-	{HTT_DATA_MSG_SVC, PIPEDIR_IN, 1,},     /* in = DL = target -> host */
-	{0, 0, 0,},             /* Must be last */
-};
-
-#ifdef HIF_PCI
-/*
- * Send an interrupt to the device to wake up the Target CPU
- * so it has an opportunity to notice any changed state.
- */
-void hif_wake_target_cpu(struct ol_softc *scn)
-{
-	CDF_STATUS rv;
-	uint32_t core_ctrl;
-
-	rv = hif_diag_read_access(scn,
-				  SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS,
-				  &core_ctrl);
-	CDF_ASSERT(rv == CDF_STATUS_SUCCESS);
-	/* A_INUM_FIRMWARE interrupt to Target CPU */
-	core_ctrl |= CORE_CTRL_CPU_INTR_MASK;
-
-	rv = hif_diag_write_access(scn,
-				   SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS,
-				   core_ctrl);
-	CDF_ASSERT(rv == CDF_STATUS_SUCCESS);
-}
-#endif
-
-static void hif_sleep_entry(void *arg)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)arg;
-	struct ol_softc *scn = hif_state->scn;
-	uint32_t idle_ms;
-	if (scn->recovery)
-		return;
-
-	if (cds_is_driver_unloading())
-		return;
-
-	cdf_spin_lock_irqsave(&hif_state->keep_awake_lock);
-	if (hif_state->verified_awake == false) {
-		idle_ms = cdf_system_ticks_to_msecs(cdf_system_ticks()
-						    - hif_state->sleep_ticks);
-		if (idle_ms >= HIF_MIN_SLEEP_INACTIVITY_TIME_MS) {
-			if (!cdf_atomic_read(&scn->link_suspended)) {
-				soc_wake_reset(scn);
-				hif_state->fake_sleep = false;
-			}
-		} else {
-			cdf_softirq_timer_cancel(&hif_state->sleep_timer);
-			cdf_softirq_timer_start(&hif_state->sleep_timer,
-				    HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS);
-		}
-	} else {
-		cdf_softirq_timer_cancel(&hif_state->sleep_timer);
-		cdf_softirq_timer_start(&hif_state->sleep_timer,
-					HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS);
-	}
-	cdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock);
-}
-#define HIF_HIA_MAX_POLL_LOOP    1000000
-#define HIF_HIA_POLLING_DELAY_MS 10
-
-#ifndef HIF_PCI
-int hif_set_hia(struct ol_softc *scn)
-{
-	return 0;
-}
-#else
-int hif_set_hia(struct ol_softc *scn)
-{
-	CDF_STATUS rv;
-	uint32_t interconnect_targ_addr = 0;
-	uint32_t pcie_state_targ_addr = 0;
-	uint32_t pipe_cfg_targ_addr = 0;
-	uint32_t svc_to_pipe_map = 0;
-	uint32_t pcie_config_flags = 0;
-	uint32_t flag2_value = 0;
-	uint32_t flag2_targ_addr = 0;
-#ifdef QCA_WIFI_3_0
-	uint32_t host_interest_area = 0;
-	uint8_t i;
-#else
-	uint32_t ealloc_value = 0;
-	uint32_t ealloc_targ_addr = 0;
-	uint8_t banks_switched = 1;
-	uint32_t chip_id;
-#endif
-	uint32_t pipe_cfg_addr;
-
-	HIF_TRACE("%s: E", __func__);
-
-	if (ADRASTEA_BU)
-		return CDF_STATUS_SUCCESS;
-
-#ifdef QCA_WIFI_3_0
-	i = 0;
-	while (i < HIF_HIA_MAX_POLL_LOOP) {
-		host_interest_area = hif_read32_mb(scn->mem +
-						A_SOC_CORE_SCRATCH_0_ADDRESS);
-		if ((host_interest_area & 0x01) == 0) {
-			cdf_mdelay(HIF_HIA_POLLING_DELAY_MS);
-			host_interest_area = 0;
-			i++;
-			if (i > HIF_HIA_MAX_POLL_LOOP && (i % 1000 == 0)) {
-				HIF_ERROR("%s: poll timeout(%d)", __func__, i);
-			}
-		} else {
-			host_interest_area &= (~0x01);
-			hif_write32_mb(scn->mem + 0x113014, 0);
-			break;
-		}
-	}
-
-	if (i >= HIF_HIA_MAX_POLL_LOOP) {
-		HIF_ERROR("%s: hia polling timeout", __func__);
-		return -EIO;
-	}
-
-	if (host_interest_area == 0) {
-		HIF_ERROR("%s: host_interest_area = 0", __func__);
-		return -EIO;
-	}
-
-	interconnect_targ_addr = host_interest_area +
-			offsetof(struct host_interest_area_t,
-			hi_interconnect_state);
-
-	flag2_targ_addr = host_interest_area +
-			offsetof(struct host_interest_area_t, hi_option_flag2);
-
-#else
-	interconnect_targ_addr = hif_hia_item_address(scn->target_type,
-		offsetof(struct host_interest_s, hi_interconnect_state));
-	ealloc_targ_addr = hif_hia_item_address(scn->target_type,
-		offsetof(struct host_interest_s, hi_early_alloc));
-	flag2_targ_addr = hif_hia_item_address(scn->target_type,
-		offsetof(struct host_interest_s, hi_option_flag2));
-#endif
-	/* Supply Target-side CE configuration */
-	rv = hif_diag_read_access(scn, interconnect_targ_addr,
-			  &pcie_state_targ_addr);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: interconnect_targ_addr = 0x%0x, ret = %d",
-			  __func__, interconnect_targ_addr, rv);
-		goto done;
-	}
-	if (pcie_state_targ_addr == 0) {
-		rv = CDF_STATUS_E_FAILURE;
-		HIF_ERROR("%s: pcie state addr is 0", __func__);
-		goto done;
-	}
-	pipe_cfg_addr = pcie_state_targ_addr +
-			  offsetof(struct pcie_state_s,
-			  pipe_cfg_addr);
-	rv = hif_diag_read_access(scn,
-			  pipe_cfg_addr,
-			  &pipe_cfg_targ_addr);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: pipe_cfg_addr = 0x%0x, ret = %d",
-			__func__, pipe_cfg_addr, rv);
-		goto done;
-	}
-	if (pipe_cfg_targ_addr == 0) {
-		rv = CDF_STATUS_E_FAILURE;
-		HIF_ERROR("%s: pipe cfg addr is 0", __func__);
-		goto done;
-	}
-
-	rv = hif_diag_write_mem(scn, pipe_cfg_targ_addr,
-			(uint8_t *) target_ce_config,
-			target_ce_config_sz);
-
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: write pipe cfg (%d)", __func__, rv);
-		goto done;
-	}
-
-	rv = hif_diag_read_access(scn,
-			  pcie_state_targ_addr +
-			  offsetof(struct pcie_state_s,
-			   svc_to_pipe_map),
-			  &svc_to_pipe_map);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: get svc/pipe map (%d)", __func__, rv);
-		goto done;
-	}
-	if (svc_to_pipe_map == 0) {
-		rv = CDF_STATUS_E_FAILURE;
-		HIF_ERROR("%s: svc_to_pipe map is 0", __func__);
-		goto done;
-	}
-
-	rv = hif_diag_write_mem(scn,
-			svc_to_pipe_map,
-			(uint8_t *) target_service_to_ce_map,
-			target_service_to_ce_map_sz);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: write svc/pipe map (%d)", __func__, rv);
-		goto done;
-	}
-
-	rv = hif_diag_read_access(scn,
-			pcie_state_targ_addr +
-			offsetof(struct pcie_state_s,
-			config_flags),
-			&pcie_config_flags);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: get pcie config_flags (%d)", __func__, rv);
-		goto done;
-	}
-#if (CONFIG_PCIE_ENABLE_L1_CLOCK_GATE)
-	pcie_config_flags |= PCIE_CONFIG_FLAG_ENABLE_L1;
-#else
-	pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
-#endif /* CONFIG_PCIE_ENABLE_L1_CLOCK_GATE */
-	pcie_config_flags |= PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT;
-#if (CONFIG_PCIE_ENABLE_AXI_CLK_GATE)
-	pcie_config_flags |= PCIE_CONFIG_FLAG_AXI_CLK_GATE;
-#endif
-	rv = hif_diag_write_mem(scn,
-			pcie_state_targ_addr +
-			offsetof(struct pcie_state_s,
-			config_flags),
-			(uint8_t *) &pcie_config_flags,
-			sizeof(pcie_config_flags));
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: write pcie config_flags (%d)", __func__, rv);
-		goto done;
-	}
-
-#ifndef QCA_WIFI_3_0
-	/* configure early allocation */
-	ealloc_targ_addr = hif_hia_item_address(scn->target_type,
-							offsetof(
-							struct host_interest_s,
-							hi_early_alloc));
-
-	rv = hif_diag_read_access(scn, ealloc_targ_addr,
-			&ealloc_value);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: get early alloc val (%d)", __func__, rv);
-		goto done;
-	}
-
-	/* 1 bank is switched to IRAM, except ROME 1.0 */
-	ealloc_value |=
-		((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
-		 HI_EARLY_ALLOC_MAGIC_MASK);
-
-	rv = hif_diag_read_access(scn,
-			  CHIP_ID_ADDRESS |
-			  RTC_SOC_BASE_ADDRESS, &chip_id);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: get chip id val (%d)", __func__, rv);
-		goto done;
-	}
-	if (CHIP_ID_VERSION_GET(chip_id) == 0xD) {
-		scn->target_revision =
-			CHIP_ID_REVISION_GET(chip_id);
-		switch (CHIP_ID_REVISION_GET(chip_id)) {
-		case 0x2:       /* ROME 1.3 */
-			/* 2 banks are switched to IRAM */
-			banks_switched = 2;
-			break;
-		case 0x4:       /* ROME 2.1 */
-		case 0x5:       /* ROME 2.2 */
-			banks_switched = 6;
-			break;
-		case 0x8:       /* ROME 3.0 */
-		case 0x9:       /* ROME 3.1 */
-		case 0xA:       /* ROME 3.2 */
-			banks_switched = 9;
-			break;
-		case 0x0:       /* ROME 1.0 */
-		case 0x1:       /* ROME 1.1 */
-		default:
-			/* 3 banks are switched to IRAM */
-			banks_switched = 3;
-			break;
-		}
-	}
-
-	ealloc_value |=
-		((banks_switched << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
-		 & HI_EARLY_ALLOC_IRAM_BANKS_MASK);
-
-	rv = hif_diag_write_access(scn,
-				ealloc_targ_addr,
-				ealloc_value);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: set early alloc val (%d)", __func__, rv);
-		goto done;
-	}
-#endif
-
-	/* Tell Target to proceed with initialization */
-	flag2_targ_addr = hif_hia_item_address(scn->target_type,
-						offsetof(
-						struct host_interest_s,
-						hi_option_flag2));
-
-	rv = hif_diag_read_access(scn, flag2_targ_addr,
-			  &flag2_value);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: get option val (%d)", __func__, rv);
-		goto done;
-	}
-
-	flag2_value |= HI_OPTION_EARLY_CFG_DONE;
-	rv = hif_diag_write_access(scn, flag2_targ_addr,
-			   flag2_value);
-	if (rv != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: set option val (%d)", __func__, rv);
-		goto done;
-	}
-
-	hif_wake_target_cpu(scn);
-
-done:
-
-	return rv;
-}
-#endif
-
-/**
- * hif_wlan_enable(): call the platform driver to enable wlan
- *
- * This function passes the con_mode and CE configuration to
- * platform driver to enable wlan.
- *
- * Return: void
- */
-static int hif_wlan_enable(void)
-{
-	struct icnss_wlan_enable_cfg cfg;
-	enum icnss_driver_mode mode;
-	uint32_t con_mode = cds_get_conparam();
-
-	cfg.num_ce_tgt_cfg = target_ce_config_sz /
-		sizeof(struct CE_pipe_config);
-	cfg.ce_tgt_cfg = (struct ce_tgt_pipe_cfg *)target_ce_config;
-	cfg.num_ce_svc_pipe_cfg = target_service_to_ce_map_sz /
-		sizeof(struct service_to_pipe);
-	cfg.ce_svc_cfg = (struct ce_svc_pipe_cfg *)target_service_to_ce_map;
-	cfg.num_shadow_reg_cfg = shadow_cfg_sz / sizeof(struct shadow_reg_cfg);
-	cfg.shadow_reg_cfg = (struct icnss_shadow_reg_cfg *) target_shadow_reg_cfg;
-
-	if (CDF_GLOBAL_FTM_MODE == con_mode)
-		mode = ICNSS_FTM;
-	else if (WLAN_IS_EPPING_ENABLED(cds_get_conparam()))
-		mode = ICNSS_EPPING;
-	else
-		mode = ICNSS_MISSION;
-
-	return icnss_wlan_enable(&cfg, mode, QWLAN_VERSIONSTR);
-}
-
-/*
- * Called from PCI layer whenever a new PCI device is probed.
- * Initializes per-device HIF state and notifies the main
- * driver that a new HIF device is present.
- */
-int hif_config_ce(hif_handle_t hif_hdl)
-{
-	struct HIF_CE_state *hif_state;
-	struct HIF_CE_pipe_info *pipe_info;
-	int pipe_num;
-#ifdef ADRASTEA_SHADOW_REGISTERS
-	int i;
-#endif
-	CDF_STATUS rv = CDF_STATUS_SUCCESS;
-	int ret;
-	struct ol_softc *scn = hif_hdl;
-	struct icnss_soc_info soc_info;
-
-	/* if epping is enabled we need to use the epping configuration. */
-	if (WLAN_IS_EPPING_ENABLED(cds_get_conparam())) {
-		if (WLAN_IS_EPPING_IRQ(cds_get_conparam()))
-			host_ce_config = host_ce_config_wlan_epping_irq;
-		else
-			host_ce_config = host_ce_config_wlan_epping_poll;
-		target_ce_config = target_ce_config_wlan_epping;
-		target_ce_config_sz = sizeof(target_ce_config_wlan_epping);
-		target_service_to_ce_map =
-		    target_service_to_ce_map_wlan_epping;
-		target_service_to_ce_map_sz =
-			sizeof(target_service_to_ce_map_wlan_epping);
-	}
-
-	ret = hif_wlan_enable();
-
-	if (ret) {
-		HIF_ERROR("%s: hif_wlan_enable error = %d", __func__, ret);
-		return CDF_STATUS_NOT_INITIALIZED;
-	}
-
-	scn->notice_send = true;
-
-	cdf_mem_zero(&soc_info, sizeof(soc_info));
-	ret = icnss_get_soc_info(&soc_info);
-	if (ret < 0) {
-		HIF_ERROR("%s: icnss_get_soc_info error = %d", __func__, ret);
-		return CDF_STATUS_NOT_INITIALIZED;
-	}
-
-	hif_state = (struct HIF_CE_state *)cdf_mem_malloc(sizeof(*hif_state));
-	if (!hif_state) {
-		return -ENOMEM;
-	}
-	cdf_mem_zero(hif_state, sizeof(*hif_state));
-
-	hif_state->scn = scn;
-	scn->hif_hdl = hif_state;
-	scn->mem = soc_info.v_addr;
-	scn->mem_pa = soc_info.p_addr;
-	scn->soc_version = soc_info.version;
-
-	cdf_spinlock_init(&hif_state->keep_awake_lock);
-
-	hif_state->keep_awake_count = 0;
-
-	hif_state->fake_sleep = false;
-	hif_state->sleep_ticks = 0;
-	cdf_softirq_timer_init(NULL, &hif_state->sleep_timer,
-			       hif_sleep_entry, (void *)hif_state,
-			       CDF_TIMER_TYPE_WAKE_APPS);
-	hif_state->sleep_timer_init = true;
-	hif_state->fw_indicator_address = FW_INDICATOR_ADDRESS;
-#ifdef HIF_PCI
-#if CONFIG_ATH_PCIE_MAX_PERF || CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD
-	/* Force AWAKE forever/till the driver is loaded */
-	if (hif_target_sleep_state_adjust(scn, false, true) < 0)
-		return -EACCES;
-#endif
-#endif
-
-	hif_config_rri_on_ddr(scn);
-
-	/* During CE initializtion */
-	scn->ce_count = HOST_CE_COUNT;
-	A_TARGET_ACCESS_LIKELY(scn);
-	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
-		struct CE_attr *attr;
-
-		pipe_info = &hif_state->pipe_info[pipe_num];
-		pipe_info->pipe_num = pipe_num;
-		pipe_info->HIF_CE_state = hif_state;
-		attr = &host_ce_config[pipe_num];
-		pipe_info->ce_hdl = ce_init(scn, pipe_num, attr);
-		CDF_ASSERT(pipe_info->ce_hdl != NULL);
-		if (pipe_info->ce_hdl == NULL) {
-			rv = CDF_STATUS_E_FAILURE;
-			A_TARGET_ACCESS_UNLIKELY(scn);
-			goto err;
-		}
-
-		if (pipe_num == DIAG_CE_ID) {
-			/* Reserve the ultimate CE for
-			 * Diagnostic Window support */
-			hif_state->ce_diag =
-				hif_state->pipe_info[scn->ce_count - 1].ce_hdl;
-			continue;
-		}
-
-		pipe_info->buf_sz = (cdf_size_t) (attr->src_sz_max);
-		cdf_spinlock_init(&pipe_info->recv_bufs_needed_lock);
-		if (attr->dest_nentries > 0) {
-			atomic_set(&pipe_info->recv_bufs_needed,
-				   init_buffer_count(attr->dest_nentries - 1));
-		} else {
-			atomic_set(&pipe_info->recv_bufs_needed, 0);
-		}
-		ce_tasklet_init(hif_state, (1 << pipe_num));
-		ce_register_irq(hif_state, (1 << pipe_num));
-		scn->request_irq_done = true;
-	}
-
-	if (athdiag_procfs_init(scn) != 0) {
-		A_TARGET_ACCESS_UNLIKELY(scn);
-		goto err;
-	}
-	scn->athdiag_procfs_inited = true;
-
-	/*
-	 * Initially, establish CE completion handlers for use with BMI.
-	 * These are overwritten with generic handlers after we exit BMI phase.
-	 */
-	pipe_info = &hif_state->pipe_info[BMI_CE_NUM_TO_TARG];
-#ifdef HIF_PCI
-	ce_send_cb_register(
-	   pipe_info->ce_hdl, hif_bmi_send_done, pipe_info, 0);
-#ifndef BMI_RSP_POLLING
-	pipe_info = &hif_state->pipe_info[BMI_CE_NUM_TO_HOST];
-	ce_recv_cb_register(
-	   pipe_info->ce_hdl, hif_bmi_recv_data, pipe_info, 0);
-#endif
-#endif
-	HIF_INFO_MED("%s: ce_init done", __func__);
-
-	rv = hif_set_hia(scn);
-
-	HIF_INFO_MED("%s: hif_set_hia done", __func__);
-
-	A_TARGET_ACCESS_UNLIKELY(scn);
-
-	if (rv != CDF_STATUS_SUCCESS)
-		goto err;
-	else
-		init_tasklet_workers();
-
-	HIF_TRACE("%s: X, ret = %d\n", __func__, rv);
-
-#ifdef ADRASTEA_SHADOW_REGISTERS
-	HIF_ERROR("Using Shadow Registers instead of CE Registers\n");
-	for (i = 0; i < NUM_SHADOW_REGISTERS; i++) {
-		HIF_ERROR("%s Shadow Register%d is mapped to address %x\n",
-			  __func__, i,
-			  (A_TARGET_READ(scn, (SHADOW_ADDRESS(i))) << 2));
-	}
-#endif
-
-
-	return rv != CDF_STATUS_SUCCESS;
-
-err:
-	/* Failure, so clean up */
-	for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) {
-		pipe_info = &hif_state->pipe_info[pipe_num];
-		if (pipe_info->ce_hdl) {
-			ce_unregister_irq(hif_state, (1 << pipe_num));
-			scn->request_irq_done = false;
-			ce_fini(pipe_info->ce_hdl);
-			pipe_info->ce_hdl = NULL;
-			pipe_info->buf_sz = 0;
-		}
-	}
-	if (hif_state->sleep_timer_init) {
-		cdf_softirq_timer_cancel(&hif_state->sleep_timer);
-		cdf_softirq_timer_free(&hif_state->sleep_timer);
-		hif_state->sleep_timer_init = false;
-	}
-	if (scn->hif_hdl) {
-		scn->hif_hdl = NULL;
-		cdf_mem_free(hif_state);
-	}
-	athdiag_procfs_remove();
-	scn->athdiag_procfs_inited = false;
-	HIF_TRACE("%s: X, ret = %d\n", __func__, rv);
-	return CDF_STATUS_SUCCESS != CDF_STATUS_E_FAILURE;
-}
-
-
-
-
-
-
-#ifdef IPA_OFFLOAD
-/**
- * hif_ipa_get_ce_resource() - get uc resource on hif
- * @scn: bus context
- * @ce_sr_base_paddr: copyengine source ring base physical address
- * @ce_sr_ring_size: copyengine source ring size
- * @ce_reg_paddr: copyengine register physical address
- *
- * IPA micro controller data path offload feature enabled,
- * HIF should release copy engine related resource information to IPA UC
- * IPA UC will access hardware resource with released information
- *
- * Return: None
- */
-void hif_ipa_get_ce_resource(struct ol_softc *scn,
-			     cdf_dma_addr_t *ce_sr_base_paddr,
-			     uint32_t *ce_sr_ring_size,
-			     cdf_dma_addr_t *ce_reg_paddr)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	struct HIF_CE_pipe_info *pipe_info =
-		&(hif_state->pipe_info[HIF_PCI_IPA_UC_ASSIGNED_CE]);
-	struct CE_handle *ce_hdl = pipe_info->ce_hdl;
-
-	ce_ipa_get_resource(ce_hdl, ce_sr_base_paddr, ce_sr_ring_size,
-			    ce_reg_paddr);
-	return;
-}
-#endif /* IPA_OFFLOAD */
-
-
-#ifdef ADRASTEA_SHADOW_REGISTERS
-
-/*
-	Current shadow register config
-
-	-----------------------------------------------------------
-	Shadow Register      |     CE   |    src/dst write index
-	-----------------------------------------------------------
-		0            |     0    |           src
-		1     No Config - Doesn't point to anything
-		2     No Config - Doesn't point to anything
-		3            |     3    |           src
-		4            |     4    |           src
-		5            |     5    |           src
-		6     No Config - Doesn't point to anything
-		7            |     7    |           src
-		8     No Config - Doesn't point to anything
-		9     No Config - Doesn't point to anything
-		10    No Config - Doesn't point to anything
-		11    No Config - Doesn't point to anything
-	-----------------------------------------------------------
-		12    No Config - Doesn't point to anything
-		13           |     1    |           dst
-		14           |     2    |           dst
-		15    No Config - Doesn't point to anything
-		16    No Config - Doesn't point to anything
-		17    No Config - Doesn't point to anything
-		18    No Config - Doesn't point to anything
-		19           |     7    |           dst
-		20           |     8    |           dst
-		21    No Config - Doesn't point to anything
-		22    No Config - Doesn't point to anything
-		23    No Config - Doesn't point to anything
-	-----------------------------------------------------------
-
-
-	ToDo - Move shadow register config to following in the future
-	This helps free up a block of shadow registers towards the end.
-	Can be used for other purposes
-
-	-----------------------------------------------------------
-	Shadow Register      |     CE   |    src/dst write index
-	-----------------------------------------------------------
-		0            |     0    |           src
-		1            |     3    |           src
-		2            |     4    |           src
-		3            |     5    |           src
-		4            |     7    |           src
-	-----------------------------------------------------------
-		5            |     1    |           dst
-		6            |     2    |           dst
-		7            |     7    |           dst
-		8            |     8    |           dst
-	-----------------------------------------------------------
-		9     No Config - Doesn't point to anything
-		12    No Config - Doesn't point to anything
-		13    No Config - Doesn't point to anything
-		14    No Config - Doesn't point to anything
-		15    No Config - Doesn't point to anything
-		16    No Config - Doesn't point to anything
-		17    No Config - Doesn't point to anything
-		18    No Config - Doesn't point to anything
-		19    No Config - Doesn't point to anything
-		20    No Config - Doesn't point to anything
-		21    No Config - Doesn't point to anything
-		22    No Config - Doesn't point to anything
-		23    No Config - Doesn't point to anything
-	-----------------------------------------------------------
-*/
-
-u32 shadow_sr_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr)
-{
-	u32 addr = 0;
-
-	switch (COPY_ENGINE_ID(ctrl_addr)) {
-	case 0:
-		addr = SHADOW_VALUE0;
-		break;
-	case 3:
-		addr = SHADOW_VALUE3;
-		break;
-	case 4:
-		addr = SHADOW_VALUE4;
-		break;
-	case 5:
-		addr = SHADOW_VALUE5;
-		break;
-	case 7:
-		addr = SHADOW_VALUE7;
-		break;
-	default:
-		HIF_ERROR("invalid CE ctrl_addr\n");
-		CDF_ASSERT(0);
-
-	}
-	return addr;
-
-}
-
-u32 shadow_dst_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr)
-{
-	u32 addr = 0;
-
-	switch (COPY_ENGINE_ID(ctrl_addr)) {
-	case 1:
-		addr = SHADOW_VALUE13;
-		break;
-	case 2:
-		addr = SHADOW_VALUE14;
-		break;
-	case 7:
-		addr = SHADOW_VALUE19;
-		break;
-	case 8:
-		addr = SHADOW_VALUE20;
-		break;
-	default:
-		HIF_ERROR("invalid CE ctrl_addr\n");
-		CDF_ASSERT(0);
-	}
-
-	return addr;
-
-}
-#endif
-
-#if defined(FEATURE_LRO)
-/**
- * ce_lro_flush_cb_register() - register the LRO flush
- * callback
- * @scn: HIF context
- * @handler: callback function
- * @data: opaque data pointer to be passed back
- *
- * Store the LRO flush callback provided
- *
- * Return: none
- */
-void ce_lro_flush_cb_register(struct ol_softc *scn,
-	 void (handler)(void *), void *data)
-{
-	uint8_t ul, dl;
-	int ul_polled, dl_polled;
-
-	CDF_ASSERT(scn != NULL);
-
-	if (CDF_STATUS_SUCCESS !=
-		 hif_map_service_to_pipe(scn, HTT_DATA_MSG_SVC,
-			 &ul, &dl, &ul_polled, &dl_polled)) {
-		printk("%s cannot map service to pipe\n", __FUNCTION__);
-		return;
-	} else {
-		struct CE_state *ce_state;
-		ce_state = scn->ce_id_to_state[dl];
-		ce_state->lro_flush_cb = handler;
-		ce_state->lro_data = data;
-	}
-}
-
-/**
- * ce_lro_flush_cb_deregister() - deregister the LRO flush
- * callback
- * @scn: HIF context
- *
- * Remove the LRO flush callback
- *
- * Return: none
- */
-void ce_lro_flush_cb_deregister(struct ol_softc *scn)
-{
-	uint8_t ul, dl;
-	int ul_polled, dl_polled;
-
-	CDF_ASSERT(scn != NULL);
-
-	if (CDF_STATUS_SUCCESS !=
-		 hif_map_service_to_pipe(scn, HTT_DATA_MSG_SVC,
-			 &ul, &dl, &ul_polled, &dl_polled)) {
-		printk("%s cannot map service to pipe\n", __FUNCTION__);
-		return;
-	} else {
-		struct CE_state *ce_state;
-		ce_state = scn->ce_id_to_state[dl];
-		ce_state->lro_flush_cb = NULL;
-		ce_state->lro_data = NULL;
-	}
-}
-#endif
-
-/**
- * hif_map_service_to_pipe() - returns  the ce ids pertaining to
- * this service
- * @scn: ol_softc pointer.
- * @svc_id: Service ID for which the mapping is needed.
- * @ul_pipe: address of the container in which ul pipe is returned.
- * @dl_pipe: address of the container in which dl pipe is returned.
- * @ul_is_polled: address of the container in which a bool
- *			indicating if the UL CE for this service
- *			is polled is returned.
- * @dl_is_polled: address of the container in which a bool
- *			indicating if the DL CE for this service
- *			is polled is returned.
- *
- * Return: Indicates whether this operation was successful.
- */
-
-int hif_map_service_to_pipe(struct ol_softc *scn, uint16_t svc_id,
-			uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
-			int *dl_is_polled)
-{
-	int status = CDF_STATUS_SUCCESS;
-
-	unsigned int i;
-	struct service_to_pipe element;
-
-	struct service_to_pipe *tgt_svc_map_to_use;
-	size_t sz_tgt_svc_map_to_use;
-
-	if (WLAN_IS_EPPING_ENABLED(cds_get_conparam())) {
-		tgt_svc_map_to_use = target_service_to_ce_map_wlan_epping;
-		sz_tgt_svc_map_to_use =
-			sizeof(target_service_to_ce_map_wlan_epping);
-	} else {
-		tgt_svc_map_to_use = target_service_to_ce_map_wlan;
-		sz_tgt_svc_map_to_use = sizeof(target_service_to_ce_map_wlan);
-	}
-
-	*dl_is_polled = 0;  /* polling for received messages not supported */
-
-	for (i = 0; i < (sz_tgt_svc_map_to_use/sizeof(element)); i++) {
-
-		memcpy(&element, &tgt_svc_map_to_use[i], sizeof(element));
-		if (element.service_id == svc_id) {
-
-			if (element.pipedir == PIPEDIR_OUT)
-				*ul_pipe = element.pipenum;
-
-			else if (element.pipedir == PIPEDIR_IN)
-				*dl_pipe = element.pipenum;
-		}
-	}
-
-	*ul_is_polled =
-		(host_ce_config[*ul_pipe].flags & CE_ATTR_DISABLE_INTR) != 0;
-
-	return status;
-}
-
-#ifdef SHADOW_REG_DEBUG
-inline uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr)
-{
-	uint32_t read_from_hw, srri_from_ddr = 0;
-
-	read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_SRRI_ADDRESS);
-
-	srri_from_ddr = SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr));
-
-	if (read_from_hw != srri_from_ddr) {
-		HIF_ERROR("error: read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x\n",
-		       srri_from_ddr, read_from_hw,
-		       CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr));
-		CDF_ASSERT(0);
-	}
-	return srri_from_ddr;
-}
-
-
-inline uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr)
-{
-	uint32_t read_from_hw, drri_from_ddr = 0;
-
-	read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_DRRI_ADDRESS);
-
-	drri_from_ddr = DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr));
-
-	if (read_from_hw != drri_from_ddr) {
-		HIF_ERROR("error: read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x\n",
-		       drri_from_ddr, read_from_hw,
-		       CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr));
-		CDF_ASSERT(0);
-	}
-	return drri_from_ddr;
-}
-
-#endif
-
-#ifdef ADRASTEA_RRI_ON_DDR
-/**
- * hif_get_src_ring_read_index(): Called to get the SRRI
- *
- * @scn: ol_softc pointer
- * @CE_ctrl_addr: base address of the CE whose RRI is to be read
- *
- * This function returns the SRRI to the caller. For CEs that
- * dont have interrupts enabled, we look at the DDR based SRRI
- *
- * Return: SRRI
- */
-inline unsigned int hif_get_src_ring_read_index(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr)
-{
-	struct CE_attr attr;
-
-	attr = host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)];
-	if (attr.flags & CE_ATTR_DISABLE_INTR)
-		return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr);
-	else
-		return A_TARGET_READ(scn,
-				(CE_ctrl_addr) + CURRENT_SRRI_ADDRESS);
-}
-
-/**
- * hif_get_dst_ring_read_index(): Called to get the DRRI
- *
- * @scn: ol_softc pointer
- * @CE_ctrl_addr: base address of the CE whose RRI is to be read
- *
- * This function returns the DRRI to the caller. For CEs that
- * dont have interrupts enabled, we look at the DDR based DRRI
- *
- * Return: DRRI
- */
-inline unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr)
-{
-	struct CE_attr attr;
-
-	attr = host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)];
-
-	if (attr.flags & CE_ATTR_DISABLE_INTR)
-		return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr);
-	else
-		return A_TARGET_READ(scn,
-				(CE_ctrl_addr) + CURRENT_DRRI_ADDRESS);
-}
-
-/**
- * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism
- *
- * @scn: ol_softc pointer
- *
- * This function allocates non cached memory on ddr and sends
- * the physical address of this memory to the CE hardware. The
- * hardware updates the RRI on this particular location.
- *
- * Return: None
- */
-static inline void hif_config_rri_on_ddr(struct ol_softc *scn)
-{
-	unsigned int i;
-	cdf_dma_addr_t paddr_rri_on_ddr;
-	uint32_t high_paddr, low_paddr;
-	scn->vaddr_rri_on_ddr =
-		(uint32_t *)cdf_os_mem_alloc_consistent(scn->cdf_dev,
-		(CE_COUNT*sizeof(uint32_t)), &paddr_rri_on_ddr, 0);
-
-	low_paddr  = BITS0_TO_31(paddr_rri_on_ddr);
-	high_paddr = BITS32_TO_35(paddr_rri_on_ddr);
-
-	HIF_ERROR("%s using srri and drri from DDR\n", __func__);
-
-	WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, low_paddr);
-	WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, high_paddr);
-
-	for (i = 0; i < CE_COUNT; i++)
-		CE_IDX_UPD_EN_SET(scn, CE_BASE_ADDRESS(i));
-
-	cdf_mem_zero(scn->vaddr_rri_on_ddr, CE_COUNT*sizeof(uint32_t));
-
-	return;
-}
-#else
-
-/**
- * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism
- *
- * @scn: ol_softc pointer
- *
- * This is a dummy implementation for platforms that don't
- * support this functionality.
- *
- * Return: None
- */
-static inline void hif_config_rri_on_ddr(struct ol_softc *scn)
-{
-	return;
-}
-#endif
-
-/**
- * hif_dump_ce_registers() - dump ce registers
- * @scn: ol_softc pointer.
- *
- * Output the copy engine registers
- *
- * Return: 0 for success or error code
- */
-int hif_dump_ce_registers(struct ol_softc *scn)
-{
-	uint32_t ce_reg_address = CE0_BASE_ADDRESS;
-	uint32_t ce_reg_values[8][CE_USEFUL_SIZE >> 2];
-	uint32_t ce_reg_word_size = CE_USEFUL_SIZE >> 2;
-	uint16_t i, j;
-
-	for (i = 0; i < 8; i++, ce_reg_address += CE_OFFSET) {
-		if (hif_diag_read_mem(scn, ce_reg_address,
-			(uint8_t *) &ce_reg_values[i][0], ce_reg_word_size *
-			sizeof(uint32_t)) != CDF_STATUS_SUCCESS) {
-				HIF_ERROR("Dumping CE register failed!");
-				return -EACCES;
-		}
-	}
-
-	for (i = 0; i < 8; i++) {
-		HIF_ERROR("CE%d Registers:", i);
-		for (j = 0; j < ce_reg_word_size; j++) {
-			HIF_ERROR("0x%08x ", ce_reg_values[i][j]);
-			if (!((j + 1) % 5) || (ce_reg_word_size - 1) == j)
-				HIF_ERROR(" ");
-		}
-	}
-
-	return 0;
-}

core/hif/src/ce/ce_main.h

@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __CE_H__
-#define __CE_H__
-
-#include "cdf_atomic.h"
-#include "cdf_lock.h"
-#include "hif.h"
-
-#define CE_HTT_T2H_MSG 1
-#define CE_HTT_H2T_MSG 4
-
-#define CE_OFFSET               0x00000400
-#define CE_USEFUL_SIZE          0x00000058
-
-/**
- * enum ce_id_type
- *
- * @ce_id_type: Copy engine ID
- */
-enum ce_id_type {
-	CE_ID_0,
-	CE_ID_1,
-	CE_ID_2,
-	CE_ID_3,
-	CE_ID_4,
-	CE_ID_5,
-	CE_ID_6,
-	CE_ID_7,
-	CE_ID_8,
-	CE_ID_9,
-	CE_ID_10,
-	CE_ID_11,
-	CE_ID_MAX
-};
-
-enum ol_ath_hif_pkt_ecodes {
-	HIF_PIPE_NO_RESOURCE = 0
-};
-
-struct HIF_CE_state;
-
-/* Per-pipe state. */
-struct HIF_CE_pipe_info {
-	/* Handle of underlying Copy Engine */
-	struct CE_handle *ce_hdl;
-
-	/* Our pipe number; facilitiates use of pipe_info ptrs. */
-	uint8_t pipe_num;
-
-	/* Convenience back pointer to HIF_CE_state. */
-	struct HIF_CE_state *HIF_CE_state;
-
-	/* Instantaneous number of receive buffers that should be posted */
-	atomic_t recv_bufs_needed;
-	cdf_size_t buf_sz;
-	cdf_spinlock_t recv_bufs_needed_lock;
-
-	cdf_spinlock_t completion_freeq_lock;
-	/* Limit the number of outstanding send requests. */
-	int num_sends_allowed;
-
-	/* adding three counts for debugging ring buffer errors */
-	uint32_t nbuf_alloc_err_count;
-	uint32_t nbuf_dma_err_count;
-	uint32_t nbuf_ce_enqueue_err_count;
-};
-
-/**
- * struct ce_tasklet_entry
- *
- * @intr_tq: intr_tq
- * @ce_id: ce_id
- * @inited: inited
- * @hif_ce_state: hif_ce_state
- * @from_irq: from_irq
- */
-struct ce_tasklet_entry {
-	struct tasklet_struct intr_tq;
-	enum ce_id_type ce_id;
-	bool inited;
-	void *hif_ce_state;
-};
-
-struct HIF_CE_state {
-	struct ol_softc *scn;
-	bool started;
-	struct ce_tasklet_entry tasklets[CE_COUNT_MAX];
-	cdf_spinlock_t keep_awake_lock;
-	unsigned int keep_awake_count;
-	bool verified_awake;
-	bool fake_sleep;
-	cdf_softirq_timer_t sleep_timer;
-	bool sleep_timer_init;
-	unsigned long sleep_ticks;
-
-	/* Per-pipe state. */
-	struct HIF_CE_pipe_info pipe_info[CE_COUNT_MAX];
-	/* to be activated after BMI_DONE */
-	struct hif_msg_callbacks msg_callbacks_pending;
-	/* current msg callbacks in use */
-	struct hif_msg_callbacks msg_callbacks_current;
-
-	/* Target address used to signal a pending firmware event */
-	uint32_t fw_indicator_address;
-
-	/* Copy Engine used for Diagnostic Accesses */
-	struct CE_handle *ce_diag;
-};
-int hif_dump_ce_registers(struct ol_softc *scn);
-#endif /* __CE_H__ */

core/hif/src/ce/ce_reg.h

@@ -1,544 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __CE_REG_H__
-#define __CE_REG_H__
-
-#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
-		- CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
-
-#define DST_WR_INDEX_ADDRESS    (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
-#define SRC_WATERMARK_ADDRESS   (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
-#define SRC_WATERMARK_LOW_MASK  (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
-#define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK)
-#define DST_WATERMARK_LOW_MASK  (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK)
-#define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK)
-#define CURRENT_SRRI_ADDRESS    (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
-#define CURRENT_DRRI_ADDRESS    (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
-
-#define SHADOW_VALUE0           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
-#define SHADOW_VALUE1           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
-#define SHADOW_VALUE2           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
-#define SHADOW_VALUE3           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
-#define SHADOW_VALUE4           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
-#define SHADOW_VALUE5           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
-#define SHADOW_VALUE6           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
-#define SHADOW_VALUE7           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
-#define SHADOW_VALUE8           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
-#define SHADOW_VALUE9           (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
-#define SHADOW_VALUE10          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
-#define SHADOW_VALUE11          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
-#define SHADOW_VALUE12          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
-#define SHADOW_VALUE13          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
-#define SHADOW_VALUE14          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
-#define SHADOW_VALUE15          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
-#define SHADOW_VALUE16          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
-#define SHADOW_VALUE17          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
-#define SHADOW_VALUE18          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
-#define SHADOW_VALUE19          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
-#define SHADOW_VALUE20          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
-#define SHADOW_VALUE21          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
-#define SHADOW_VALUE22          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
-#define SHADOW_VALUE23          (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
-#define SHADOW_ADDRESS0         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
-#define SHADOW_ADDRESS1         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
-#define SHADOW_ADDRESS2         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
-#define SHADOW_ADDRESS3         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
-#define SHADOW_ADDRESS4         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
-#define SHADOW_ADDRESS5         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
-#define SHADOW_ADDRESS6         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
-#define SHADOW_ADDRESS7         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
-#define SHADOW_ADDRESS8         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
-#define SHADOW_ADDRESS9         (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
-#define SHADOW_ADDRESS10        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
-#define SHADOW_ADDRESS11        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
-#define SHADOW_ADDRESS12        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
-#define SHADOW_ADDRESS13        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
-#define SHADOW_ADDRESS14        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
-#define SHADOW_ADDRESS15        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
-#define SHADOW_ADDRESS16        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
-#define SHADOW_ADDRESS17        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
-#define SHADOW_ADDRESS18        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
-#define SHADOW_ADDRESS19        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
-#define SHADOW_ADDRESS20        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
-#define SHADOW_ADDRESS21        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
-#define SHADOW_ADDRESS22        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
-#define SHADOW_ADDRESS23        (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
-
-#define SHADOW_ADDRESS(i) (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0))
-
-#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
-	(scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
-#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
-	(scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
-#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
-	(scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
-#define HOST_IS_DST_RING_LOW_WATERMARK_MASK \
-	(scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
-#define MISC_IS_ADDRESS         (scn->target_ce_def->d_MISC_IS_ADDRESS)
-#define HOST_IS_COPY_COMPLETE_MASK \
-	(scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK)
-#define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
-#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \
-	(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
-#define CE_DDR_ADDRESS_FOR_RRI_LOW \
-	(scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_LOW)
-#define CE_DDR_ADDRESS_FOR_RRI_HIGH \
-	(scn->target_ce_def->d_CE_DDR_ADDRESS_FOR_RRI_HIGH)
-#define HOST_IE_COPY_COMPLETE_MASK \
-	(scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
-#define SR_BA_ADDRESS             (scn->target_ce_def->d_SR_BA_ADDRESS)
-#define SR_BA_ADDRESS_HIGH        (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH)
-#define SR_SIZE_ADDRESS           (scn->target_ce_def->d_SR_SIZE_ADDRESS)
-#define CE_CTRL1_ADDRESS          (scn->target_ce_def->d_CE_CTRL1_ADDRESS)
-#define CE_CTRL1_DMAX_LENGTH_MASK \
-	(scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK)
-#define DR_BA_ADDRESS             (scn->target_ce_def->d_DR_BA_ADDRESS)
-#define DR_BA_ADDRESS_HIGH        (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH)
-#define DR_SIZE_ADDRESS           (scn->target_ce_def->d_DR_SIZE_ADDRESS)
-#define CE_CMD_REGISTER           (scn->target_ce_def->d_CE_CMD_REGISTER)
-#define CE_MSI_ADDRESS            (scn->target_ce_def->d_CE_MSI_ADDRESS)
-#define CE_MSI_ADDRESS_HIGH       (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH)
-#define CE_MSI_DATA               (scn->target_ce_def->d_CE_MSI_DATA)
-#define CE_MSI_ENABLE_BIT         (scn->target_ce_def->d_CE_MSI_ENABLE_BIT)
-#define MISC_IE_ADDRESS           (scn->target_ce_def->d_MISC_IE_ADDRESS)
-#define MISC_IS_AXI_ERR_MASK      (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK)
-#define MISC_IS_DST_ADDR_ERR_MASK \
-	(scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK)
-#define MISC_IS_SRC_LEN_ERR_MASK \
-	(scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK)
-#define MISC_IS_DST_MAX_LEN_VIO_MASK \
-	(scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
-#define MISC_IS_DST_RING_OVERFLOW_MASK \
-	(scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK)
-#define MISC_IS_SRC_RING_OVERFLOW_MASK \
-	(scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
-#define SRC_WATERMARK_LOW_LSB     (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB)
-#define SRC_WATERMARK_HIGH_LSB    (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB)
-#define DST_WATERMARK_LOW_LSB     (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB)
-#define DST_WATERMARK_HIGH_LSB    (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB)
-#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
-	(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
-#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB  \
-	(scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
-#define CE_CTRL1_DMAX_LENGTH_LSB  (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
-#define CE_CTRL1_IDX_UPD_EN  (scn->target_ce_def->d_CE_CTRL1_IDX_UPD_EN_MASK)
-#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
-	(scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
-#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
-	(scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
-#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
-	(scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
-#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
-	(scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
-#define WLAN_DEBUG_INPUT_SEL_OFFSET \
-	(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
-#define WLAN_DEBUG_INPUT_SEL_SRC_MSB \
-	(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
-#define WLAN_DEBUG_INPUT_SEL_SRC_LSB \
-	(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
-#define WLAN_DEBUG_INPUT_SEL_SRC_MASK \
-	(scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
-#define WLAN_DEBUG_CONTROL_OFFSET  (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
-#define WLAN_DEBUG_CONTROL_ENABLE_MSB \
-	(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
-#define WLAN_DEBUG_CONTROL_ENABLE_LSB \
-	(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
-#define WLAN_DEBUG_CONTROL_ENABLE_MASK \
-	(scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
-#define WLAN_DEBUG_OUT_OFFSET    (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
-#define WLAN_DEBUG_OUT_DATA_MSB  (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
-#define WLAN_DEBUG_OUT_DATA_LSB  (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
-#define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
-#define AMBA_DEBUG_BUS_OFFSET    (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
-#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \
-	(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
-#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \
-	(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
-#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \
-	(scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
-#define AMBA_DEBUG_BUS_SEL_MSB    (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
-#define AMBA_DEBUG_BUS_SEL_LSB    (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
-#define AMBA_DEBUG_BUS_SEL_MASK   (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
-#define CE_WRAPPER_DEBUG_OFFSET   (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
-#define CE_WRAPPER_DEBUG_SEL_MSB  (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
-#define CE_WRAPPER_DEBUG_SEL_LSB  (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
-#define CE_WRAPPER_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
-#define CE_DEBUG_OFFSET           (scn->target_ce_def->d_CE_DEBUG_OFFSET)
-#define CE_DEBUG_SEL_MSB          (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
-#define CE_DEBUG_SEL_LSB          (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
-#define CE_DEBUG_SEL_MASK         (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
-#define HOST_IE_ADDRESS           (scn->target_ce_def->d_HOST_IE_ADDRESS)
-#define HOST_IS_ADDRESS           (scn->target_ce_def->d_HOST_IS_ADDRESS)
-
-#define SRC_WATERMARK_LOW_SET(x) \
-	(((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
-#define SRC_WATERMARK_HIGH_SET(x) \
-	(((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
-#define DST_WATERMARK_LOW_SET(x) \
-	(((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
-#define DST_WATERMARK_HIGH_SET(x) \
-	(((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
-#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
-	(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
-		CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
-#define CE_CTRL1_DMAX_LENGTH_SET(x) \
-	(((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
-#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
-	(((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
-		CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
-#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
-	(((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
-		CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
-#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \
-	(((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \
-		WLAN_DEBUG_INPUT_SEL_SRC_LSB)
-#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \
-	(((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \
-		WLAN_DEBUG_INPUT_SEL_SRC_MASK)
-#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \
-	(((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \
-		WLAN_DEBUG_CONTROL_ENABLE_LSB)
-#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \
-	(((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \
-		WLAN_DEBUG_CONTROL_ENABLE_MASK)
-#define WLAN_DEBUG_OUT_DATA_GET(x) \
-	(((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
-#define WLAN_DEBUG_OUT_DATA_SET(x) \
-	(((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
-#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \
-	(((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \
-		AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
-#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \
-	(((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \
-		AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
-#define AMBA_DEBUG_BUS_SEL_GET(x) \
-	(((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB)
-#define AMBA_DEBUG_BUS_SEL_SET(x) \
-	(((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK)
-#define CE_WRAPPER_DEBUG_SEL_GET(x) \
-	(((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB)
-#define CE_WRAPPER_DEBUG_SEL_SET(x) \
-	(((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK)
-#define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
-#define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
-
-uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr);
-uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr);
-
-#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(paddr_rri_on_ddr)\
-				     & (uint64_t)(0xFFFFFFFF)))
-#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(paddr_rri_on_ddr)\
-				     & (uint64_t)(0xF00000000))>>32))
-
-#define VADDR_FOR_CE(scn, CE_ctrl_addr)\
-	((uint32_t *)((uint64_t)(scn->vaddr_rri_on_ddr) + \
-	COPY_ENGINE_ID(CE_ctrl_addr)*sizeof(uint32_t)))
-
-#define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
-#define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF)
-
-#ifdef ADRASTEA_RRI_ON_DDR
-#ifdef SHADOW_REG_DEBUG
-#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
-	DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)
-#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
-	DEBUG_CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)
-#else
-#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
-	SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
-#define CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
-	DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
-#endif
-
-unsigned int hif_get_src_ring_read_index(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr);
-unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
-		uint32_t CE_ctrl_addr);
-
-#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
-	hif_get_src_ring_read_index(scn, CE_ctrl_addr)
-#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
-	hif_get_dst_ring_read_index(scn, CE_ctrl_addr)
-#else
-#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
-#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
-	A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
-
-/**
- * if RRI on DDR is not enabled, get idx from ddr defaults to
- * using the register value & force wake must be used for
- * non interrupt processing.
- */
-#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
-	A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
-
-#endif
-
-#define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr))
-
-#define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr))
-
-#define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH)
-
-#define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n))
-
-#define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
-	   (A_TARGET_READ(scn, (CE_ctrl_addr) + \
-	   CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \
-	   CE_CTRL1_DMAX_LENGTH_SET(n))
-
-#define CE_IDX_UPD_EN_SET(scn, CE_ctrl_addr)  \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
-	(A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
-	| CE_CTRL1_IDX_UPD_EN))
-
-#define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER)
-
-#define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n)
-
-#define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr))
-
-#define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr))
-
-#define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data))
-
-#define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val)
-
-#define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS)
-
-#define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
-		       (A_TARGET_READ((targid), \
-		       (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
-		       & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \
-		       CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n))
-
-#define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \
-		       (A_TARGET_READ((targid), \
-		       (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
-		       & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \
-		       CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n))
-
-
-#define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr))
-
-#define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr))
-
-#define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH)
-
-#define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n))
-
-#define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
-		       (A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
-		       & ~SRC_WATERMARK_HIGH_MASK) | \
-		       SRC_WATERMARK_HIGH_SET(n))
-
-#define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
-		       (A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
-		       & ~SRC_WATERMARK_LOW_MASK) | \
-		       SRC_WATERMARK_LOW_SET(n))
-
-#define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
-		       (A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
-		       & ~DST_WATERMARK_HIGH_MASK) | \
-		       DST_WATERMARK_HIGH_SET(n))
-
-#define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
-		       (A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
-		       & ~DST_WATERMARK_LOW_MASK) | \
-		       DST_WATERMARK_LOW_SET(n))
-
-#define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
-		       A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
-		       HOST_IE_COPY_COMPLETE_MASK)
-
-#define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
-		       A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + HOST_IE_ADDRESS) \
-		       & ~HOST_IE_COPY_COMPLETE_MASK)
-
-#define CE_BASE_ADDRESS(CE_id) \
-	CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \
-	CE0_BASE_ADDRESS)*(CE_id))
-
-#define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
-		       A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
-		       CE_WATERMARK_MASK)
-
-#define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr)	\
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
-		       A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + HOST_IE_ADDRESS) \
-		       & ~CE_WATERMARK_MASK)
-
-#define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \
-		       A_TARGET_READ(scn, \
-		       (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK)
-
-#define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS)
-
-#define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS)
-
-#define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask))
-
-#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK  | \
-			   HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
-			   HOST_IS_DST_RING_LOW_WATERMARK_MASK  | \
-			   HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
-
-#define CE_ERROR_MASK     (MISC_IS_AXI_ERR_MASK           | \
-			   MISC_IS_DST_ADDR_ERR_MASK      | \
-			   MISC_IS_SRC_LEN_ERR_MASK       | \
-			   MISC_IS_DST_MAX_LEN_VIO_MASK   | \
-			   MISC_IS_DST_RING_OVERFLOW_MASK | \
-			   MISC_IS_SRC_RING_OVERFLOW_MASK)
-
-#define CE_SRC_RING_TO_DESC(baddr, idx) \
-	(&(((struct CE_src_desc *)baddr)[idx]))
-#define CE_DEST_RING_TO_DESC(baddr, idx) \
-	(&(((struct CE_dest_desc *)baddr)[idx]))
-
-/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
-#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
-	(((int)(toidx)-(int)(fromidx)) & (nentries_mask))
-
-#define CE_RING_IDX_INCR(nentries_mask, idx) \
-	(((idx) + 1) & (nentries_mask))
-
-#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
-	(((idx) + (num)) & (nentries_mask))
-
-#define CE_INTERRUPT_SUMMARY(scn) \
-	CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
-		A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \
-		CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
-
-#define READ_CE_DDR_ADDRESS_FOR_RRI_LOW(scn) \
-	(A_TARGET_READ(scn, \
-		       CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW))
-
-#define READ_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn) \
-	(A_TARGET_READ(scn, \
-		       CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH))
-
-#define WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, val) \
-	(A_TARGET_WRITE(scn, \
-			CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_LOW, \
-			val))
-
-#define WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, val) \
-	(A_TARGET_WRITE(scn, \
-			CE_WRAPPER_BASE_ADDRESS + CE_DDR_ADDRESS_FOR_RRI_HIGH, \
-			val))
-
-/*Macro to increment CE packet errors*/
-#define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \
-	do { if (_ce_ecode == CE_RING_DELTA_FAIL) \
-			(_scn->pkt_stats.ce_ring_delta_fail_count) \
-			+= 1; } while (0)
-
-/* Given a Copy Engine's ID, determine the interrupt number for that
- * copy engine's interrupts.
- */
-#define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id))
-#define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE)
-#define CE0_BASE_ADDRESS         (scn->target_ce_def->d_CE0_BASE_ADDRESS)
-#define CE1_BASE_ADDRESS         (scn->target_ce_def->d_CE1_BASE_ADDRESS)
-
-#ifdef ADRASTEA_SHADOW_REGISTERS
-
-#define NUM_SHADOW_REGISTERS 24
-
-u32 shadow_sr_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
-u32 shadow_dst_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
-#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n)
-
-#define CE_SRC_RING_WRITE_IDX_GET(scn, CE_ctrl_addr)  \
-	A_TARGET_READ(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr))
-
-#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n)
-
-#define CE_DEST_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr))
-
-#else
-
-#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
-
-#define CE_SRC_RING_WRITE_IDX_GET(scn, CE_ctrl_addr)	\
-	A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS)
-
-#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
-	A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
-
-#define CE_DEST_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
-	A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS)
-
-#endif
-
-#endif /* __CE_REG_H__ */

core/hif/src/ce/ce_service.c

@@ -1,1840 +0,0 @@
-/*
- * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include <osdep.h>
-#include "a_types.h"
-#include <athdefs.h>
-#include "osapi_linux.h"
-#include "hif.h"
-#include "hif_io32.h"
-#include "ce_api.h"
-#include "ce_main.h"
-#include "ce_internal.h"
-#include "ce_reg.h"
-#include "cdf_lock.h"
-#include "regtable.h"
-#include "epping_main.h"
-#include "hif_main.h"
-#include "hif_debug.h"
-#include "cds_concurrency.h"
-
-#ifdef IPA_OFFLOAD
-#ifdef QCA_WIFI_3_0
-#define CE_IPA_RING_INIT(ce_desc)                       \
-	do {                                            \
-		ce_desc->gather = 0;                    \
-		ce_desc->enable_11h = 0;                \
-		ce_desc->meta_data_low = 0;             \
-		ce_desc->packet_result_offset = 64;     \
-		ce_desc->toeplitz_hash_enable = 0;      \
-		ce_desc->addr_y_search_disable = 0;     \
-		ce_desc->addr_x_search_disable = 0;     \
-		ce_desc->misc_int_disable = 0;          \
-		ce_desc->target_int_disable = 0;        \
-		ce_desc->host_int_disable = 0;          \
-		ce_desc->dest_byte_swap = 0;            \
-		ce_desc->byte_swap = 0;                 \
-		ce_desc->type = 2;                      \
-		ce_desc->tx_classify = 1;               \
-		ce_desc->buffer_addr_hi = 0;            \
-		ce_desc->meta_data = 0;                 \
-		ce_desc->nbytes = 128;                  \
-	} while (0)
-#else
-#define CE_IPA_RING_INIT(ce_desc)                       \
-	do {                                            \
-		ce_desc->byte_swap = 0;                 \
-		ce_desc->nbytes = 60;                   \
-		ce_desc->gather = 0;                    \
-	} while (0)
-#endif /* QCA_WIFI_3_0 */
-#endif /* IPA_OFFLOAD */
-
-static int war1_allow_sleep;
-/* io32 write workaround */
-static int hif_ce_war1;
-
-#ifdef CONFIG_SLUB_DEBUG_ON
-
-/**
- * struct hif_ce_event - structure for detailing a ce event
- * @type: what the event was
- * @time: when it happened
- * @descriptor: descriptor enqueued or dequeued
- * @memory: virtual address that was used
- * @index: location of the descriptor in the ce ring;
- */
-struct hif_ce_desc_event {
-	uint16_t index;
-	enum hif_ce_event_type type;
-	uint64_t time;
-	union ce_desc descriptor;
-	void *memory;
-};
-
-/* max history to record per copy engine */
-#define HIF_CE_HISTORY_MAX 512
-cdf_atomic_t hif_ce_desc_history_index[CE_COUNT_MAX];
-struct hif_ce_desc_event hif_ce_desc_history[CE_COUNT_MAX][HIF_CE_HISTORY_MAX];
-
-
-/**
- * get_next_record_index() - get the next record index
- * @table_index: atomic index variable to increment
- * @array_size: array size of the circular buffer
- *
- * Increment the atomic index and reserve the value.
- * Takes care of buffer wrap.
- * Guaranteed to be thread safe as long as fewer than array_size contexts
- * try to access the array.  If there are more than array_size contexts
- * trying to access the array, full locking of the recording process would
- * be needed to have sane logging.
- */
-static int get_next_record_index(cdf_atomic_t *table_index, int array_size)
-{
-	int record_index = cdf_atomic_inc_return(table_index);
-	if (record_index == array_size)
-		cdf_atomic_sub(array_size, table_index);
-
-	while (record_index >= array_size)
-		record_index -= array_size;
-	return record_index;
-}
-
-/**
- * hif_record_ce_desc_event() - record ce descriptor events
- * @ce_id: which ce is the event occuring on
- * @type: what happened
- * @descriptor: pointer to the descriptor posted/completed
- * @memory: virtual address of buffer related to the descriptor
- * @index: index that the descriptor was/will be at.
- */
-void hif_record_ce_desc_event(int ce_id, enum hif_ce_event_type type,
-		union ce_desc *descriptor, void *memory, int index)
-{
-	int record_index = get_next_record_index(
-			&hif_ce_desc_history_index[ce_id], HIF_CE_HISTORY_MAX);
-
-	struct hif_ce_desc_event *event =
-		&hif_ce_desc_history[ce_id][record_index];
-	event->type = type;
-	event->time = cds_get_monotonic_boottime();
-	if (descriptor != NULL)
-		event->descriptor = *descriptor;
-	else
-		memset(&event->descriptor, 0, sizeof(union ce_desc));
-	event->memory = memory;
-	event->index = index;
-}
-
-/**
- * ce_init_ce_desc_event_log() - initialize the ce event log
- * @ce_id: copy engine id for which we are initializing the log
- * @size: size of array to dedicate
- *
- * Currently the passed size is ignored in favor of a precompiled value.
- */
-void ce_init_ce_desc_event_log(int ce_id, int size)
-{
-	cdf_atomic_init(&hif_ce_desc_history_index[ce_id]);
-}
-#else
-void hif_record_ce_desc_event(
-		int ce_id, enum hif_ce_event_type type,
-		union ce_desc *descriptor, void *memory,
-		int index)
-{
-}
-
-inline void ce_init_ce_desc_event_log(int ce_id, int size)
-{
-}
-#endif
-
-/*
- * Support for Copy Engine hardware, which is mainly used for
- * communication between Host and Target over a PCIe interconnect.
- */
-
-/*
- * A single CopyEngine (CE) comprises two "rings":
- *   a source ring
- *   a destination ring
- *
- * Each ring consists of a number of descriptors which specify
- * an address, length, and meta-data.
- *
- * Typically, one side of the PCIe interconnect (Host or Target)
- * controls one ring and the other side controls the other ring.
- * The source side chooses when to initiate a transfer and it
- * chooses what to send (buffer address, length). The destination
- * side keeps a supply of "anonymous receive buffers" available and
- * it handles incoming data as it arrives (when the destination
- * recieves an interrupt).
- *
- * The sender may send a simple buffer (address/length) or it may
- * send a small list of buffers.  When a small list is sent, hardware
- * "gathers" these and they end up in a single destination buffer
- * with a single interrupt.
- *
- * There are several "contexts" managed by this layer -- more, it
- * may seem -- than should be needed. These are provided mainly for
- * maximum flexibility and especially to facilitate a simpler HIF
- * implementation. There are per-CopyEngine recv, send, and watermark
- * contexts. These are supplied by the caller when a recv, send,
- * or watermark handler is established and they are echoed back to
- * the caller when the respective callbacks are invoked. There is
- * also a per-transfer context supplied by the caller when a buffer
- * (or sendlist) is sent and when a buffer is enqueued for recv.
- * These per-transfer contexts are echoed back to the caller when
- * the buffer is sent/received.
- * Target TX harsh result toeplitz_hash_result
- */
-
-/*
- * Guts of ce_send, used by both ce_send and ce_sendlist_send.
- * The caller takes responsibility for any needed locking.
- */
-int
-ce_completed_send_next_nolock(struct CE_state *CE_state,
-			      void **per_CE_contextp,
-			      void **per_transfer_contextp,
-			      cdf_dma_addr_t *bufferp,
-			      unsigned int *nbytesp,
-			      unsigned int *transfer_idp,
-			      unsigned int *sw_idx, unsigned int *hw_idx,
-			      uint32_t *toeplitz_hash_result);
-
-void war_ce_src_ring_write_idx_set(struct ol_softc *scn,
-				   u32 ctrl_addr, unsigned int write_index)
-{
-	if (hif_ce_war1) {
-		void __iomem *indicator_addr;
-
-		indicator_addr = scn->mem + ctrl_addr + DST_WATERMARK_ADDRESS;
-
-		if (!war1_allow_sleep
-		    && ctrl_addr == CE_BASE_ADDRESS(CDC_WAR_DATA_CE)) {
-			hif_write32_mb(indicator_addr,
-				      (CDC_WAR_MAGIC_STR | write_index));
-		} else {
-			unsigned long irq_flags;
-			local_irq_save(irq_flags);
-			hif_write32_mb(indicator_addr, 1);
-
-			/*
-			 * PCIE write waits for ACK in IPQ8K, there is no
-			 * need to read back value.
-			 */
-			(void)hif_read32_mb(indicator_addr);
-			(void)hif_read32_mb(indicator_addr); /* conservative */
-
-			CE_SRC_RING_WRITE_IDX_SET(scn,
-						  ctrl_addr, write_index);
-
-			hif_write32_mb(indicator_addr, 0);
-			local_irq_restore(irq_flags);
-		}
-	} else
-		CE_SRC_RING_WRITE_IDX_SET(scn, ctrl_addr, write_index);
-}
-
-int
-ce_send_nolock(struct CE_handle *copyeng,
-			   void *per_transfer_context,
-			   cdf_dma_addr_t buffer,
-			   uint32_t nbytes,
-			   uint32_t transfer_id,
-			   uint32_t flags,
-			   uint32_t user_flags)
-{
-	int status;
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	struct CE_ring_state *src_ring = CE_state->src_ring;
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	unsigned int nentries_mask = src_ring->nentries_mask;
-	unsigned int sw_index = src_ring->sw_index;
-	unsigned int write_index = src_ring->write_index;
-	uint64_t dma_addr = buffer;
-	struct ol_softc *scn = CE_state->scn;
-
-	A_TARGET_ACCESS_BEGIN_RET(scn);
-	if (unlikely(CE_RING_DELTA(nentries_mask,
-				write_index, sw_index - 1) <= 0)) {
-		OL_ATH_CE_PKT_ERROR_COUNT_INCR(scn, CE_RING_DELTA_FAIL);
-		status = CDF_STATUS_E_FAILURE;
-		A_TARGET_ACCESS_END_RET(scn);
-		return status;
-	}
-	{
-		enum hif_ce_event_type event_type = HIF_TX_GATHER_DESC_POST;
-		struct CE_src_desc *src_ring_base =
-			(struct CE_src_desc *)src_ring->base_addr_owner_space;
-		struct CE_src_desc *shadow_base =
-			(struct CE_src_desc *)src_ring->shadow_base;
-		struct CE_src_desc *src_desc =
-			CE_SRC_RING_TO_DESC(src_ring_base, write_index);
-		struct CE_src_desc *shadow_src_desc =
-			CE_SRC_RING_TO_DESC(shadow_base, write_index);
-
-		/* Update low 32 bits source descriptor address */
-		shadow_src_desc->buffer_addr =
-			(uint32_t)(dma_addr & 0xFFFFFFFF);
-#ifdef QCA_WIFI_3_0
-		shadow_src_desc->buffer_addr_hi =
-			(uint32_t)((dma_addr >> 32) & 0x1F);
-		user_flags |= shadow_src_desc->buffer_addr_hi;
-		memcpy(&(((uint32_t *)shadow_src_desc)[1]), &user_flags,
-			   sizeof(uint32_t));
-#endif
-		shadow_src_desc->meta_data = transfer_id;
-
-		/*
-		 * Set the swap bit if:
-		 * typical sends on this CE are swapped (host is big-endian)
-		 * and this send doesn't disable the swapping
-		 * (data is not bytestream)
-		 */
-		shadow_src_desc->byte_swap =
-			(((CE_state->attr_flags & CE_ATTR_BYTE_SWAP_DATA)
-			 != 0) & ((flags & CE_SEND_FLAG_SWAP_DISABLE) == 0));
-		shadow_src_desc->gather = ((flags & CE_SEND_FLAG_GATHER) != 0);
-		shadow_src_desc->nbytes = nbytes;
-
-		*src_desc = *shadow_src_desc;
-
-		src_ring->per_transfer_context[write_index] =
-			per_transfer_context;
-
-		/* Update Source Ring Write Index */
-		write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
-
-		/* WORKAROUND */
-		if (!shadow_src_desc->gather) {
-			event_type = HIF_TX_DESC_POST;
-			war_ce_src_ring_write_idx_set(scn, ctrl_addr,
-						      write_index);
-		}
-
-		/* src_ring->write index hasn't been updated event though
-		 * the register has allready been written to.
-		 */
-		hif_record_ce_desc_event(CE_state->id, event_type,
-			(union ce_desc *) shadow_src_desc, per_transfer_context,
-			src_ring->write_index);
-
-		src_ring->write_index = write_index;
-		status = CDF_STATUS_SUCCESS;
-	}
-	A_TARGET_ACCESS_END_RET(scn);
-
-	return status;
-}
-
-int
-ce_send(struct CE_handle *copyeng,
-		void *per_transfer_context,
-		cdf_dma_addr_t buffer,
-		uint32_t nbytes,
-		uint32_t transfer_id,
-		uint32_t flags,
-		uint32_t user_flag)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	int status;
-
-	cdf_spin_lock_bh(&CE_state->ce_index_lock);
-	status = ce_send_nolock(copyeng, per_transfer_context, buffer, nbytes,
-			transfer_id, flags, user_flag);
-	cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-
-	return status;
-}
-
-unsigned int ce_sendlist_sizeof(void)
-{
-	return sizeof(struct ce_sendlist);
-}
-
-void ce_sendlist_init(struct ce_sendlist *sendlist)
-{
-	struct ce_sendlist_s *sl = (struct ce_sendlist_s *)sendlist;
-	sl->num_items = 0;
-}
-
-int
-ce_sendlist_buf_add(struct ce_sendlist *sendlist,
-					cdf_dma_addr_t buffer,
-					uint32_t nbytes,
-					uint32_t flags,
-					uint32_t user_flags)
-{
-	struct ce_sendlist_s *sl = (struct ce_sendlist_s *)sendlist;
-	unsigned int num_items = sl->num_items;
-	struct ce_sendlist_item *item;
-
-	if (num_items >= CE_SENDLIST_ITEMS_MAX) {
-		CDF_ASSERT(num_items < CE_SENDLIST_ITEMS_MAX);
-		return CDF_STATUS_E_RESOURCES;
-	}
-
-	item = &sl->item[num_items];
-	item->send_type = CE_SIMPLE_BUFFER_TYPE;
-	item->data = buffer;
-	item->u.nbytes = nbytes;
-	item->flags = flags;
-	item->user_flags = user_flags;
-	sl->num_items = num_items + 1;
-	return CDF_STATUS_SUCCESS;
-}
-
-int
-ce_sendlist_send(struct CE_handle *copyeng,
-		 void *per_transfer_context,
-		 struct ce_sendlist *sendlist, unsigned int transfer_id)
-{
-	int status = -ENOMEM;
-	struct ce_sendlist_s *sl = (struct ce_sendlist_s *)sendlist;
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	struct CE_ring_state *src_ring = CE_state->src_ring;
-	unsigned int nentries_mask = src_ring->nentries_mask;
-	unsigned int num_items = sl->num_items;
-	unsigned int sw_index;
-	unsigned int write_index;
-
-	CDF_ASSERT((num_items > 0) && (num_items < src_ring->nentries));
-
-	cdf_spin_lock_bh(&CE_state->ce_index_lock);
-	sw_index = src_ring->sw_index;
-	write_index = src_ring->write_index;
-
-	if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) >=
-	    num_items) {
-		struct ce_sendlist_item *item;
-		int i;
-
-		/* handle all but the last item uniformly */
-		for (i = 0; i < num_items - 1; i++) {
-			item = &sl->item[i];
-			/* TBDXXX: Support extensible sendlist_types? */
-			CDF_ASSERT(item->send_type == CE_SIMPLE_BUFFER_TYPE);
-			status = ce_send_nolock(copyeng, CE_SENDLIST_ITEM_CTXT,
-				(cdf_dma_addr_t) item->data,
-				item->u.nbytes, transfer_id,
-				item->flags | CE_SEND_FLAG_GATHER,
-				item->user_flags);
-			CDF_ASSERT(status == CDF_STATUS_SUCCESS);
-		}
-		/* provide valid context pointer for final item */
-		item = &sl->item[i];
-		/* TBDXXX: Support extensible sendlist_types? */
-		CDF_ASSERT(item->send_type == CE_SIMPLE_BUFFER_TYPE);
-		status = ce_send_nolock(copyeng, per_transfer_context,
-					(cdf_dma_addr_t) item->data,
-					item->u.nbytes,
-					transfer_id, item->flags,
-					item->user_flags);
-		CDF_ASSERT(status == CDF_STATUS_SUCCESS);
-		NBUF_UPDATE_TX_PKT_COUNT((cdf_nbuf_t)per_transfer_context,
-					NBUF_TX_PKT_CE);
-		DPTRACE(cdf_dp_trace((cdf_nbuf_t)per_transfer_context,
-			CDF_DP_TRACE_CE_PACKET_PTR_RECORD,
-			(uint8_t *)(((cdf_nbuf_t)per_transfer_context)->data),
-			sizeof(((cdf_nbuf_t)per_transfer_context)->data)));
-	} else {
-		/*
-		 * Probably not worth the additional complexity to support
-		 * partial sends with continuation or notification.  We expect
-		 * to use large rings and small sendlists. If we can't handle
-		 * the entire request at once, punt it back to the caller.
-		 */
-	}
-	cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-
-	return status;
-}
-
-#ifdef WLAN_FEATURE_FASTPATH
-#ifdef QCA_WIFI_3_0
-static inline void
-ce_buffer_addr_hi_set(struct CE_src_desc *shadow_src_desc,
-		      uint64_t dma_addr,
-		      uint32_t user_flags)
-{
-	shadow_src_desc->buffer_addr_hi =
-			(uint32_t)((dma_addr >> 32) & 0x1F);
-	user_flags |= shadow_src_desc->buffer_addr_hi;
-	memcpy(&(((uint32_t *)shadow_src_desc)[1]), &user_flags,
-			sizeof(uint32_t));
-}
-#else
-static inline void
-ce_buffer_addr_hi_set(struct CE_src_desc *shadow_src_desc,
-		      uint64_t dma_addr,
-		      uint32_t user_flags)
-{
-}
-#endif
-
-/**
- * ce_send_fast() CE layer Tx buffer posting function
- * @copyeng: copy engine handle
- * @msdus: iarray of msdu to be sent
- * @num_msdus: number of msdus in an array
- * @transfer_id: transfer_id
- *
- * Assumption : Called with an array of MSDU's
- * Function:
- * For each msdu in the array
- * 1. Check no. of available entries
- * 2. Create src ring entries (allocated in consistent memory
- * 3. Write index to h/w
- *
- * Return: No. of packets that could be sent
- */
-
-int ce_send_fast(struct CE_handle *copyeng, cdf_nbuf_t *msdus,
-		 unsigned int num_msdus, unsigned int transfer_id)
-{
-	struct CE_state *ce_state = (struct CE_state *)copyeng;
-	struct ol_softc *scn = ce_state->scn;
-	struct CE_ring_state *src_ring = ce_state->src_ring;
-	u_int32_t ctrl_addr = ce_state->ctrl_addr;
-	unsigned int nentries_mask = src_ring->nentries_mask;
-	unsigned int write_index;
-	unsigned int sw_index;
-	unsigned int frag_len;
-	cdf_nbuf_t msdu;
-	int i;
-	uint64_t dma_addr;
-	uint32_t user_flags = 0;
-
-	cdf_spin_lock_bh(&ce_state->ce_index_lock);
-	sw_index = src_ring->sw_index;
-	write_index = src_ring->write_index;
-
-	/* 2 msdus per packet */
-	for (i = 0; i < num_msdus; i++) {
-		struct CE_src_desc *src_ring_base =
-			(struct CE_src_desc *)src_ring->base_addr_owner_space;
-		struct CE_src_desc *shadow_base =
-			(struct CE_src_desc *)src_ring->shadow_base;
-		struct CE_src_desc *src_desc =
-			CE_SRC_RING_TO_DESC(src_ring_base, write_index);
-		struct CE_src_desc *shadow_src_desc =
-			CE_SRC_RING_TO_DESC(shadow_base, write_index);
-
-		hif_pm_runtime_get_noresume(scn);
-		msdu = msdus[i];
-
-		/*
-		 * First fill out the ring descriptor for the HTC HTT frame
-		 * header. These are uncached writes. Should we use a local
-		 * structure instead?
-		 */
-		/* HTT/HTC header can be passed as a argument */
-		dma_addr = cdf_nbuf_get_frag_paddr_lo(msdu, 0);
-		shadow_src_desc->buffer_addr = (uint32_t)(dma_addr &
-							  0xFFFFFFFF);
-		user_flags = cdf_nbuf_data_attr_get(msdu) & DESC_DATA_FLAG_MASK;
-		ce_buffer_addr_hi_set(shadow_src_desc, dma_addr, user_flags);
-
-		shadow_src_desc->meta_data = transfer_id;
-		shadow_src_desc->nbytes = cdf_nbuf_get_frag_len(msdu, 0);
-
-		/*
-		 * HTC HTT header is a word stream, so byte swap if CE byte
-		 * swap enabled
-		 */
-		shadow_src_desc->byte_swap = ((ce_state->attr_flags &
-					CE_ATTR_BYTE_SWAP_DATA) != 0);
-		/* For the first one, it still does not need to write */
-		shadow_src_desc->gather = 1;
-		*src_desc = *shadow_src_desc;
-
-		/* By default we could initialize the transfer context to this
-		 * value
-		 */
-		src_ring->per_transfer_context[write_index] =
-			CE_SENDLIST_ITEM_CTXT;
-
-		write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
-
-		src_desc = CE_SRC_RING_TO_DESC(src_ring_base, write_index);
-		shadow_src_desc = CE_SRC_RING_TO_DESC(shadow_base, write_index);
-		/*
-		 * Now fill out the ring descriptor for the actual data
-		 * packet
-		 */
-		dma_addr = cdf_nbuf_get_frag_paddr_lo(msdu, 1);
-		shadow_src_desc->buffer_addr = (uint32_t)(dma_addr &
-							  0xFFFFFFFF);
-		/*
-		 * Clear packet offset for all but the first CE desc.
-		 */
-		user_flags &= ~CDF_CE_TX_PKT_OFFSET_BIT_M;
-		ce_buffer_addr_hi_set(shadow_src_desc, dma_addr, user_flags);
-		shadow_src_desc->meta_data = transfer_id;
-
-		/* get actual packet length */
-		frag_len = cdf_nbuf_get_frag_len(msdu, 1);
-
-		/* only read download_len once */
-		shadow_src_desc->nbytes =  ce_state->download_len;
-		if (shadow_src_desc->nbytes > frag_len)
-			shadow_src_desc->nbytes = frag_len;
-
-		/*  Data packet is a byte stream, so disable byte swap */
-		shadow_src_desc->byte_swap = 0;
-		/* For the last one, gather is not set */
-		shadow_src_desc->gather    = 0;
-		*src_desc = *shadow_src_desc;
-		src_ring->per_transfer_context[write_index] = msdu;
-		write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
-	}
-
-	/* Write the final index to h/w one-shot */
-	if (i) {
-		src_ring->write_index = write_index;
-
-		if (hif_pm_runtime_get(scn) == 0) {
-			/* Don't call WAR_XXX from here
-			 * Just call XXX instead, that has the reqd. intel
-			 */
-			war_ce_src_ring_write_idx_set(scn, ctrl_addr,
-					write_index);
-			hif_pm_runtime_put(scn);
-		}
-	}
-
-	cdf_spin_unlock_bh(&ce_state->ce_index_lock);
-
-	/*
-	 * If all packets in the array are transmitted,
-	 * i = num_msdus
-	 * Temporarily add an ASSERT
-	 */
-	ASSERT(i == num_msdus);
-	return i;
-}
-#endif /* WLAN_FEATURE_FASTPATH */
-
-int
-ce_recv_buf_enqueue(struct CE_handle *copyeng,
-		    void *per_recv_context, cdf_dma_addr_t buffer)
-{
-	int status;
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	struct CE_ring_state *dest_ring = CE_state->dest_ring;
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	unsigned int nentries_mask = dest_ring->nentries_mask;
-	unsigned int write_index;
-	unsigned int sw_index;
-	int val = 0;
-	uint64_t dma_addr = buffer;
-	struct ol_softc *scn = CE_state->scn;
-
-	cdf_spin_lock_bh(&CE_state->ce_index_lock);
-	write_index = dest_ring->write_index;
-	sw_index = dest_ring->sw_index;
-
-	A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val);
-	if (val == -1) {
-		cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-		return val;
-	}
-
-	if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) > 0) {
-		struct CE_dest_desc *dest_ring_base =
-			(struct CE_dest_desc *)dest_ring->
-			    base_addr_owner_space;
-		struct CE_dest_desc *dest_desc =
-			CE_DEST_RING_TO_DESC(dest_ring_base, write_index);
-
-		/* Update low 32 bit destination descriptor */
-		dest_desc->buffer_addr = (uint32_t)(dma_addr & 0xFFFFFFFF);
-#ifdef QCA_WIFI_3_0
-		dest_desc->buffer_addr_hi =
-			(uint32_t)((dma_addr >> 32) & 0x1F);
-#endif
-		dest_desc->nbytes = 0;
-
-		dest_ring->per_transfer_context[write_index] =
-			per_recv_context;
-
-		hif_record_ce_desc_event(CE_state->id, HIF_RX_DESC_POST,
-				(union ce_desc *) dest_desc, per_recv_context,
-				write_index);
-
-		/* Update Destination Ring Write Index */
-		write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
-		CE_DEST_RING_WRITE_IDX_SET(scn, ctrl_addr, write_index);
-		dest_ring->write_index = write_index;
-		status = CDF_STATUS_SUCCESS;
-	} else {
-		status = CDF_STATUS_E_FAILURE;
-	}
-	A_TARGET_ACCESS_END_RET_EXT(scn, val);
-	if (val == -1) {
-		cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-		return val;
-	}
-
-	cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-
-	return status;
-}
-
-void
-ce_send_watermarks_set(struct CE_handle *copyeng,
-		       unsigned int low_alert_nentries,
-		       unsigned int high_alert_nentries)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	struct ol_softc *scn = CE_state->scn;
-
-	CE_SRC_RING_LOWMARK_SET(scn, ctrl_addr, low_alert_nentries);
-	CE_SRC_RING_HIGHMARK_SET(scn, ctrl_addr, high_alert_nentries);
-}
-
-void
-ce_recv_watermarks_set(struct CE_handle *copyeng,
-		       unsigned int low_alert_nentries,
-		       unsigned int high_alert_nentries)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	struct ol_softc *scn = CE_state->scn;
-
-	CE_DEST_RING_LOWMARK_SET(scn, ctrl_addr,
-				low_alert_nentries);
-	CE_DEST_RING_HIGHMARK_SET(scn, ctrl_addr,
-				high_alert_nentries);
-}
-
-unsigned int ce_send_entries_avail(struct CE_handle *copyeng)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	struct CE_ring_state *src_ring = CE_state->src_ring;
-	unsigned int nentries_mask = src_ring->nentries_mask;
-	unsigned int sw_index;
-	unsigned int write_index;
-
-	cdf_spin_lock(&CE_state->ce_index_lock);
-	sw_index = src_ring->sw_index;
-	write_index = src_ring->write_index;
-	cdf_spin_unlock(&CE_state->ce_index_lock);
-
-	return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
-}
-
-unsigned int ce_recv_entries_avail(struct CE_handle *copyeng)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	struct CE_ring_state *dest_ring = CE_state->dest_ring;
-	unsigned int nentries_mask = dest_ring->nentries_mask;
-	unsigned int sw_index;
-	unsigned int write_index;
-
-	cdf_spin_lock(&CE_state->ce_index_lock);
-	sw_index = dest_ring->sw_index;
-	write_index = dest_ring->write_index;
-	cdf_spin_unlock(&CE_state->ce_index_lock);
-
-	return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
-}
-
-/*
- * Guts of ce_send_entries_done.
- * The caller takes responsibility for any necessary locking.
- */
-unsigned int
-ce_send_entries_done_nolock(struct ol_softc *scn,
-			    struct CE_state *CE_state)
-{
-	struct CE_ring_state *src_ring = CE_state->src_ring;
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	unsigned int nentries_mask = src_ring->nentries_mask;
-	unsigned int sw_index;
-	unsigned int read_index;
-
-	sw_index = src_ring->sw_index;
-	read_index = CE_SRC_RING_READ_IDX_GET(scn, ctrl_addr);
-
-	return CE_RING_DELTA(nentries_mask, sw_index, read_index);
-}
-
-unsigned int ce_send_entries_done(struct CE_handle *copyeng)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	unsigned int nentries;
-
-	cdf_spin_lock(&CE_state->ce_index_lock);
-	nentries = ce_send_entries_done_nolock(CE_state->scn, CE_state);
-	cdf_spin_unlock(&CE_state->ce_index_lock);
-
-	return nentries;
-}
-
-/*
- * Guts of ce_recv_entries_done.
- * The caller takes responsibility for any necessary locking.
- */
-unsigned int
-ce_recv_entries_done_nolock(struct ol_softc *scn,
-			    struct CE_state *CE_state)
-{
-	struct CE_ring_state *dest_ring = CE_state->dest_ring;
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	unsigned int nentries_mask = dest_ring->nentries_mask;
-	unsigned int sw_index;
-	unsigned int read_index;
-
-	sw_index = dest_ring->sw_index;
-	read_index = CE_DEST_RING_READ_IDX_GET(scn, ctrl_addr);
-
-	return CE_RING_DELTA(nentries_mask, sw_index, read_index);
-}
-
-unsigned int ce_recv_entries_done(struct CE_handle *copyeng)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	unsigned int nentries;
-
-	cdf_spin_lock(&CE_state->ce_index_lock);
-	nentries = ce_recv_entries_done_nolock(CE_state->scn, CE_state);
-	cdf_spin_unlock(&CE_state->ce_index_lock);
-
-	return nentries;
-}
-
-/* Debug support */
-void *ce_debug_cmplrn_context;  /* completed recv next context */
-void *ce_debug_cnclsn_context;  /* cancel send next context */
-void *ce_debug_rvkrn_context;   /* revoke receive next context */
-void *ce_debug_cmplsn_context;  /* completed send next context */
-
-/*
- * Guts of ce_completed_recv_next.
- * The caller takes responsibility for any necessary locking.
- */
-int
-ce_completed_recv_next_nolock(struct CE_state *CE_state,
-			      void **per_CE_contextp,
-			      void **per_transfer_contextp,
-			      cdf_dma_addr_t *bufferp,
-			      unsigned int *nbytesp,
-			      unsigned int *transfer_idp,
-			      unsigned int *flagsp)
-{
-	int status;
-	struct CE_ring_state *dest_ring = CE_state->dest_ring;
-	unsigned int nentries_mask = dest_ring->nentries_mask;
-	unsigned int sw_index = dest_ring->sw_index;
-
-	struct CE_dest_desc *dest_ring_base =
-		(struct CE_dest_desc *)dest_ring->base_addr_owner_space;
-	struct CE_dest_desc *dest_desc =
-		CE_DEST_RING_TO_DESC(dest_ring_base, sw_index);
-	int nbytes;
-	struct CE_dest_desc dest_desc_info;
-	/*
-	 * By copying the dest_desc_info element to local memory, we could
-	 * avoid extra memory read from non-cachable memory.
-	 */
-	dest_desc_info =  *dest_desc;
-	nbytes = dest_desc_info.nbytes;
-	if (nbytes == 0) {
-		/*
-		 * This closes a relatively unusual race where the Host
-		 * sees the updated DRRI before the update to the
-		 * corresponding descriptor has completed. We treat this
-		 * as a descriptor that is not yet done.
-		 */
-		status = CDF_STATUS_E_FAILURE;
-		goto done;
-	}
-
-	hif_record_ce_desc_event(CE_state->id, HIF_RX_DESC_COMPLETION,
-			(union ce_desc *) dest_desc,
-			dest_ring->per_transfer_context[sw_index],
-			sw_index);
-
-	dest_desc->nbytes = 0;
-
-	/* Return data from completed destination descriptor */
-	*bufferp = HIF_CE_DESC_ADDR_TO_DMA(&dest_desc_info);
-	*nbytesp = nbytes;
-	*transfer_idp = dest_desc_info.meta_data;
-	*flagsp = (dest_desc_info.byte_swap) ? CE_RECV_FLAG_SWAPPED : 0;
-
-	if (per_CE_contextp) {
-		*per_CE_contextp = CE_state->recv_context;
-	}
-
-	ce_debug_cmplrn_context = dest_ring->per_transfer_context[sw_index];
-	if (per_transfer_contextp) {
-		*per_transfer_contextp = ce_debug_cmplrn_context;
-	}
-	dest_ring->per_transfer_context[sw_index] = 0;  /* sanity */
-
-	/* Update sw_index */
-	sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
-	dest_ring->sw_index = sw_index;
-	status = CDF_STATUS_SUCCESS;
-
-done:
-	return status;
-}
-
-int
-ce_completed_recv_next(struct CE_handle *copyeng,
-		       void **per_CE_contextp,
-		       void **per_transfer_contextp,
-		       cdf_dma_addr_t *bufferp,
-		       unsigned int *nbytesp,
-		       unsigned int *transfer_idp, unsigned int *flagsp)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	int status;
-
-	cdf_spin_lock_bh(&CE_state->ce_index_lock);
-	status =
-		ce_completed_recv_next_nolock(CE_state, per_CE_contextp,
-					      per_transfer_contextp, bufferp,
-					      nbytesp, transfer_idp, flagsp);
-	cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-
-	return status;
-}
-
-/* NB: Modeled after ce_completed_recv_next_nolock */
-CDF_STATUS
-ce_revoke_recv_next(struct CE_handle *copyeng,
-		    void **per_CE_contextp,
-		    void **per_transfer_contextp, cdf_dma_addr_t *bufferp)
-{
-	struct CE_state *CE_state;
-	struct CE_ring_state *dest_ring;
-	unsigned int nentries_mask;
-	unsigned int sw_index;
-	unsigned int write_index;
-	CDF_STATUS status;
-	struct ol_softc *scn;
-
-	CE_state = (struct CE_state *)copyeng;
-	dest_ring = CE_state->dest_ring;
-	if (!dest_ring) {
-		return CDF_STATUS_E_FAILURE;
-	}
-
-	scn = CE_state->scn;
-	cdf_spin_lock(&CE_state->ce_index_lock);
-	nentries_mask = dest_ring->nentries_mask;
-	sw_index = dest_ring->sw_index;
-	write_index = dest_ring->write_index;
-	if (write_index != sw_index) {
-		struct CE_dest_desc *dest_ring_base =
-			(struct CE_dest_desc *)dest_ring->
-			    base_addr_owner_space;
-		struct CE_dest_desc *dest_desc =
-			CE_DEST_RING_TO_DESC(dest_ring_base, sw_index);
-
-		/* Return data from completed destination descriptor */
-		*bufferp = HIF_CE_DESC_ADDR_TO_DMA(dest_desc);
-
-		if (per_CE_contextp) {
-			*per_CE_contextp = CE_state->recv_context;
-		}
-
-		ce_debug_rvkrn_context =
-			dest_ring->per_transfer_context[sw_index];
-		if (per_transfer_contextp) {
-			*per_transfer_contextp = ce_debug_rvkrn_context;
-		}
-		dest_ring->per_transfer_context[sw_index] = 0;  /* sanity */
-
-		/* Update sw_index */
-		sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
-		dest_ring->sw_index = sw_index;
-		status = CDF_STATUS_SUCCESS;
-	} else {
-		status = CDF_STATUS_E_FAILURE;
-	}
-	cdf_spin_unlock(&CE_state->ce_index_lock);
-
-	return status;
-}
-
-/*
- * Guts of ce_completed_send_next.
- * The caller takes responsibility for any necessary locking.
- */
-int
-ce_completed_send_next_nolock(struct CE_state *CE_state,
-			      void **per_CE_contextp,
-			      void **per_transfer_contextp,
-			      cdf_dma_addr_t *bufferp,
-			      unsigned int *nbytesp,
-			      unsigned int *transfer_idp,
-			      unsigned int *sw_idx,
-			      unsigned int *hw_idx,
-			      uint32_t *toeplitz_hash_result)
-{
-	int status = CDF_STATUS_E_FAILURE;
-	struct CE_ring_state *src_ring = CE_state->src_ring;
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	unsigned int nentries_mask = src_ring->nentries_mask;
-	unsigned int sw_index = src_ring->sw_index;
-	unsigned int read_index;
-	struct ol_softc *scn = CE_state->scn;
-
-	if (src_ring->hw_index == sw_index) {
-		/*
-		 * The SW completion index has caught up with the cached
-		 * version of the HW completion index.
-		 * Update the cached HW completion index to see whether
-		 * the SW has really caught up to the HW, or if the cached
-		 * value of the HW index has become stale.
-		 */
-		A_TARGET_ACCESS_BEGIN_RET(scn);
-		src_ring->hw_index =
-			CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, ctrl_addr);
-		A_TARGET_ACCESS_END_RET(scn);
-	}
-	read_index = src_ring->hw_index;
-
-	if (sw_idx)
-		*sw_idx = sw_index;
-
-	if (hw_idx)
-		*hw_idx = read_index;
-
-	if ((read_index != sw_index) && (read_index != 0xffffffff)) {
-		struct CE_src_desc *shadow_base =
-			(struct CE_src_desc *)src_ring->shadow_base;
-		struct CE_src_desc *shadow_src_desc =
-			CE_SRC_RING_TO_DESC(shadow_base, sw_index);
-#ifdef QCA_WIFI_3_0
-		struct CE_src_desc *src_ring_base =
-			(struct CE_src_desc *)src_ring->base_addr_owner_space;
-		struct CE_src_desc *src_desc =
-			CE_SRC_RING_TO_DESC(src_ring_base, sw_index);
-#endif
-		hif_record_ce_desc_event(CE_state->id, HIF_TX_DESC_COMPLETION,
-				(union ce_desc *) shadow_src_desc,
-				src_ring->per_transfer_context[sw_index],
-				sw_index);
-
-		/* Return data from completed source descriptor */
-		*bufferp = HIF_CE_DESC_ADDR_TO_DMA(shadow_src_desc);
-		*nbytesp = shadow_src_desc->nbytes;
-		*transfer_idp = shadow_src_desc->meta_data;
-#ifdef QCA_WIFI_3_0
-		*toeplitz_hash_result = src_desc->toeplitz_hash_result;
-#else
-		*toeplitz_hash_result = 0;
-#endif
-		if (per_CE_contextp) {
-			*per_CE_contextp = CE_state->send_context;
-		}
-
-		ce_debug_cmplsn_context =
-			src_ring->per_transfer_context[sw_index];
-		if (per_transfer_contextp) {
-			*per_transfer_contextp = ce_debug_cmplsn_context;
-		}
-		src_ring->per_transfer_context[sw_index] = 0;   /* sanity */
-
-		/* Update sw_index */
-		sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
-		src_ring->sw_index = sw_index;
-		status = CDF_STATUS_SUCCESS;
-	}
-
-	return status;
-}
-
-/* NB: Modeled after ce_completed_send_next */
-CDF_STATUS
-ce_cancel_send_next(struct CE_handle *copyeng,
-		void **per_CE_contextp,
-		void **per_transfer_contextp,
-		cdf_dma_addr_t *bufferp,
-		unsigned int *nbytesp,
-		unsigned int *transfer_idp,
-		uint32_t *toeplitz_hash_result)
-{
-	struct CE_state *CE_state;
-	struct CE_ring_state *src_ring;
-	unsigned int nentries_mask;
-	unsigned int sw_index;
-	unsigned int write_index;
-	CDF_STATUS status;
-	struct ol_softc *scn;
-
-	CE_state = (struct CE_state *)copyeng;
-	src_ring = CE_state->src_ring;
-	if (!src_ring) {
-		return CDF_STATUS_E_FAILURE;
-	}
-
-	scn = CE_state->scn;
-	cdf_spin_lock(&CE_state->ce_index_lock);
-	nentries_mask = src_ring->nentries_mask;
-	sw_index = src_ring->sw_index;
-	write_index = src_ring->write_index;
-
-	if (write_index != sw_index) {
-		struct CE_src_desc *src_ring_base =
-			(struct CE_src_desc *)src_ring->base_addr_owner_space;
-		struct CE_src_desc *src_desc =
-			CE_SRC_RING_TO_DESC(src_ring_base, sw_index);
-
-		/* Return data from completed source descriptor */
-		*bufferp = HIF_CE_DESC_ADDR_TO_DMA(src_desc);
-		*nbytesp = src_desc->nbytes;
-		*transfer_idp = src_desc->meta_data;
-#ifdef QCA_WIFI_3_0
-		*toeplitz_hash_result = src_desc->toeplitz_hash_result;
-#else
-		*toeplitz_hash_result = 0;
-#endif
-
-		if (per_CE_contextp) {
-			*per_CE_contextp = CE_state->send_context;
-		}
-
-		ce_debug_cnclsn_context =
-			src_ring->per_transfer_context[sw_index];
-		if (per_transfer_contextp) {
-			*per_transfer_contextp = ce_debug_cnclsn_context;
-		}
-		src_ring->per_transfer_context[sw_index] = 0;   /* sanity */
-
-		/* Update sw_index */
-		sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
-		src_ring->sw_index = sw_index;
-		status = CDF_STATUS_SUCCESS;
-	} else {
-		status = CDF_STATUS_E_FAILURE;
-	}
-	cdf_spin_unlock(&CE_state->ce_index_lock);
-
-	return status;
-}
-
-/* Shift bits to convert IS_*_RING_*_WATERMARK_MASK to CE_WM_FLAG_*_* */
-#define CE_WM_SHFT 1
-
-int
-ce_completed_send_next(struct CE_handle *copyeng,
-		       void **per_CE_contextp,
-		       void **per_transfer_contextp,
-		       cdf_dma_addr_t *bufferp,
-		       unsigned int *nbytesp,
-		       unsigned int *transfer_idp,
-		       unsigned int *sw_idx,
-		       unsigned int *hw_idx,
-		       unsigned int *toeplitz_hash_result)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-	int status;
-
-	cdf_spin_lock_bh(&CE_state->ce_index_lock);
-	status =
-		ce_completed_send_next_nolock(CE_state, per_CE_contextp,
-					      per_transfer_contextp, bufferp,
-					      nbytesp, transfer_idp, sw_idx,
-					      hw_idx, toeplitz_hash_result);
-	cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-
-	return status;
-}
-
-#ifdef ATH_11AC_TXCOMPACT
-/* CE engine descriptor reap
- * Similar to ce_per_engine_service , Only difference is ce_per_engine_service
- * does recieve and reaping of completed descriptor ,
- * This function only handles reaping of Tx complete descriptor.
- * The Function is called from threshold reap  poll routine
- * hif_send_complete_check so should not countain recieve functionality
- * within it .
- */
-
-void ce_per_engine_servicereap(struct ol_softc *scn, unsigned int ce_id)
-{
-	void *CE_context;
-	void *transfer_context;
-	cdf_dma_addr_t buf;
-	unsigned int nbytes;
-	unsigned int id;
-	unsigned int sw_idx, hw_idx;
-	uint32_t toeplitz_hash_result;
-	struct CE_state *CE_state = scn->ce_id_to_state[ce_id];
-
-	A_TARGET_ACCESS_BEGIN(scn);
-	hif_record_ce_desc_event(ce_id, HIF_CE_REAP_ENTRY,
-			NULL, NULL, 0);
-
-	/* Since this function is called from both user context and
-	 * tasklet context the spinlock has to lock the bottom halves.
-	 * This fix assumes that ATH_11AC_TXCOMPACT flag is always
-	 * enabled in TX polling mode. If this is not the case, more
-	 * bottom halve spin lock changes are needed. Due to data path
-	 * performance concern, after internal discussion we've decided
-	 * to make minimum change, i.e., only address the issue occured
-	 * in this function. The possible negative effect of this minimum
-	 * change is that, in the future, if some other function will also
-	 * be opened to let the user context to use, those cases need to be
-	 * addressed by change spin_lock to spin_lock_bh also.
-	 */
-
-	cdf_spin_lock_bh(&CE_state->ce_index_lock);
-
-	if (CE_state->send_cb) {
-		{
-			/* Pop completed send buffers and call the
-			 * registered send callback for each
-			 */
-			while (ce_completed_send_next_nolock
-				 (CE_state, &CE_context,
-				  &transfer_context, &buf,
-				  &nbytes, &id, &sw_idx, &hw_idx,
-				  &toeplitz_hash_result) ==
-				  CDF_STATUS_SUCCESS) {
-				if (ce_id != CE_HTT_H2T_MSG) {
-					cdf_spin_unlock_bh(
-						&CE_state->ce_index_lock);
-					CE_state->send_cb(
-						(struct CE_handle *)
-						CE_state, CE_context,
-						transfer_context, buf,
-						nbytes, id, sw_idx, hw_idx,
-						toeplitz_hash_result);
-					cdf_spin_lock_bh(
-						&CE_state->ce_index_lock);
-				} else {
-					struct HIF_CE_pipe_info *pipe_info =
-						(struct HIF_CE_pipe_info *)
-						CE_context;
-
-					cdf_spin_lock_bh(&pipe_info->
-						 completion_freeq_lock);
-					pipe_info->num_sends_allowed++;
-					cdf_spin_unlock_bh(&pipe_info->
-						   completion_freeq_lock);
-				}
-			}
-		}
-	}
-
-	cdf_spin_unlock_bh(&CE_state->ce_index_lock);
-
-	hif_record_ce_desc_event(ce_id, HIF_CE_REAP_EXIT,
-			NULL, NULL, 0);
-	A_TARGET_ACCESS_END(scn);
-}
-
-#endif /*ATH_11AC_TXCOMPACT */
-
-/*
- * Number of times to check for any pending tx/rx completion on
- * a copy engine, this count should be big enough. Once we hit
- * this threashold we'll not check for any Tx/Rx comlpetion in same
- * interrupt handling. Note that this threashold is only used for
- * Rx interrupt processing, this can be used tor Tx as well if we
- * suspect any infinite loop in checking for pending Tx completion.
- */
-#define CE_TXRX_COMP_CHECK_THRESHOLD 20
-
-/*
- * Guts of interrupt handler for per-engine interrupts on a particular CE.
- *
- * Invokes registered callbacks for recv_complete,
- * send_complete, and watermarks.
- *
- * Returns: number of messages processed
- */
-
-int ce_per_engine_service(struct ol_softc *scn, unsigned int CE_id)
-{
-	struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	void *CE_context;
-	void *transfer_context;
-	cdf_dma_addr_t buf;
-	unsigned int nbytes;
-	unsigned int id;
-	unsigned int flags;
-	uint32_t CE_int_status;
-	unsigned int more_comp_cnt = 0;
-	unsigned int more_snd_comp_cnt = 0;
-	unsigned int sw_idx, hw_idx;
-	uint32_t toeplitz_hash_result;
-
-	if (Q_TARGET_ACCESS_BEGIN(scn) < 0) {
-		HIF_ERROR("[premature rc=0]\n");
-		return 0; /* no work done */
-	}
-
-	cdf_spin_lock(&CE_state->ce_index_lock);
-
-	/* Clear force_break flag and re-initialize receive_count to 0 */
-
-	/* NAPI: scn variables- thread/multi-processing safety? */
-	CE_state->receive_count = 0;
-	CE_state->force_break = 0;
-more_completions:
-	if (CE_state->recv_cb) {
-
-		/* Pop completed recv buffers and call
-		 * the registered recv callback for each
-		 */
-		while (ce_completed_recv_next_nolock
-				(CE_state, &CE_context, &transfer_context,
-				&buf, &nbytes, &id, &flags) ==
-				CDF_STATUS_SUCCESS) {
-			cdf_spin_unlock(&CE_state->ce_index_lock);
-			CE_state->recv_cb((struct CE_handle *)CE_state,
-					  CE_context, transfer_context, buf,
-					  nbytes, id, flags);
-
-			/*
-			 * EV #112693 -
-			 * [Peregrine][ES1][WB342][Win8x86][Performance]
-			 * BSoD_0x133 occurred in VHT80 UDP_DL
-			 * Break out DPC by force if number of loops in
-			 * hif_pci_ce_recv_data reaches MAX_NUM_OF_RECEIVES
-			 * to avoid spending too long time in
-			 * DPC for each interrupt handling. Schedule another
-			 * DPC to avoid data loss if we had taken
-			 * force-break action before apply to Windows OS
-			 * only currently, Linux/MAC os can expand to their
-			 * platform if necessary
-			 */
-
-			/* Break the receive processes by
-			 * force if force_break set up
-			 */
-			if (cdf_unlikely(CE_state->force_break)) {
-				cdf_atomic_set(&CE_state->rx_pending, 1);
-				CE_ENGINE_INT_STATUS_CLEAR(scn, ctrl_addr,
-					HOST_IS_COPY_COMPLETE_MASK);
-				if (Q_TARGET_ACCESS_END(scn) < 0)
-					HIF_ERROR("<--[premature rc=%d]\n",
-						  CE_state->receive_count);
-				return CE_state->receive_count;
-			}
-			cdf_spin_lock(&CE_state->ce_index_lock);
-		}
-	}
-
-	/*
-	 * Attention: We may experience potential infinite loop for below
-	 * While Loop during Sending Stress test.
-	 * Resolve the same way as Receive Case (Refer to EV #112693)
-	 */
-
-	if (CE_state->send_cb) {
-		/* Pop completed send buffers and call
-		 * the registered send callback for each
-		 */
-
-#ifdef ATH_11AC_TXCOMPACT
-		while (ce_completed_send_next_nolock
-			 (CE_state, &CE_context,
-			 &transfer_context, &buf, &nbytes,
-			 &id, &sw_idx, &hw_idx,
-			 &toeplitz_hash_result) == CDF_STATUS_SUCCESS) {
-
-			if (CE_id != CE_HTT_H2T_MSG ||
-			    WLAN_IS_EPPING_ENABLED(cds_get_conparam())) {
-				cdf_spin_unlock(&CE_state->ce_index_lock);
-				CE_state->send_cb((struct CE_handle *)CE_state,
-						  CE_context, transfer_context,
-						  buf, nbytes, id, sw_idx,
-						  hw_idx, toeplitz_hash_result);
-				cdf_spin_lock(&CE_state->ce_index_lock);
-			} else {
-				struct HIF_CE_pipe_info *pipe_info =
-					(struct HIF_CE_pipe_info *)CE_context;
-
-				cdf_spin_lock(&pipe_info->
-					      completion_freeq_lock);
-				pipe_info->num_sends_allowed++;
-				cdf_spin_unlock(&pipe_info->
-						completion_freeq_lock);
-			}
-		}
-#else                           /*ATH_11AC_TXCOMPACT */
-		while (ce_completed_send_next_nolock
-			 (CE_state, &CE_context,
-			  &transfer_context, &buf, &nbytes,
-			  &id, &sw_idx, &hw_idx,
-			  &toeplitz_hash_result) == CDF_STATUS_SUCCESS) {
-			cdf_spin_unlock(&CE_state->ce_index_lock);
-			CE_state->send_cb((struct CE_handle *)CE_state,
-				  CE_context, transfer_context, buf,
-				  nbytes, id, sw_idx, hw_idx,
-				  toeplitz_hash_result);
-			cdf_spin_lock(&CE_state->ce_index_lock);
-		}
-#endif /*ATH_11AC_TXCOMPACT */
-	}
-
-more_watermarks:
-	if (CE_state->misc_cbs) {
-		CE_int_status = CE_ENGINE_INT_STATUS_GET(scn, ctrl_addr);
-		if (CE_int_status & CE_WATERMARK_MASK) {
-			if (CE_state->watermark_cb) {
-				cdf_spin_unlock(&CE_state->ce_index_lock);
-				/* Convert HW IS bits to software flags */
-				flags =
-					(CE_int_status & CE_WATERMARK_MASK) >>
-					CE_WM_SHFT;
-
-				CE_state->
-				watermark_cb((struct CE_handle *)CE_state,
-					     CE_state->wm_context, flags);
-				cdf_spin_lock(&CE_state->ce_index_lock);
-			}
-		}
-	}
-
-	/*
-	 * Clear the misc interrupts (watermark) that were handled above,
-	 * and that will be checked again below.
-	 * Clear and check for copy-complete interrupts again, just in case
-	 * more copy completions happened while the misc interrupts were being
-	 * handled.
-	 */
-	CE_ENGINE_INT_STATUS_CLEAR(scn, ctrl_addr,
-				   CE_WATERMARK_MASK |
-				   HOST_IS_COPY_COMPLETE_MASK);
-
-	/*
-	 * Now that per-engine interrupts are cleared, verify that
-	 * no recv interrupts arrive while processing send interrupts,
-	 * and no recv or send interrupts happened while processing
-	 * misc interrupts.Go back and check again.Keep checking until
-	 * we find no more events to process.
-	 */
-	if (CE_state->recv_cb && ce_recv_entries_done_nolock(scn, CE_state)) {
-		if (WLAN_IS_EPPING_ENABLED(cds_get_conparam()) ||
-		    more_comp_cnt++ < CE_TXRX_COMP_CHECK_THRESHOLD) {
-			goto more_completions;
-		} else {
-			HIF_ERROR(
-				"%s:Potential infinite loop detected during Rx processing nentries_mask:0x%x sw read_idx:0x%x hw read_idx:0x%x",
-				__func__, CE_state->dest_ring->nentries_mask,
-				CE_state->dest_ring->sw_index,
-				CE_DEST_RING_READ_IDX_GET(scn,
-							  CE_state->ctrl_addr));
-		}
-	}
-
-	if (CE_state->send_cb && ce_send_entries_done_nolock(scn, CE_state)) {
-		if (WLAN_IS_EPPING_ENABLED(cds_get_conparam()) ||
-		    more_snd_comp_cnt++ < CE_TXRX_COMP_CHECK_THRESHOLD) {
-			goto more_completions;
-		} else {
-			HIF_ERROR(
-				"%s:Potential infinite loop detected during send completion nentries_mask:0x%x sw read_idx:0x%x hw read_idx:0x%x",
-				__func__, CE_state->src_ring->nentries_mask,
-				CE_state->src_ring->sw_index,
-				CE_SRC_RING_READ_IDX_GET(scn,
-							 CE_state->ctrl_addr));
-		}
-	}
-
-	if (CE_state->misc_cbs) {
-		CE_int_status = CE_ENGINE_INT_STATUS_GET(scn, ctrl_addr);
-		if (CE_int_status & CE_WATERMARK_MASK) {
-			if (CE_state->watermark_cb) {
-				goto more_watermarks;
-			}
-		}
-	}
-
-	cdf_spin_unlock(&CE_state->ce_index_lock);
-	cdf_atomic_set(&CE_state->rx_pending, 0);
-
-	if (Q_TARGET_ACCESS_END(scn) < 0)
-		HIF_ERROR("<--[premature rc=%d]\n", CE_state->receive_count);
-	return CE_state->receive_count;
-}
-
-/*
- * Handler for per-engine interrupts on ALL active CEs.
- * This is used in cases where the system is sharing a
- * single interrput for all CEs
- */
-
-void ce_per_engine_service_any(int irq, struct ol_softc *scn)
-{
-	int CE_id;
-	uint32_t intr_summary;
-
-	A_TARGET_ACCESS_BEGIN(scn);
-	if (!cdf_atomic_read(&scn->tasklet_from_intr)) {
-		for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
-			struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
-			if (cdf_atomic_read(&CE_state->rx_pending)) {
-				cdf_atomic_set(&CE_state->rx_pending, 0);
-				ce_per_engine_service(scn, CE_id);
-			}
-		}
-
-		A_TARGET_ACCESS_END(scn);
-		return;
-	}
-
-	intr_summary = CE_INTERRUPT_SUMMARY(scn);
-
-	for (CE_id = 0; intr_summary && (CE_id < scn->ce_count); CE_id++) {
-		if (intr_summary & (1 << CE_id)) {
-			intr_summary &= ~(1 << CE_id);
-		} else {
-			continue;       /* no intr pending on this CE */
-		}
-
-		ce_per_engine_service(scn, CE_id);
-	}
-
-	A_TARGET_ACCESS_END(scn);
-}
-
-/*
- * Adjust interrupts for the copy complete handler.
- * If it's needed for either send or recv, then unmask
- * this interrupt; otherwise, mask it.
- *
- * Called with target_lock held.
- */
-static void
-ce_per_engine_handler_adjust(struct CE_state *CE_state,
-			     int disable_copy_compl_intr)
-{
-	uint32_t ctrl_addr = CE_state->ctrl_addr;
-	struct ol_softc *scn = CE_state->scn;
-
-	CE_state->disable_copy_compl_intr = disable_copy_compl_intr;
-	A_TARGET_ACCESS_BEGIN(scn);
-	if ((!disable_copy_compl_intr) &&
-	    (CE_state->send_cb || CE_state->recv_cb)) {
-		CE_COPY_COMPLETE_INTR_ENABLE(scn, ctrl_addr);
-	} else {
-		CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr);
-	}
-
-	if (CE_state->watermark_cb) {
-		CE_WATERMARK_INTR_ENABLE(scn, ctrl_addr);
-	} else {
-		CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr);
-	}
-	A_TARGET_ACCESS_END(scn);
-
-}
-
-/*Iterate the CE_state list and disable the compl interrupt
- * if it has been registered already.
- */
-void ce_disable_any_copy_compl_intr_nolock(struct ol_softc *scn)
-{
-	int CE_id;
-
-	A_TARGET_ACCESS_BEGIN(scn);
-	for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
-		struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
-		uint32_t ctrl_addr = CE_state->ctrl_addr;
-
-		/* if the interrupt is currently enabled, disable it */
-		if (!CE_state->disable_copy_compl_intr
-		    && (CE_state->send_cb || CE_state->recv_cb)) {
-			CE_COPY_COMPLETE_INTR_DISABLE(scn, ctrl_addr);
-		}
-
-		if (CE_state->watermark_cb) {
-			CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr);
-		}
-	}
-	A_TARGET_ACCESS_END(scn);
-}
-
-void ce_enable_any_copy_compl_intr_nolock(struct ol_softc *scn)
-{
-	int CE_id;
-
-	A_TARGET_ACCESS_BEGIN(scn);
-	for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
-		struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
-		uint32_t ctrl_addr = CE_state->ctrl_addr;
-
-		/*
-		 * If the CE is supposed to have copy complete interrupts
-		 * enabled (i.e. there a callback registered, and the
-		 * "disable" flag is not set), then re-enable the interrupt.
-		 */
-		if (!CE_state->disable_copy_compl_intr
-		    && (CE_state->send_cb || CE_state->recv_cb)) {
-			CE_COPY_COMPLETE_INTR_ENABLE(scn, ctrl_addr);
-		}
-
-		if (CE_state->watermark_cb) {
-			CE_WATERMARK_INTR_ENABLE(scn, ctrl_addr);
-		}
-	}
-	A_TARGET_ACCESS_END(scn);
-}
-
-/**
- * ce_send_cb_register(): register completion handler
- * @copyeng: CE_state representing the ce we are adding the behavior to
- * @fn_ptr: callback that the ce should use when processing tx completions
- * @disable_interrupts: if the interupts should be enabled or not.
- *
- * Caller should guarantee that no transactions are in progress before
- * switching the callback function.
- *
- * Registers the send context before the fn pointer so that if the cb is valid
- * the context should be valid.
- *
- * Beware that currently this function will enable completion interrupts.
- */
-void
-ce_send_cb_register(struct CE_handle *copyeng,
-		    ce_send_cb fn_ptr,
-		    void *ce_send_context, int disable_interrupts)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-
-	if (CE_state == NULL) {
-		pr_err("%s: Error CE state = NULL\n", __func__);
-		return;
-	}
-	CE_state->send_context = ce_send_context;
-	CE_state->send_cb = fn_ptr;
-	ce_per_engine_handler_adjust(CE_state, disable_interrupts);
-}
-
-/**
- * ce_recv_cb_register(): register completion handler
- * @copyeng: CE_state representing the ce we are adding the behavior to
- * @fn_ptr: callback that the ce should use when processing rx completions
- * @disable_interrupts: if the interupts should be enabled or not.
- *
- * Registers the send context before the fn pointer so that if the cb is valid
- * the context should be valid.
- *
- * Caller should guarantee that no transactions are in progress before
- * switching the callback function.
- */
-void
-ce_recv_cb_register(struct CE_handle *copyeng,
-		    CE_recv_cb fn_ptr,
-		    void *CE_recv_context, int disable_interrupts)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-
-	if (CE_state == NULL) {
-		pr_err("%s: ERROR CE state = NULL\n", __func__);
-		return;
-	}
-	CE_state->recv_context = CE_recv_context;
-	CE_state->recv_cb = fn_ptr;
-	ce_per_engine_handler_adjust(CE_state, disable_interrupts);
-}
-
-/**
- * ce_watermark_cb_register(): register completion handler
- * @copyeng: CE_state representing the ce we are adding the behavior to
- * @fn_ptr: callback that the ce should use when processing watermark events
- *
- * Caller should guarantee that no watermark events are being processed before
- * switching the callback function.
- */
-void
-ce_watermark_cb_register(struct CE_handle *copyeng,
-			 CE_watermark_cb fn_ptr, void *CE_wm_context)
-{
-	struct CE_state *CE_state = (struct CE_state *)copyeng;
-
-	CE_state->watermark_cb = fn_ptr;
-	CE_state->wm_context = CE_wm_context;
-	ce_per_engine_handler_adjust(CE_state, 0);
-	if (fn_ptr) {
-		CE_state->misc_cbs = 1;
-	}
-}
-
-#ifdef WLAN_FEATURE_FASTPATH
-/**
- * ce_pkt_dl_len_set() set the HTT packet download length
- * @hif_sc: HIF context
- * @pkt_download_len: download length
- *
- * Return: None
- */
-void ce_pkt_dl_len_set(void *hif_sc, u_int32_t pkt_download_len)
-{
-	struct ol_softc *sc = (struct ol_softc *)(hif_sc);
-	struct CE_state *ce_state = sc->ce_id_to_state[CE_HTT_H2T_MSG];
-
-	cdf_assert_always(ce_state);
-
-	ce_state->download_len = pkt_download_len;
-
-	cdf_print("%s CE %d Pkt download length %d\n", __func__,
-		  ce_state->id, ce_state->download_len);
-}
-#else
-void ce_pkt_dl_len_set(void *hif_sc, u_int32_t pkt_download_len)
-{
-}
-#endif /* WLAN_FEATURE_FASTPATH */
-
-bool ce_get_rx_pending(struct ol_softc *scn)
-{
-	int CE_id;
-
-	for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
-		struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
-		if (cdf_atomic_read(&CE_state->rx_pending))
-			return true;
-	}
-
-	return false;
-}
-
-/**
- * ce_check_rx_pending() - ce_check_rx_pending
- * @scn: ol_softc
- * @ce_id: ce_id
- *
- * Return: bool
- */
-bool ce_check_rx_pending(struct ol_softc *scn, int ce_id)
-{
-	struct CE_state *CE_state = scn->ce_id_to_state[ce_id];
-	if (cdf_atomic_read(&CE_state->rx_pending))
-		return true;
-	else
-		return false;
-}
-
-/**
- * ce_enable_msi(): write the msi configuration to the target
- * @scn: hif context
- * @CE_id: which copy engine will be configured for msi interupts
- * @msi_addr_lo: Hardware will write to this address to generate an interrupt
- * @msi_addr_hi: Hardware will write to this address to generate an interrupt
- * @msi_data: Hardware will write this data to generate an interrupt
- *
- * should be done in the initialization sequence so no locking would be needed
- */
-void ce_enable_msi(struct ol_softc *scn, unsigned int CE_id,
-				   uint32_t msi_addr_lo, uint32_t msi_addr_hi,
-				   uint32_t msi_data)
-{
-#ifdef WLAN_ENABLE_QCA6180
-	struct CE_state *CE_state;
-	A_target_id_t targid;
-	u_int32_t ctrl_addr;
-	uint32_t tmp;
-
-	CE_state = scn->ce_id_to_state[CE_id];
-	if (!CE_state) {
-		HIF_ERROR("%s: error - CE_state = NULL", __func__);
-		return;
-	}
-	targid = TARGID(sc);
-	ctrl_addr = CE_state->ctrl_addr;
-	CE_MSI_ADDR_LOW_SET(scn, ctrl_addr, msi_addr_lo);
-	CE_MSI_ADDR_HIGH_SET(scn, ctrl_addr, msi_addr_hi);
-	CE_MSI_DATA_SET(scn, ctrl_addr, msi_data);
-	tmp = CE_CTRL_REGISTER1_GET(scn, ctrl_addr);
-	tmp |= (1 << CE_MSI_ENABLE_BIT);
-	CE_CTRL_REGISTER1_SET(scn, ctrl_addr, tmp);
-#endif
-}
-
-#ifdef IPA_OFFLOAD
-/**
- * ce_ipa_get_resource() - get uc resource on copyengine
- * @ce: copyengine context
- * @ce_sr_base_paddr: copyengine source ring base physical address
- * @ce_sr_ring_size: copyengine source ring size
- * @ce_reg_paddr: copyengine register physical address
- *
- * Copy engine should release resource to micro controller
- * Micro controller needs
- *  - Copy engine source descriptor base address
- *  - Copy engine source descriptor size
- *  - PCI BAR address to access copy engine regiser
- *
- * Return: None
- */
-void ce_ipa_get_resource(struct CE_handle *ce,
-			 cdf_dma_addr_t *ce_sr_base_paddr,
-			 uint32_t *ce_sr_ring_size,
-			 cdf_dma_addr_t *ce_reg_paddr)
-{
-	struct CE_state *CE_state = (struct CE_state *)ce;
-	uint32_t ring_loop;
-	struct CE_src_desc *ce_desc;
-	cdf_dma_addr_t phy_mem_base;
-	struct ol_softc *scn = CE_state->scn;
-
-	if (CE_RUNNING != CE_state->state) {
-		*ce_sr_base_paddr = 0;
-		*ce_sr_ring_size = 0;
-		return;
-	}
-
-	/* Update default value for descriptor */
-	for (ring_loop = 0; ring_loop < CE_state->src_ring->nentries;
-	     ring_loop++) {
-		ce_desc = (struct CE_src_desc *)
-			  ((char *)CE_state->src_ring->base_addr_owner_space +
-			   ring_loop * (sizeof(struct CE_src_desc)));
-		CE_IPA_RING_INIT(ce_desc);
-	}
-
-	/* Get BAR address */
-	hif_read_phy_mem_base(CE_state->scn, &phy_mem_base);
-
-	*ce_sr_base_paddr = CE_state->src_ring->base_addr_CE_space;
-	*ce_sr_ring_size = (uint32_t) (CE_state->src_ring->nentries *
-		sizeof(struct CE_src_desc));
-	*ce_reg_paddr = phy_mem_base + CE_BASE_ADDRESS(CE_state->id) +
-			SR_WR_INDEX_ADDRESS;
-	return;
-}
-#endif /* IPA_OFFLOAD */
-

core/hif/src/ce/ce_tasklet.c

@@ -1,411 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include <osdep.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/if_arp.h>
-#include "a_types.h"
-#include "athdefs.h"
-#include "cdf_lock.h"
-#include "cdf_types.h"
-#include "cdf_status.h"
-#include "cds_api.h"
-#include "regtable.h"
-#include "hif.h"
-#include "hif_io32.h"
-#include "ce_main.h"
-#include "ce_api.h"
-#include "ce_reg.h"
-#include "ce_internal.h"
-#ifdef CONFIG_CNSS
-#include <net/cnss.h>
-#ifdef HIF_PCI
-#include "icnss_stub.h"
-#else
-#include <soc/qcom/icnss.h>
-#endif /* HIF_PCI */
-#endif
-#include "hif_debug.h"
-#include "hif_napi.h"
-
-
-/**
- * ce_irq_status() - read CE IRQ status
- * @scn: struct ol_softc
- * @ce_id: ce_id
- * @host_status: host_status
- *
- * Return: IRQ status
- */
-static inline void ce_irq_status(struct ol_softc *scn,
-	int ce_id, uint32_t *host_status)
-{
-	uint32_t offset = HOST_IS_ADDRESS + CE_BASE_ADDRESS(ce_id);
-
-	*host_status = hif_read32_mb(scn->mem + offset);
-}
-
-/**
- * reschedule_ce_tasklet_work_handler() - reschedule work
- * @ce_id: ce_id
- *
- * Return: N/A
- */
-static void reschedule_ce_tasklet_work_handler(int ce_id)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct HIF_CE_state *hif_ce_state;
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: tasklet scn is null", __func__);
-		return;
-	}
-	hif_ce_state = (struct HIF_CE_state *)scn->hif_hdl;
-
-	if (scn->hif_init_done == false) {
-		HIF_ERROR("%s: wlan driver is unloaded", __func__);
-		return;
-	}
-	tasklet_schedule(&hif_ce_state->tasklets[ce_id].intr_tq);
-	return;
-}
-
-/**
- * struct tasklet_work
- *
- * @id: ce_id
- * @work: work
- */
-struct tasklet_work {
-	enum ce_id_type id;
-	struct work_struct work;
-};
-
-static struct tasklet_work tasklet_workers[CE_ID_MAX];
-static bool work_initialized;
-
-/**
- * work_handler() - work_handler
- * @work: struct work_struct
- *
- * Return: N/A
- */
-static void work_handler(struct work_struct *work)
-{
-	struct tasklet_work *tmp;
-
-	tmp = container_of(work, struct tasklet_work, work);
-	reschedule_ce_tasklet_work_handler(tmp->id);
-}
-
-/**
- * init_tasklet_work() - init_tasklet_work
- * @work: struct work_struct
- * @work_handler: work_handler
- *
- * Return: N/A
- */
-#ifdef CONFIG_CNSS
-static void init_tasklet_work(struct work_struct *work,
-	work_func_t work_handler)
-{
-	cnss_init_work(work, work_handler);
-}
-#else
-static void init_tasklet_work(struct work_struct *work,
-	work_func_t work_handler)
-{
-	INIT_WORK(work, work_handler);
-}
-#endif
-
-/**
- * init_tasklet_workers() - init_tasklet_workers
- *
- * Return: N/A
- */
-void init_tasklet_workers(void)
-{
-	uint32_t id;
-
-	for (id = 0; id < CE_ID_MAX; id++) {
-		tasklet_workers[id].id = id;
-		init_tasklet_work(&tasklet_workers[id].work, work_handler);
-	}
-	work_initialized = true;
-}
-
-#ifdef CONFIG_SLUB_DEBUG_ON
-/**
- * ce_schedule_tasklet() - schedule ce tasklet
- * @tasklet_entry: struct ce_tasklet_entry
- *
- * Return: N/A
- */
-static inline void ce_schedule_tasklet(struct ce_tasklet_entry *tasklet_entry)
-{
-	if (work_initialized && (tasklet_entry->ce_id < CE_ID_MAX))
-		schedule_work(&tasklet_workers[tasklet_entry->ce_id].work);
-	else
-		HIF_ERROR("%s: work_initialized = %d, ce_id = %d",
-			__func__, work_initialized, tasklet_entry->ce_id);
-}
-#else
-/**
- * ce_schedule_tasklet() - schedule ce tasklet
- * @tasklet_entry: struct ce_tasklet_entry
- *
- * Return: N/A
- */
-static inline void ce_schedule_tasklet(struct ce_tasklet_entry *tasklet_entry)
-{
-	tasklet_schedule(&tasklet_entry->intr_tq);
-}
-#endif
-
-/**
- * ce_tasklet() - ce_tasklet
- * @data: data
- *
- * Return: N/A
- */
-static void ce_tasklet(unsigned long data)
-{
-	struct ce_tasklet_entry *tasklet_entry =
-		(struct ce_tasklet_entry *)data;
-	struct HIF_CE_state *hif_ce_state = tasklet_entry->hif_ce_state;
-	struct ol_softc *scn = hif_ce_state->scn;
-	struct CE_state *CE_state = scn->ce_id_to_state[tasklet_entry->ce_id];
-
-	hif_record_ce_desc_event(tasklet_entry->ce_id, HIF_CE_TASKLET_ENTRY,
-			NULL, NULL, 0);
-
-	if (cdf_atomic_read(&scn->link_suspended)) {
-		HIF_ERROR("%s: ce %d tasklet fired after link suspend.",
-				__func__, tasklet_entry->ce_id);
-		CDF_BUG(0);
-	}
-
-	ce_per_engine_service(scn, tasklet_entry->ce_id);
-
-	if (CE_state->lro_flush_cb != NULL) {
-		CE_state->lro_flush_cb(CE_state->lro_data);
-	}
-
-	if (ce_check_rx_pending(scn, tasklet_entry->ce_id)) {
-		/*
-		 * There are frames pending, schedule tasklet to process them.
-		 * Enable the interrupt only when there is no pending frames in
-		 * any of the Copy Engine pipes.
-		 */
-		hif_record_ce_desc_event(tasklet_entry->ce_id,
-				HIF_CE_TASKLET_RESCHEDULE, NULL, NULL, 0);
-		ce_schedule_tasklet(tasklet_entry);
-		return;
-	}
-
-	if (scn->target_status != OL_TRGET_STATUS_RESET)
-		ce_irq_enable(scn, tasklet_entry->ce_id);
-
-	hif_record_ce_desc_event(tasklet_entry->ce_id, HIF_CE_TASKLET_EXIT,
-			NULL, NULL, 0);
-
-	cdf_atomic_dec(&scn->active_tasklet_cnt);
-}
-/**
- * ce_tasklet_init() - ce_tasklet_init
- * @hif_ce_state: hif_ce_state
- * @mask: mask
- *
- * Return: N/A
- */
-void ce_tasklet_init(struct HIF_CE_state *hif_ce_state, uint32_t mask)
-{
-	int i;
-
-	for (i = 0; i < CE_COUNT_MAX; i++) {
-		if (mask & (1 << i)) {
-			hif_ce_state->tasklets[i].ce_id = i;
-			hif_ce_state->tasklets[i].inited = true;
-			hif_ce_state->tasklets[i].hif_ce_state = hif_ce_state;
-			tasklet_init(&hif_ce_state->tasklets[i].intr_tq,
-				ce_tasklet,
-				(unsigned long)&hif_ce_state->tasklets[i]);
-		}
-	}
-}
-/**
- * ce_tasklet_kill() - ce_tasklet_kill
- * @hif_ce_state: hif_ce_state
- *
- * Return: N/A
- */
-void ce_tasklet_kill(struct HIF_CE_state *hif_ce_state)
-{
-	int i;
-	struct ol_softc *scn = hif_ce_state->scn;
-
-	for (i = 0; i < CE_COUNT_MAX; i++)
-		if (hif_ce_state->tasklets[i].inited) {
-			tasklet_kill(&hif_ce_state->tasklets[i].intr_tq);
-			hif_ce_state->tasklets[i].inited = false;
-		}
-	cdf_atomic_set(&scn->active_tasklet_cnt, 0);
-}
-/**
- * ce_irq_handler() - ce_irq_handler
- * @ce_id: ce_id
- * @context: context
- *
- * Return: N/A
- */
-static irqreturn_t ce_irq_handler(int irq, void *context)
-{
-	struct ce_tasklet_entry *tasklet_entry = context;
-	struct HIF_CE_state *hif_ce_state = tasklet_entry->hif_ce_state;
-	struct ol_softc *scn = hif_ce_state->scn;
-	uint32_t host_status;
-	int ce_id = icnss_get_ce_id(irq);
-
-	if (tasklet_entry->ce_id != ce_id) {
-		HIF_ERROR("%s: ce_id (expect %d, received %d) does not match",
-			  __func__, tasklet_entry->ce_id, ce_id);
-		return IRQ_NONE;
-	}
-	if (unlikely(ce_id >= CE_COUNT_MAX)) {
-		HIF_ERROR("%s: ce_id=%d > CE_COUNT_MAX=%d",
-			  __func__, tasklet_entry->ce_id, CE_COUNT_MAX);
-		return IRQ_NONE;
-	}
-#ifndef HIF_PCI
-	disable_irq_nosync(irq);
-#endif
-	ce_irq_disable(scn, ce_id);
-	ce_irq_status(scn, ce_id, &host_status);
-	cdf_atomic_inc(&scn->active_tasklet_cnt);
-	hif_record_ce_desc_event(ce_id, HIF_IRQ_EVENT, NULL, NULL, 0);
-	if (hif_napi_enabled(scn, ce_id))
-		hif_napi_schedule(scn, ce_id);
-	else
-		tasklet_schedule(&tasklet_entry->intr_tq);
-
-	return IRQ_HANDLED;
-}
-
-/**
- * const char *ce_name
- *
- * @ce_name: ce_name
- */
-const char *ce_name[ICNSS_MAX_IRQ_REGISTRATIONS] = {
-	"WLAN_CE_0",
-	"WLAN_CE_1",
-	"WLAN_CE_2",
-	"WLAN_CE_3",
-	"WLAN_CE_4",
-	"WLAN_CE_5",
-	"WLAN_CE_6",
-	"WLAN_CE_7",
-	"WLAN_CE_8",
-	"WLAN_CE_9",
-	"WLAN_CE_10",
-	"WLAN_CE_11",
-};
-/**
- * ce_unregister_irq() - ce_unregister_irq
- * @hif_ce_state: hif_ce_state copy engine device handle
- * @mask: which coppy engines to unregister for.
- *
- * Unregisters copy engine irqs matching mask.  If a 1 is set at bit x,
- * unregister for copy engine x.
- *
- * Return: CDF_STATUS
- */
-CDF_STATUS ce_unregister_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
-{
-	int id;
-	int ret;
-
-	if (hif_ce_state == NULL) {
-		HIF_WARN("%s: hif_ce_state = NULL", __func__);
-		return CDF_STATUS_SUCCESS;
-	}
-	for (id = 0; id < CE_COUNT_MAX; id++) {
-		if ((mask & (1 << id)) && hif_ce_state->tasklets[id].inited) {
-			ret = icnss_ce_free_irq(id,
-					&hif_ce_state->tasklets[id]);
-			if (ret < 0)
-				HIF_ERROR(
-					"%s: icnss_unregister_irq error - ce_id = %d, ret = %d",
-					__func__, id, ret);
-		}
-	}
-	return CDF_STATUS_SUCCESS;
-}
-/**
- * ce_register_irq() - ce_register_irq
- * @hif_ce_state: hif_ce_state
- * @mask: which coppy engines to unregister for.
- *
- * Registers copy engine irqs matching mask.  If a 1 is set at bit x,
- * Register for copy engine x.
- *
- * Return: CDF_STATUS
- */
-CDF_STATUS ce_register_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
-{
-	int id;
-	int ret;
-	unsigned long irqflags = IRQF_TRIGGER_RISING;
-	uint32_t done_mask = 0;
-
-	for (id = 0; id < CE_COUNT_MAX; id++) {
-		if ((mask & (1 << id)) && hif_ce_state->tasklets[id].inited) {
-			ret = icnss_ce_request_irq(id, ce_irq_handler,
-				irqflags, ce_name[id],
-				&hif_ce_state->tasklets[id]);
-			if (ret) {
-				HIF_ERROR(
-					"%s: cannot register CE %d irq handler, ret = %d",
-					__func__, id, ret);
-				ce_unregister_irq(hif_ce_state, done_mask);
-				return CDF_STATUS_E_FAULT;
-			} else {
-				done_mask |= 1 << id;
-			}
-		}
-	}
-
-#ifndef HIF_PCI
-	/* move to hif_configure_irq */
-	ce_enable_irq_in_group_reg(hif_ce_state->scn, done_mask);
-#endif
-
-	return CDF_STATUS_SUCCESS;
-}

core/hif/src/ce/ce_tasklet.h

@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __CE_TASKLET_H__
-#define __CE_TASKLET_H__
-#include "ce_main.h"
-void init_tasklet_workers(void);
-void ce_tasklet_init(struct HIF_CE_state *hif_ce_state, uint32_t mask);
-void ce_tasklet_kill(struct HIF_CE_state *hif_ce_state);
-CDF_STATUS ce_register_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask);
-CDF_STATUS ce_unregister_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask);
-#endif /* __CE_TASKLET_H__ */

core/hif/src/hif_debug.h

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef __HIF_DEBUG_H__
-#define __HIF_DEBUG_H__
-#include "cdf_trace.h"
-
-#define HIF_ERROR(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_ERROR, ## args)
-#define HIF_WARN(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_WARN, ## args)
-#define HIF_INFO(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO, ## args)
-#define HIF_INFO_HI(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO_HIGH, ## args)
-#define HIF_INFO_MED(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO_MED, ## args)
-#define HIF_INFO_LO(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_INFO_LOW, ## args)
-#define HIF_TRACE(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_ERROR, ## args)
-#define HIF_DBG(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_DEBUG, ## args)
-#endif /* __HIF_DEBUG_H__ */

core/hif/src/hif_hw_version.h

@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2012-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-
-#ifndef HIF_HW_VERSION_H
-#define HIF_HW_VERSION_H
-
-#define AR6320_REV1_VERSION             0x5000000
-#define AR6320_REV1_1_VERSION           0x5000001
-#define AR6320_REV1_3_VERSION           0x5000003
-#define AR6320_REV2_1_VERSION           0x5010000
-#define AR6320_REV3_VERSION             0x5020000
-#define AR6320_REV3_2_VERSION           0x5030000
-
-struct qwlan_hw {
-	u32 id;
-	u32 subid;
-	const char *name;
-};
-
-static const struct qwlan_hw qwlan_hw_list[] = {
-	{
-		.id = AR6320_REV1_VERSION,
-		.subid = 0,
-		.name = "QCA6174_REV1",
-	},
-	{
-		.id = AR6320_REV1_1_VERSION,
-		.subid = 0x1,
-		.name = "QCA6174_REV1_1",
-	},
-	{
-		.id = AR6320_REV1_3_VERSION,
-		.subid = 0x2,
-		.name = "QCA6174_REV1_3",
-	},
-	{
-		.id = AR6320_REV2_1_VERSION,
-		.subid = 0x4,
-		.name = "QCA6174_REV2_1",
-	},
-	{
-		.id = AR6320_REV2_1_VERSION,
-		.subid = 0x5,
-		.name = "QCA6174_REV2_2",
-	},
-	{
-		.id = AR6320_REV3_VERSION,
-		.subid = 0x6,
-		.name = "QCA6174_REV2.3",
-	},
-	{
-		.id = AR6320_REV3_VERSION,
-		.subid = 0x8,
-		.name = "QCA6174_REV3",
-	},
-	{
-		.id = AR6320_REV3_VERSION,
-		.subid = 0x9,
-		.name = "QCA6174_REV3_1",
-	},
-	{
-		.id = AR6320_REV3_2_VERSION,
-		.subid = 0xA,
-		.name = "AR6320_REV3_2_VERSION",
-	}
-};
-
-#endif /* HIF_HW_VERSION_H */

core/hif/src/hif_io32.h

@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __HIF_IO32_H__
-#define __HIF_IO32_H__
-
-#include <linux/io.h>
-#include "ol_if_athvar.h"
-#include "hif.h"
-#ifdef HIF_PCI
-#include "hif_io32_pci.h"
-#else
-#include "hif_io32_snoc.h"
-#endif /* HIF_PCI */
-#endif /* __HIF_IO32_H__ */

core/hif/src/hif_main.c

@@ -1,881 +0,0 @@
-/*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include <osdep.h>
-#include "a_types.h"
-#include "athdefs.h"
-#include "osapi_linux.h"
-#include "targcfg.h"
-#include "cdf_lock.h"
-#include "cdf_status.h"
-#include <cdf_atomic.h>         /* cdf_atomic_read */
-#include <targaddrs.h>
-#include <bmi_msg.h>
-#include "hif_io32.h"
-#include <hif.h>
-#include <htc_services.h>
-#include "regtable.h"
-#define ATH_MODULE_NAME hif
-#include <a_debug.h>
-#include "hif_main.h"
-#include "hif_hw_version.h"
-#include "ce_api.h"
-#include "ce_tasklet.h"
-#include "cdf_trace.h"
-#include "cdf_status.h"
-#include "cds_api.h"
-#ifdef CONFIG_CNSS
-#include <net/cnss.h>
-#endif
-#include "epping_main.h"
-#include "hif_debug.h"
-#include "mp_dev.h"
-#ifdef HIF_PCI
-#include "icnss_stub.h"
-#else
-#include <soc/qcom/icnss.h>
-#endif
-
-#ifndef REMOVE_PKT_LOG
-#include "pktlog_ac.h"
-#endif
-
-#include "cds_concurrency.h"
-
-#define AGC_DUMP         1
-#define CHANINFO_DUMP    2
-#define BB_WATCHDOG_DUMP 3
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-#define PCIE_ACCESS_DUMP 4
-#endif
-
-void hif_dump(struct ol_softc *scn, uint8_t cmd_id, bool start)
-{
-	switch (cmd_id) {
-	case AGC_DUMP:
-		if (start)
-			priv_start_agc(scn);
-		else
-			priv_dump_agc(scn);
-		break;
-
-	case CHANINFO_DUMP:
-		if (start)
-			priv_start_cap_chaninfo(scn);
-		else
-			priv_dump_chaninfo(scn);
-		break;
-
-	case BB_WATCHDOG_DUMP:
-		priv_dump_bbwatchdog(scn);
-		break;
-
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-	case PCIE_ACCESS_DUMP:
-		hif_target_dump_access_log();
-		break;
-#endif
-	default:
-		HIF_ERROR("%s: Invalid htc dump command", __func__);
-		break;
-	}
-}
-
-/**
- * hif_shut_down_device() - hif_shut_down_device
- *
- * SThis fucntion shuts down the device
- *
- * @scn: ol_softc
- *
- * Return: void
- */
-void hif_shut_down_device(struct ol_softc *scn)
-{
-	if (scn && scn->hif_hdl) {
-		struct HIF_CE_state *hif_state =
-			(struct HIF_CE_state *)scn->hif_hdl;
-
-		hif_stop(scn);
-		cdf_mem_free(hif_state);
-		scn->hif_hdl = NULL;
-	}
-
-}
-
-
-
-/**
- * hif_cancel_deferred_target_sleep() - cancel deferred target sleep
- *
- * This function cancels the defered target sleep
- *
- * @scn: ol_softc
- *
- * Return: void
- */
-void hif_cancel_deferred_target_sleep(struct ol_softc *scn)
-{
-	hif_pci_cancel_deferred_target_sleep(scn);
-}
-
-/**
- * hif_get_target_id(): hif_get_target_id
- *
- * Return the virtual memory base address to the caller
- *
- * @scn: ol_softc
- *
- * Return: A_target_id_t
- */
-A_target_id_t hif_get_target_id(struct ol_softc *scn)
-{
-	return scn->mem;
-}
-
-/**
- * hif_set_target_sleep(): hif_set_target_sleep
- * @scn: scn
- * @sleep_ok: sleep_ok
- * @wait_for_it: wait
- *
- * Return: void
- */
-void hif_set_target_sleep(struct ol_softc *scn,
-		     bool sleep_ok, bool wait_for_it)
-{
-	hif_target_sleep_state_adjust(scn,
-				      sleep_ok, wait_for_it);
-}
-
-/**
- * hif_target_forced_awake(): hif_target_forced_awake
- * @scn: scn
- *
- * Return: bool
- */
-bool hif_target_forced_awake(struct ol_softc *scn)
-{
-	A_target_id_t addr = scn->mem;
-	bool awake;
-	bool forced_awake;
-
-	awake = hif_targ_is_awake(scn, addr);
-
-	forced_awake =
-		!!(hif_read32_mb
-			   (addr + PCIE_LOCAL_BASE_ADDRESS +
-			   PCIE_SOC_WAKE_ADDRESS) & PCIE_SOC_WAKE_V_MASK);
-
-	return awake && forced_awake;
-}
-
-
-static inline void hif_fw_event_handler(struct HIF_CE_state *hif_state)
-{
-	struct hif_msg_callbacks *msg_callbacks =
-		&hif_state->msg_callbacks_current;
-
-	if (!msg_callbacks->fwEventHandler)
-		return;
-
-	msg_callbacks->fwEventHandler(msg_callbacks->Context,
-			CDF_STATUS_E_FAILURE);
-}
-
-/**
- * hif_fw_interrupt_handler(): FW interrupt handler
- *
- * This function is the FW interrupt handlder
- *
- * @irq: irq number
- * @arg: the user pointer
- *
- * Return: bool
- */
-#ifndef QCA_WIFI_3_0
-irqreturn_t hif_fw_interrupt_handler(int irq, void *arg)
-{
-	struct ol_softc *scn = arg;
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	uint32_t fw_indicator_address, fw_indicator;
-
-	A_TARGET_ACCESS_BEGIN_RET(scn);
-
-	fw_indicator_address = hif_state->fw_indicator_address;
-	/* For sudden unplug this will return ~0 */
-	fw_indicator = A_TARGET_READ(scn, fw_indicator_address);
-
-	if ((fw_indicator != ~0) && (fw_indicator & FW_IND_EVENT_PENDING)) {
-		/* ACK: clear Target-side pending event */
-		A_TARGET_WRITE(scn, fw_indicator_address,
-			       fw_indicator & ~FW_IND_EVENT_PENDING);
-		A_TARGET_ACCESS_END_RET(scn);
-
-		if (hif_state->started) {
-			hif_fw_event_handler(hif_state);
-		} else {
-			/*
-			 * Probable Target failure before we're prepared
-			 * to handle it.  Generally unexpected.
-			 */
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-				("%s: Early firmware event indicated\n",
-				 __func__));
-		}
-	} else {
-		A_TARGET_ACCESS_END_RET(scn);
-	}
-
-	return ATH_ISR_SCHED;
-}
-#else
-irqreturn_t hif_fw_interrupt_handler(int irq, void *arg)
-{
-	return ATH_ISR_SCHED;
-}
-#endif /* #ifdef QCA_WIFI_3_0 */
-
-/**
- * hif_get_targetdef(): hif_get_targetdef
- * @scn: scn
- *
- * Return: void *
- */
-void *hif_get_targetdef(struct ol_softc *scn)
-{
-	return scn->targetdef;
-}
-
-/**
- * hif_vote_link_down(): unvote for link up
- *
- * Call hif_vote_link_down to release a previous request made using
- * hif_vote_link_up. A hif_vote_link_down call should only be made
- * after a corresponding hif_vote_link_up, otherwise you could be
- * negating a vote from another source. When no votes are present
- * hif will not guarantee the linkstate after hif_bus_suspend.
- *
- * SYNCHRONIZE WITH hif_vote_link_up by only calling in MC thread
- * and initialization deinitialization sequencences.
- *
- * Return: n/a
- */
-void hif_vote_link_down(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	CDF_BUG(scn);
-
-	scn->linkstate_vote--;
-	if (scn->linkstate_vote == 0)
-		hif_bus_prevent_linkdown(scn, false);
-}
-
-/**
- * hif_vote_link_up(): vote to prevent bus from suspending
- *
- * Makes hif guarantee that fw can message the host normally
- * durring suspend.
- *
- * SYNCHRONIZE WITH hif_vote_link_up by only calling in MC thread
- * and initialization deinitialization sequencences.
- *
- * Return: n/a
- */
-void hif_vote_link_up(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	CDF_BUG(scn);
-
-	scn->linkstate_vote++;
-	if (scn->linkstate_vote == 1)
-		hif_bus_prevent_linkdown(scn, true);
-}
-
-/**
- * hif_can_suspend_link(): query if hif is permitted to suspend the link
- *
- * Hif will ensure that the link won't be suspended if the upperlayers
- * don't want it to.
- *
- * SYNCHRONIZATION: MC thread is stopped before bus suspend thus
- * we don't need extra locking to ensure votes dont change while
- * we are in the process of suspending or resuming.
- *
- * Return: false if hif will guarantee link up durring suspend.
- */
-bool hif_can_suspend_link(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	CDF_BUG(scn);
-
-	return scn->linkstate_vote == 0;
-}
-
-/**
- * hif_hia_item_address(): hif_hia_item_address
- * @target_type: target_type
- * @item_offset: item_offset
- *
- * Return: n/a
- */
-uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset)
-{
-	switch (target_type) {
-	case TARGET_TYPE_AR6002:
-		return AR6002_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_AR6003:
-		return AR6003_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_AR6004:
-		return AR6004_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_AR6006:
-		return AR6006_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_AR9888:
-		return AR9888_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_AR6320:
-	case TARGET_TYPE_AR6320V2:
-		return AR6320_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_QCA6180:
-		return QCA6180_HOST_INTEREST_ADDRESS + item_offset;
-	case TARGET_TYPE_ADRASTEA:
-		/* ADRASTEA doesn't have a host interest address */
-		ASSERT(0);
-		return 0;
-	default:
-		ASSERT(0);
-		return 0;
-	}
-}
-
-/**
- * hif_max_num_receives_reached() - check max receive is reached
- * @count: unsigned int.
- *
- * Output check status as bool
- *
- * Return: bool
- */
-bool hif_max_num_receives_reached(unsigned int count)
-{
-	if (WLAN_IS_EPPING_ENABLED(cds_get_conparam()))
-		return count > 120;
-	else
-		return count > MAX_NUM_OF_RECEIVES;
-}
-
-/**
- * init_buffer_count() - initial buffer count
- * @maxSize: cdf_size_t
- *
- * routine to modify the initial buffer count to be allocated on an os
- * platform basis. Platform owner will need to modify this as needed
- *
- * Return: cdf_size_t
- */
-cdf_size_t init_buffer_count(cdf_size_t maxSize)
-{
-	return maxSize;
-}
-
-/**
- * hif_init_cdf_ctx(): hif_init_cdf_ctx
- * @hif_ctx: hif_ctx
- *
- * Return: int
- */
-int hif_init_cdf_ctx(void *hif_ctx)
-{
-	cdf_device_t cdf_ctx;
-	struct ol_softc *scn = (struct ol_softc *)hif_ctx;
-
-	cdf_ctx = cds_get_context(CDF_MODULE_ID_CDF_DEVICE);
-	if (!cdf_ctx) {
-		HIF_ERROR("%s: CDF is NULL", __func__);
-		return -ENOMEM;
-	}
-
-	cdf_ctx->drv = &scn->aps_osdev;
-	cdf_ctx->drv_hdl = scn->aps_osdev.bdev;
-	cdf_ctx->dev = scn->aps_osdev.device;
-	scn->cdf_dev = cdf_ctx;
-	return 0;
-}
-
-/**
- * hif_deinit_cdf_ctx(): hif_deinit_cdf_ctx
- * @hif_ctx: hif_ctx
- *
- * Return: void
- */
-void hif_deinit_cdf_ctx(void *hif_ctx)
-{
-	struct ol_softc *scn = (struct ol_softc *)hif_ctx;
-
-	if (scn == NULL || !scn->cdf_dev)
-		return;
-	scn->cdf_dev = NULL;
-}
-
-/**
- * hif_save_htc_htt_config_endpoint():
- * hif_save_htc_htt_config_endpoint
- * @htc_endpoint: htc_endpoint
- *
- * Return: void
- */
-void hif_save_htc_htt_config_endpoint(int htc_endpoint)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-
-	if (!scn) {
-		HIF_ERROR("%s: error: scn or scn->hif_sc is NULL!",
-		       __func__);
-		return;
-	}
-
-	scn->htc_endpoint = htc_endpoint;
-}
-
-/**
- * hif_get_hw_name(): get a human readable name for the hardware
- *
- * Return: human readible name for the underlying wifi hardware.
- */
-const char *hif_get_hw_name(struct ol_softc *scn)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(qwlan_hw_list); i++) {
-		if (scn->target_version == qwlan_hw_list[i].id &&
-		    scn->target_revision == qwlan_hw_list[i].subid) {
-			return qwlan_hw_list[i].name;
-		}
-	}
-
-	return "Unknown Device";
-}
-
-/**
- * hif_get_hw_info(): hif_get_hw_info
- * @scn: scn
- * @version: version
- * @revision: revision
- *
- * Return: n/a
- */
-void hif_get_hw_info(void *scn, u32 *version, u32 *revision,
-			const char **target_name)
-{
-	*version = ((struct ol_softc *)scn)->target_version;
-	*revision = ((struct ol_softc *)scn)->target_revision;
-	*target_name = hif_get_hw_name((struct ol_softc *)scn);
-}
-
-/**
- * hif_set_fw_info(): set the target_fw_version
- * @scn: scn
- * @target_fw_version: target_fw_version
- *
- * Return: n/a
- */
-void hif_set_fw_info(void *scn, uint32_t target_fw_version)
-{
-	((struct ol_softc *)scn)->target_fw_version = target_fw_version;
-}
-
-/**
- * hif_open(): hif_open
- *
- * Return: scn
- */
-CDF_STATUS hif_open(enum ath_hal_bus_type bus_type)
-{
-	struct ol_softc *scn;
-	v_CONTEXT_t cds_context;
-	CDF_STATUS status = CDF_STATUS_SUCCESS;
-
-	cds_context = cds_get_global_context();
-	status = cds_alloc_context(cds_context, CDF_MODULE_ID_HIF,
-				(void **)&scn, sizeof(*scn));
-	if (status != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: cannot alloc ol_sc", __func__);
-		return status;
-	}
-
-	cdf_mem_zero(scn, sizeof(*scn));
-	scn->enableuartprint = 0;
-	scn->enablefwlog = 0;
-	scn->max_no_of_peers = 1;
-	scn->pkt_log_init = false;
-	cdf_atomic_init(&scn->wow_done);
-	cdf_atomic_init(&scn->active_tasklet_cnt);
-	cdf_atomic_init(&scn->link_suspended);
-	cdf_atomic_init(&scn->tasklet_from_intr);
-	init_waitqueue_head(&scn->aps_osdev.event_queue);
-	scn->linkstate_vote = 0;
-
-	status = hif_bus_open(scn, bus_type);
-	if (status != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: hif_bus_open error = %d, bus_type = %d",
-				  __func__, status, bus_type);
-		cds_free_context(cds_context, CDF_MODULE_ID_HIF, scn);
-	}
-
-	return status;
-}
-
-/**
- * hif_close(): hif_close
- * @hif_ctx: hif_ctx
- *
- * Return: n/a
- */
-void hif_close(void *hif_ctx)
-{
-	struct ol_softc *scn = hif_ctx;
-
-	if (scn == NULL) {
-		HIF_ERROR("%s: ol_softc is NULL", __func__);
-		return;
-	}
-
-	if (scn->athdiag_procfs_inited) {
-		athdiag_procfs_remove();
-		scn->athdiag_procfs_inited = false;
-	}
-
-	if (scn->hif_hdl) {
-		cdf_mem_free(scn->hif_hdl);
-		scn->hif_hdl = NULL;
-	}
-	hif_bus_close(scn);
-	cds_free_context(cds_get_global_context(),
-		CDF_MODULE_ID_HIF, hif_ctx);
-}
-
-/**
- * hif_enable(): hif_enable
- * @hif_ctx: hif_ctx
- * @dev: dev
- * @bdev: bus dev
- * @bid: bus ID
- * @bus_type: bus type
- * @type: enable type
- *
- * Return: CDF_STATUS
- */
-CDF_STATUS hif_enable(void *hif_ctx, struct device *dev,
-					  void *bdev, const hif_bus_id *bid,
-					  enum ath_hal_bus_type bus_type,
-					  enum hif_enable_type type)
-{
-	CDF_STATUS status;
-	struct ol_softc *scn = hif_ctx;
-
-	if (scn == NULL) {
-		HIF_ERROR("%s: hif_ctx = NULL", __func__);
-		return CDF_STATUS_E_NULL_VALUE;
-	}
-
-	status = hif_enable_bus(scn, dev, bdev, bid, type);
-	if (status != CDF_STATUS_SUCCESS) {
-		HIF_ERROR("%s: hif_enable_bus error = %d",
-				  __func__, status);
-		return status;
-	}
-
-	if (ADRASTEA_BU)
-		hif_vote_link_up();
-
-	if (hif_config_ce(scn)) {
-		HIF_ERROR("%s: Target probe failed.", __func__);
-		hif_disable_bus(scn->aps_osdev.bdev);
-		status = CDF_STATUS_E_FAILURE;
-		return status;
-	}
-	/*
-	 * Flag to avoid potential unallocated memory access from MSI
-	 * interrupt handler which could get scheduled as soon as MSI
-	 * is enabled, i.e to take care of the race due to the order
-	 * in where MSI is enabled before the memory, that will be
-	 * in interrupt handlers, is allocated.
-	 */
-
-#ifdef HIF_PCI
-	status = hif_configure_irq(scn->hif_sc);
-	if (status < 0) {
-		HIF_ERROR("%s: ERROR - configure_IRQ_and_CE failed, status = %d",
-			   __func__, status);
-		return CDF_STATUS_E_FAILURE;
-	}
-#endif
-
-	scn->hif_init_done = true;
-
-	HIF_TRACE("%s: X OK", __func__);
-
-	return CDF_STATUS_SUCCESS;
-}
-
-/**
- * hif_pktlogmod_exit(): hif_pktlogmod_exit
- * @scn: scn
- *
- * Return: n/a
- */
-#ifndef REMOVE_PKT_LOG
-void hif_pktlogmod_exit(void *hif_ctx)
-{
-	struct ol_softc *scn = hif_ctx;
-
-	if (scn && cds_get_conparam() != CDF_GLOBAL_FTM_MODE &&
-	    !WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && scn->pkt_log_init) {
-		pktlogmod_exit(scn);
-		scn->pkt_log_init = false;
-	}
-}
-#else
-void hif_pktlogmod_exit(void *hif_ctx)
-{
-}
-#endif
-
-/**
- * hif_wlan_disable(): call the platform driver to disable wlan
- *
- * This function passes the con_mode to platform driver to disable
- * wlan.
- *
- * Return: void
- */
-void hif_wlan_disable(void)
-{
-	enum icnss_driver_mode mode;
-	uint32_t con_mode = cds_get_conparam();
-
-	if (CDF_GLOBAL_FTM_MODE == con_mode)
-		mode = ICNSS_FTM;
-	else if (WLAN_IS_EPPING_ENABLED(cds_get_conparam()))
-		mode = ICNSS_EPPING;
-	else
-		mode = ICNSS_MISSION;
-
-	icnss_wlan_disable(mode);
-}
-
-void hif_disable(void *hif_ctx, enum hif_disable_type type)
-{
-	struct ol_softc *scn = hif_ctx;
-
-	if (!scn)
-		return;
-
-	hif_nointrs(scn);
-	if (scn->hif_init_done == false)
-		hif_shut_down_device(scn);
-	else
-		hif_stop(scn);
-
-	if (ADRASTEA_BU)
-		hif_vote_link_down();
-
-	if (scn->aps_osdev.bdev)
-		hif_disable_bus(scn->aps_osdev.bdev);
-
-	hif_wlan_disable();
-
-	scn->notice_send = false;
-
-	HIF_INFO("%s: X", __func__);
-}
-
-
-/**
- * hif_crash_shutdown_dump_bus_register() - dump bus registers
- * @hif_ctx: hif_ctx
- *
- * Return: n/a
- */
-#if defined(TARGET_RAMDUMP_AFTER_KERNEL_PANIC) \
-&& defined(HIF_PCI) && defined(DEBUG)
-
-static void hif_crash_shutdown_dump_bus_register(void *hif_ctx)
-{
-	struct ol_softc *scn = hif_ctx;
-
-	if (hif_check_soc_status(scn))
-		return;
-
-	if (hif_dump_registers(scn))
-		HIF_ERROR("Failed to dump bus registers!");
-}
-
-/**
- * hif_crash_shutdown(): hif_crash_shutdown
- *
- * This function is called by the platform driver to dump CE registers
- *
- * @hif_ctx: hif_ctx
- *
- * Return: n/a
- */
-void hif_crash_shutdown(void *hif_ctx)
-{
-	struct ol_softc *scn = hif_ctx;
-	struct HIF_CE_state *hif_state;
-
-	if (!scn)
-		return;
-
-	hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	if (!hif_state)
-		return;
-
-
-	if (OL_TRGET_STATUS_RESET == scn->target_status) {
-		HIF_INFO_MED("%s: Target is already asserted, ignore!",
-			    __func__);
-		return;
-	}
-
-	if (cds_is_load_or_unload_in_progress()) {
-		HIF_ERROR("%s: Load/unload is in progress, ignore!", __func__);
-		return;
-	}
-
-	hif_crash_shutdown_dump_bus_register(hif_ctx);
-
-	if (ol_copy_ramdump(scn))
-		goto out;
-
-	HIF_INFO_MED("%s: RAM dump collecting completed!", __func__);
-
-out:
-	return;
-}
-#else
-void hif_crash_shutdown(void *hif_ctx)
-{
-	HIF_INFO_MED("%s: Collecting target RAM dump disabled",
-		__func__);
-	return;
-}
-#endif /* TARGET_RAMDUMP_AFTER_KERNEL_PANIC */
-
-#ifdef QCA_WIFI_3_0
-/**
- * hif_check_fw_reg(): hif_check_fw_reg
- * @scn: scn
- * @state:
- *
- * Return: int
- */
-int hif_check_fw_reg(struct ol_softc *scn)
-{
-	return 0;
-}
-#endif
-
-#ifdef IPA_OFFLOAD
-/**
- * hif_read_phy_mem_base(): hif_read_phy_mem_base
- * @scn: scn
- * @phy_mem_base: physical mem base
- *
- * Return: n/a
- */
-void hif_read_phy_mem_base(struct ol_softc *scn, cdf_dma_addr_t *phy_mem_base)
-{
-	*phy_mem_base = scn->mem_pa;
-}
-#endif /* IPA_OFFLOAD */
-
-/**
- * hif_get_device_type(): hif_get_device_type
- * @device_id: device_id
- * @revision_id: revision_id
- * @hif_type: returned hif_type
- * @target_type: returned target_type
- *
- * Return: int
- */
-int hif_get_device_type(uint32_t device_id,
-			uint32_t revision_id,
-			uint32_t *hif_type, uint32_t *target_type)
-{
-	int ret = 0;
-
-	switch (device_id) {
-#ifdef QCA_WIFI_3_0_ADRASTEA
-	case ADRASTEA_DEVICE_ID:
-	case ADRASTEA_DEVICE_ID_P2_E12:
-
-		*hif_type = HIF_TYPE_ADRASTEA;
-		*target_type = TARGET_TYPE_ADRASTEA;
-		break;
-#else
-	case QCA6180_DEVICE_ID:
-		*hif_type = HIF_TYPE_QCA6180;
-		*target_type = TARGET_TYPE_QCA6180;
-		break;
-#endif
-
-	case AR9888_DEVICE_ID:
-		*hif_type = HIF_TYPE_AR9888;
-		*target_type = TARGET_TYPE_AR9888;
-		break;
-
-	case AR6320_DEVICE_ID:
-		switch (revision_id) {
-		case AR6320_FW_1_1:
-		case AR6320_FW_1_3:
-			*hif_type = HIF_TYPE_AR6320;
-			*target_type = TARGET_TYPE_AR6320;
-			break;
-
-		case AR6320_FW_2_0:
-		case AR6320_FW_3_0:
-		case AR6320_FW_3_2:
-			*hif_type = HIF_TYPE_AR6320V2;
-			*target_type = TARGET_TYPE_AR6320V2;
-			break;
-
-		default:
-			HIF_ERROR("%s: error - dev_id = 0x%x, rev_id = 0x%x",
-				   __func__, device_id, revision_id);
-			ret = -ENODEV;
-			goto end;
-		}
-		break;
-
-	default:
-		HIF_ERROR("%s: Unsupported device ID!", __func__);
-		ret = -ENODEV;
-		break;
-	}
-end:
-	return ret;
-}

core/hif/src/hif_main.h

@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-/*
- * NB: Inappropriate references to "HTC" are used in this (and other)
- * HIF implementations.  HTC is typically the calling layer, but it
- * theoretically could be some alternative.
- */
-
-/*
- * This holds all state needed to process a pending send/recv interrupt.
- * The information is saved here as soon as the interrupt occurs (thus
- * allowing the underlying CE to re-use the ring descriptor). The
- * information here is eventually processed by a completion processing
- * thread.
- */
-
-#ifndef __HIF_MAIN_H__
-#define __HIF_MAIN_H__
-
-#include <cdf_atomic.h>         /* cdf_atomic_read */
-#include "cdf_lock.h"
-#include "cepci.h"
-#include "hif.h"
-
-#define HIF_MIN_SLEEP_INACTIVITY_TIME_MS     50
-#define HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS 60
-
-/*
- * This macro implementation is exposed for efficiency only.
- * The implementation may change and callers should
- * consider the targid to be a completely opaque handle.
- */
-#define TARGID_TO_PCI_ADDR(targid) (*((A_target_id_t *)(targid)))
-
-A_target_id_t hif_get_target_id(struct ol_softc *scn);
-bool hif_target_forced_awake(struct ol_softc *scn);
-
-#ifdef QCA_WIFI_3_0
-#define DISABLE_L1SS_STATES 1
-#endif
-#ifdef CONFIG_SLUB_DEBUG_ON
-#define MAX_NUM_OF_RECEIVES 100 /* Maximum number of Rx buf to process before*
-				 * break out in SLUB debug builds */
-#elif defined(FEATURE_NAPI)
-#define MAX_NUM_OF_RECEIVES HIF_NAPI_MAX_RECEIVES
-#else /* no SLUBS, no NAPI */
-/* Maximum number of Rx buf to process before break out */
-#define MAX_NUM_OF_RECEIVES 1000
-#endif /* SLUB_DEBUG_ON / FEATURE_NAPI */
-
-#ifdef QCA_WIFI_3_0_ADRASTEA
-#define ADRASTEA_BU 1
-#else
-#define ADRASTEA_BU 0
-#endif
-
-#ifdef QCA_WIFI_3_0
-#define HAS_FW_INDICATOR 0
-#else
-#define HAS_FW_INDICATOR 1
-#endif
-
-
-#define AR9888_DEVICE_ID (0x003c)
-#define AR6320_DEVICE_ID (0x003e)
-#define AR6320_FW_1_1  (0x11)
-#define AR6320_FW_1_3  (0x13)
-#define AR6320_FW_2_0  (0x20)
-#define AR6320_FW_3_0  (0x30)
-#define AR6320_FW_3_2  (0x32)
-#define ADRASTEA_DEVICE_ID (0xabcd)
-#define ADRASTEA_DEVICE_ID_P2_E12 (0x7021)
-#if (defined(QVIT))
-#define QCA6180_DEVICE_ID (0xabcd)
-#else
-#define QCA6180_DEVICE_ID (0x041)
-#endif
-
-A_target_id_t hif_get_target_id(struct ol_softc *scn);
-void hif_dump_pipe_debug_count(struct ol_softc *scn);
-
-bool hif_max_num_receives_reached(unsigned int count);
-int hif_config_ce(hif_handle_t hif_hdl);
-int athdiag_procfs_init(void *scn);
-void athdiag_procfs_remove(void);
-/* routine to modify the initial buffer count to be allocated on an os
- * platform basis. Platform owner will need to modify this as needed
- */
-cdf_size_t init_buffer_count(cdf_size_t maxSize);
-
-irqreturn_t hif_fw_interrupt_handler(int irq, void *arg);
-int hif_get_target_type(struct ol_softc *ol_sc, struct device *dev,
-	void *bdev, const hif_bus_id *bid, uint32_t *hif_type,
-	uint32_t *target_type);
-int hif_get_device_type(uint32_t device_id,
-			uint32_t revision_id,
-			uint32_t *hif_type, uint32_t *target_type);
-/*These functions are exposed to HDD*/
-int hif_init_cdf_ctx(void *ol_sc);
-void hif_deinit_cdf_ctx(void *ol_sc);
-bool hif_targ_is_awake(struct ol_softc *scn, void *__iomem *mem);
-void hif_nointrs(struct ol_softc *scn);
-void hif_bus_close(struct ol_softc *ol_sc);
-CDF_STATUS hif_bus_open(struct ol_softc *ol_sc,
-	enum ath_hal_bus_type bus_type);
-CDF_STATUS hif_enable_bus(struct ol_softc *ol_sc, struct device *dev,
-	void *bdev, const hif_bus_id *bid, enum hif_enable_type type);
-void hif_disable_bus(void *bdev);
-void hif_bus_prevent_linkdown(struct ol_softc *scn, bool flag);
-
-#endif /* __HIF_MAIN_H__ */

core/hif/src/hif_napi.c

@@ -1,464 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-/**
- * DOC: hif_napi.c
- *
- * HIF NAPI interface implementation
- */
-
-#include <string.h> /* memset */
-
-#include <cds_api.h>
-#include <hif_napi.h>
-#include <hif_debug.h>
-#include <hif_io32.h>
-#include <ce_api.h>
-#include <ce_internal.h>
-
-enum napi_decision_vector {
-	HIF_NAPI_NOEVENT = 0,
-	HIF_NAPI_INITED  = 1,
-	HIF_NAPI_CONF_UP = 2
-};
-#define ENABLE_NAPI_MASK (HIF_NAPI_INITED | HIF_NAPI_CONF_UP)
-
-/**
- * hif_napi_create() - creates the NAPI structures for a given CE
- * @hif    : pointer to hif context
- * @pipe_id: the CE id on which the instance will be created
- * @poll   : poll function to be used for this NAPI instance
- * @budget : budget to be registered with the NAPI instance
- * @scale  : scale factor on the weight (to scaler budget to 1000)
- *
- * Description:
- *    Creates NAPI instances. This function is called
- *    unconditionally during initialization. It creates
- *    napi structures through the proper HTC/HIF calls.
- *    The structures are disabled on creation.
- *    Note that for each NAPI instance a separate dummy netdev is used
- *
- * Return:
- * < 0: error
- * = 0: <should never happen>
- * > 0: id of the created object (for multi-NAPI, number of objects created)
- */
-int hif_napi_create(struct ol_softc   *hif,
-		    uint8_t            pipe_id,
-		    int (*poll)(struct napi_struct *, int),
-		    int                budget,
-		    int                scale)
-{
-	struct qca_napi_data *napid;
-	struct qca_napi_info *napii;
-
-	NAPI_DEBUG("-->(pipe=%d, budget=%d, scale=%d)\n",
-		   pipe_id, budget, scale);
-	NAPI_DEBUG("hif->napi_data.state = 0x%08x\n",
-		   hif->napi_data.state);
-	NAPI_DEBUG("hif->napi_data.ce_map = 0x%08x\n",
-		   hif->napi_data.ce_map);
-
-	napid = &(hif->napi_data);
-	if (0 == (napid->state &  HIF_NAPI_INITED)) {
-		memset(napid, 0, sizeof(struct qca_napi_data));
-		mutex_init(&(napid->mutex));
-
-		init_dummy_netdev(&(napid->netdev));
-
-		napid->state |= HIF_NAPI_INITED;
-		HIF_INFO("%s: NAPI structures initialized\n", __func__);
-
-		NAPI_DEBUG("NAPI structures initialized\n");
-	}
-	napii = &(napid->napis[pipe_id]);
-	memset(napii, 0, sizeof(struct qca_napi_info));
-	napii->scale = scale;
-	napii->id    = NAPI_PIPE2ID(pipe_id);
-
-	NAPI_DEBUG("adding napi=%p to netdev=%p (poll=%p, bdgt=%d)\n",
-		   &(napii->napi), &(napid->netdev), poll, budget);
-	netif_napi_add(&(napid->netdev), &(napii->napi), poll, budget);
-
-	NAPI_DEBUG("after napi_add\n");
-	NAPI_DEBUG("napi=0x%p, netdev=0x%p\n",
-		   &(napii->napi), &(napid->netdev));
-	NAPI_DEBUG("napi.dev_list.prev=0x%p, next=0x%p\n",
-		   napii->napi.dev_list.prev, napii->napi.dev_list.next);
-	NAPI_DEBUG("dev.napi_list.prev=0x%p, next=0x%p\n",
-		   napid->netdev.napi_list.prev, napid->netdev.napi_list.next);
-
-	/* It is OK to change the state variable below without protection
-	 * as there should be no-one around yet
-	 */
-	napid->ce_map |= (0x01 << pipe_id);
-	HIF_INFO("%s: NAPI id %d created for pipe %d\n", __func__,
-		 napii->id, pipe_id);
-
-	NAPI_DEBUG("NAPI id %d created for pipe %d\n", napii->id, pipe_id);
-	NAPI_DEBUG("<--napi_id=%d]\n", napii->id);
-	return napii->id;
-}
-
-/**
- *
- * hif_napi_destroy() - destroys the NAPI structures for a given instance
- * @hif   : pointer to hif context
- * @ce_id : the CE id whose napi instance will be destroyed
- * @force : if set, will destroy even if entry is active (de-activates)
- *
- * Description:
- *    Destroy a given NAPI instance. This function is called
- *    unconditionally during cleanup.
- *    Refuses to destroy an entry of it is still enabled (unless force=1)
- *    Marks the whole napi_data invalid if all instances are destroyed.
- *
- * Return:
- * -EINVAL: specific entry has not been created
- * -EPERM : specific entry is still active
- * 0 <    : error
- * 0 =    : success
- */
-int hif_napi_destroy(struct ol_softc *hif,
-		     uint8_t          id,
-		     int              force)
-{
-	uint8_t ce = NAPI_ID2PIPE(id);
-	int rc = 0;
-
-	NAPI_DEBUG("-->(id=%d, force=%d)\n", id, force);
-
-	if (0 == (hif->napi_data.state & HIF_NAPI_INITED)) {
-		HIF_ERROR("%s: NAPI not initialized or entry %d not created\n",
-			  __func__, id);
-		rc = -EINVAL;
-	} else if (0 == (hif->napi_data.ce_map & (0x01 << ce))) {
-		HIF_ERROR("%s: NAPI instance %d (pipe %d) not created\n",
-			  __func__, id, ce);
-		rc = -EINVAL;
-	} else {
-		struct qca_napi_data *napid;
-		struct qca_napi_info *napii;
-
-		napid = &(hif->napi_data);
-		napii = &(napid->napis[ce]);
-
-		if (hif->napi_data.state == HIF_NAPI_CONF_UP) {
-			if (force) {
-				napi_disable(&(napii->napi));
-				HIF_INFO("%s: NAPI entry %d force disabled\n",
-					 __func__, id);
-				NAPI_DEBUG("NAPI %d force disabled\n", id);
-			} else {
-				HIF_ERROR("%s: Cannot destroy active NAPI %d\n",
-					  __func__, id);
-				rc = -EPERM;
-			}
-		}
-		if (0 == rc) {
-			NAPI_DEBUG("before napi_del\n");
-			NAPI_DEBUG("napi.dlist.prv=0x%p, next=0x%p\n",
-				  napii->napi.dev_list.prev,
-				  napii->napi.dev_list.next);
-			NAPI_DEBUG("dev.napi_l.prv=0x%p, next=0x%p\n",
-				   napid->netdev.napi_list.prev,
-				   napid->netdev.napi_list.next);
-
-			netif_napi_del(&(napii->napi));
-
-			napid->ce_map &= ~(0x01 << ce);
-			napii->scale  = 0;
-			HIF_INFO("%s: NAPI %d destroyed\n", __func__, id);
-
-			/* if there are no active instances and
-			 * if they are all destroyed,
-			 * set the whole structure to uninitialized state
-			 */
-			if (napid->ce_map == 0) {
-				/* hif->napi_data.state = 0; */
-				memset(napid,
-				       0, sizeof(struct qca_napi_data));
-				HIF_INFO("%s: no NAPI instances. Zapped.\n",
-					 __func__);
-			}
-		}
-	}
-
-	return rc;
-}
-
-/**
- *
- * hif_napi_get_all() - returns the address of the whole HIF NAPI structure
- * @hif: pointer to hif context
- *
- * Description:
- *    Returns the address of the whole structure
- *
- * Return:
- *  <addr>: address of the whole HIF NAPI structure
- */
-inline struct qca_napi_data *hif_napi_get_all(struct ol_softc   *hif)
-{
-	return &(hif->napi_data);
-}
-
-/**
- *
- * hif_napi_event() - Decision-maker to enable/disable NAPI.
- * @hif : pointer to hif context
- * @evnt: event that has been detected
- * @data: more data regarding the event
- *
- * Description:
- *   This function decides whether or not NAPI should be enabled.
- *   NAPI will be enabled, if all the following is satisfied.
- *    1- has been enabled administratively:
- *       the .ini file has the enabled setting and it has not been disabled
- *           by an vendor command override later
- *
- * Return:
- *  < 0: some error
- *  = 0: NAPI is now disabled
- *  = 1: NAPI is now enabled
- */
-int hif_napi_event(struct ol_softc *hif, enum qca_napi_event event, void *data)
-{
-	int      rc;
-	uint32_t prev_state;
-	int      i;
-	struct napi_struct *napi;
-
-	NAPI_DEBUG("-->(event=%d, aux=%p)\n", event, data);
-
-	mutex_lock(&(hif->napi_data.mutex));
-	prev_state = hif->napi_data.state;
-	switch (event) {
-	case NAPI_EVT_INI_FILE:
-	case NAPI_EVT_CMD_STATE: {
-		int on = (data != ((void *)0));
-
-		HIF_INFO("%s: received evnt: CONF %s; v = %d (state=0x%0x)\n",
-			 __func__,
-			 (event == NAPI_EVT_INI_FILE)?".ini file":"cmd",
-			 on, prev_state);
-		if (on)
-			if (prev_state & HIF_NAPI_CONF_UP) {
-				HIF_INFO("%s: duplicate NAPI conf ON msg\n",
-					 __func__);
-			} else {
-				HIF_INFO("%s: setting configuration to ON\n",
-					 __func__);
-				hif->napi_data.state |= HIF_NAPI_CONF_UP;
-			}
-		else /* off request */
-			if (prev_state & HIF_NAPI_CONF_UP) {
-				HIF_INFO("%s: setting configuration to OFF\n",
-				 __func__);
-				hif->napi_data.state &= ~HIF_NAPI_CONF_UP;
-			} else {
-				HIF_INFO("%s: duplicate NAPI conf OFF msg\n",
-					 __func__);
-			}
-		break;
-	}
-	/* case NAPI_INIT_FILE/CMD_STATE */
-	default: {
-		HIF_ERROR("%s: unknown event: %d (data=0x%0lx)\n",
-			  __func__, event, (unsigned long) data);
-		break;
-	} /* default */
-	}; /* switch */
-
-
-	mutex_unlock(&(hif->napi_data.mutex));
-
-	if (prev_state != hif->napi_data.state) {
-		if (hif->napi_data.state == ENABLE_NAPI_MASK) {
-			rc = 1;
-			for (i = 0; i < CE_COUNT_MAX; i++)
-				if ((hif->napi_data.ce_map & (0x01 << i))) {
-					napi = &(hif->napi_data.napis[i].napi);
-					NAPI_DEBUG("enabling NAPI %d\n", i);
-					napi_enable(napi);
-				}
-		} else {
-			rc = 0;
-			for (i = 0; i < CE_COUNT_MAX; i++)
-				if (hif->napi_data.ce_map & (0x01 << i)) {
-					napi = &(hif->napi_data.napis[i].napi);
-					NAPI_DEBUG("disabling NAPI %d\n", i);
-					napi_disable(napi);
-				}
-		}
-	} else {
-		HIF_INFO("%s: no change in hif napi state (still %d)\n",
-			 __func__, prev_state);
-		rc = (hif->napi_data.state == ENABLE_NAPI_MASK);
-	}
-
-	NAPI_DEBUG("<--[rc=%d]\n", rc);
-	return rc;
-}
-
-/**
- * hif_napi_enabled() - checks whether NAPI is enabled for given ce or not
- * @hif: hif context
- * @ce : CE instance (or -1, to check if any CEs are enabled)
- *
- * Return: bool
- */
-int hif_napi_enabled(struct ol_softc *hif, int ce)
-{
-	int rc;
-
-	if (-1 == ce)
-		rc = ((hif->napi_data.state == ENABLE_NAPI_MASK));
-	else
-		rc = ((hif->napi_data.state == ENABLE_NAPI_MASK) &&
-		      (hif->napi_data.ce_map & (0x01 << ce)));
-	return rc;
-};
-
-/**
- * hif_napi_enable_irq() - enables bus interrupts after napi_complete
- *
- * @hif: hif context
- * @id : id of NAPI instance calling this (used to determine the CE)
- *
- * Return: void
- */
-inline void hif_napi_enable_irq(struct ol_softc *hif, int id)
-{
-	ce_irq_enable(hif, NAPI_ID2PIPE(id));
-}
-
-
-/**
- * hif_napi_schedule() - schedules napi, updates stats
- * @scn:  hif context
- * @ce_id: index of napi instance
- *
- * Return: void
- */
-int hif_napi_schedule(struct ol_softc *scn, int ce_id)
-{
-	int cpu = smp_processor_id();
-
-	scn->napi_data.napis[ce_id].stats[cpu].napi_schedules++;
-	NAPI_DEBUG("scheduling napi %d (ce:%d)\n",
-		   scn->napi_data.napis[ce_id].id, ce_id);
-	napi_schedule(&(scn->napi_data.napis[ce_id].napi));
-
-	return true;
-}
-
-/**
- * hif_napi_poll() - NAPI poll routine
- * @napi  : pointer to NAPI struct as kernel holds it
- * @budget:
- *
- * This is the body of the poll function.
- * The poll function is called by kernel. So, there is a wrapper
- * function in HDD, which in turn calls this function.
- * Two main reasons why the whole thing is not implemented in HDD:
- * a) references to things like ce_service that HDD is not aware of
- * b) proximity to the implementation of ce_tasklet, which the body
- *    of this function should be very close to.
- *
- * NOTE TO THE MAINTAINER:
- *  Consider this function and ce_tasklet very tightly coupled pairs.
- *  Any changes to ce_tasklet or this function may likely need to be
- *  reflected in the counterpart.
- *
- * Returns:
- *  int: the amount of work done in this poll ( <= budget)
- */
-int hif_napi_poll(struct napi_struct *napi, int budget)
-{
-	int    rc = 0; /* default: no work done, also takes care of error */
-	int    normalized, bucket;
-	int    cpu = smp_processor_id();
-	struct ol_softc      *hif;
-	struct qca_napi_info *napi_info;
-	struct CE_state *ce_state;
-
-	NAPI_DEBUG("%s -->(.., budget=%d)\n", budget);
-
-	napi_info = (struct qca_napi_info *)
-		container_of(napi, struct qca_napi_info, napi);
-	napi_info->stats[cpu].napi_polls++;
-
-	hif = (struct ol_softc *)cds_get_context(CDF_MODULE_ID_HIF);
-	if (unlikely(NULL == hif))
-		CDF_ASSERT(hif != NULL); /* emit a warning if hif NULL */
-	else {
-		rc = ce_per_engine_service(hif, NAPI_ID2PIPE(napi_info->id));
-		HIF_INFO_HI("%s: ce_per_engine_service processed %d msgs",
-			    __func__, rc);
-	}
-	napi_info->stats[cpu].napi_workdone += rc;
-	normalized = (rc / napi_info->scale);
-
-	if (NULL != hif) {
-		ce_state = hif->ce_id_to_state[NAPI_ID2PIPE(napi_info->id)];
-		if (ce_state->lro_flush_cb != NULL) {
-			ce_state->lro_flush_cb(ce_state->lro_data);
-		}
-	}
-
-	/* do not return 0, if there was some work done,
-	 * even if it is below the scale
-	 */
-	if (rc)
-		normalized++;
-	bucket   = (normalized / QCA_NAPI_DEF_SCALE);
-	napi_info->stats[cpu].napi_budget_uses[bucket]++;
-
-	/* if ce_per engine reports 0, then poll should be terminated */
-	if (0 == rc)
-		NAPI_DEBUG("%s:%d: nothing processed by CE. Completing NAPI\n",
-			   __func__, __LINE__);
-
-	if (rc <= HIF_NAPI_MAX_RECEIVES) {
-		napi_info->stats[cpu].napi_completes++;
-		/* enable interrupts */
-		napi_complete(napi);
-		if (NULL != hif) {
-			hif_napi_enable_irq(hif, napi_info->id);
-
-			/* support suspend/resume */
-			cdf_atomic_dec(&(hif->active_tasklet_cnt));
-		}
-
-		NAPI_DEBUG("%s:%d: napi_complete + enabling the interrupts\n",
-			   __func__, __LINE__);
-	}
-
-	NAPI_DEBUG("%s <--[normalized=%d]\n", _func__, normalized);
-	return normalized;
-}

core/hif/src/icnss_stub/icnss_stub.c

@@ -1,369 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifdef HIF_PCI
-
-#include "icnss_stub.h"
-#include "hif_io32.h"
-#include <hif.h>
-#include "regtable.h"
-#include "hif_debug.h"
-#include "cds_api.h"
-#include "cdf_status.h"
-#include "qwlan_version.h"
-#include <net/cnss.h>
-
-static int icnss_get_irq_num(int ce_id);
-
-/**
- * struct icnss_stub_entry
- *
- * @irq_handler: irq_handler
- * @data: data
- * @name: name
- * @ce_id: ce_id
- */
-struct icnss_stub_entry {
-	irqreturn_t (*irq_handler)(int, void *);
-	void *data;
-	const char *name;
-	int ce_id;
-};
-
-/**
- * struct icnss_stub_context
- *
- * @stub: icnss_stub_entry
- * @regged_irq: regged_irq
- */
-struct icnss_stub_context {
-	struct icnss_stub_entry stub[ICNSS_MAX_IRQ_REGISTRATIONS];
-	uint32_t regged_irq;
-};
-
-static struct icnss_stub_context cnss_stub;
-
-#ifndef QCA_WIFI_3_0_ADRASTEA
-/**
- * icnss_wlan_enable() - icnss_wlan_enable
- * @config: ce configuration information
- * @mode: driver_mode
- * @host_version: version string to send to the fw
- *
- * Return: int
- */
-int icnss_wlan_enable(struct icnss_wlan_enable_cfg *config,
-	enum icnss_driver_mode mode, const char *host_version)
-{
-	return 0;
-}
-
-/**
- * icnss_wlan_disable() - icnss_wlan_disable
- * @mode: driver_mode
- *
- * Return: int
- */
-int icnss_wlan_disable(enum icnss_driver_mode mode)
-{
-	return 0;
-}
-
-/**
- * icnss_set_fw_debug_mode() - icnss_set_fw_debug_mode
- * @mode: fw debug mode, 0 for QXDM, 1 for WMI
- *
- * Return: int
- */
-int icnss_set_fw_debug_mode(bool mode)
-{
-	return 0;
-}
-
-#else
-
-/**
- * icnss_wlan_enable(): call the platform driver to enable wlan
- * @config: ce configuration information
- * @mode: driver_mode
- * @host_version: version string to send to the fw
- *
- * This function passes the con_mode and CE configuration to
- * platform driver to enable wlan.
- * cnss_wlan_enable has been hacked to do a qmi handshake with fw.
- * this is not needed for rome.
- *
- * Return: 0 on success, error number otherwise.
- */
-int icnss_wlan_enable(struct icnss_wlan_enable_cfg *config,
-	enum icnss_driver_mode mode, const char *host_version)
-{
-	struct cnss_wlan_enable_cfg cfg;
-	enum cnss_driver_mode cnss_mode;
-
-	cfg.num_ce_tgt_cfg = config->num_ce_tgt_cfg;
-	cfg.ce_tgt_cfg = (struct cnss_ce_tgt_pipe_cfg *)
-		config->ce_tgt_cfg;
-	cfg.num_ce_svc_pipe_cfg = config->num_ce_svc_pipe_cfg;
-	cfg.ce_svc_cfg = (struct cnss_ce_svc_pipe_cfg *)
-		config->ce_svc_cfg;
-
-	cfg.num_shadow_reg_cfg = config->num_shadow_reg_cfg;
-	cfg.shadow_reg_cfg = (struct cnss_shadow_reg_cfg *)
-		config->shadow_reg_cfg;
-
-	switch (mode) {
-	case ICNSS_FTM:
-		cnss_mode = CNSS_FTM;
-		break;
-	case ICNSS_EPPING:
-		cnss_mode = CNSS_EPPING;
-		break;
-	default:
-		cnss_mode = CNSS_MISSION;
-		break;
-	}
-	return cnss_wlan_enable(&cfg, cnss_mode, host_version);
-}
-
-/**
- * icnss_wlan_disable(): call the platform driver to disable wlan
- *
- * This function passes the con_mode to platform driver to disable wlan.
- * cnss_wlan_disable has been hacked to do a qmi handshake with fw.
- * this is not needed for rome.
- *
- * Return: void
- */
-int icnss_wlan_disable(enum icnss_driver_mode con_mode)
-{
-	enum cnss_driver_mode mode;
-
-	switch (con_mode) {
-	case ICNSS_FTM:
-		mode = CNSS_FTM;
-		break;
-	case ICNSS_EPPING:
-		mode = CNSS_EPPING;
-		break;
-	default:
-		mode = CNSS_MISSION;
-		break;
-	}
-
-	cnss_wlan_disable(mode);
-	return 0;
-}
-
-/**
- * icnss_set_fw_debug_mode() - call the platform driver to set fw
- * debug mode
- * @mode: fw debug mode, 0 for QXDM, 1 for WMI
- *
- * This function passes the fw debug mode to platform driver.
- * cnss_set_fw_debug_mode has been hacked to do a qmi handshake with fw.
- * This is not needed for rome.
- *
- * Return: int
- */
-int icnss_set_fw_debug_mode(bool mode)
-{
-	return cnss_set_fw_debug_mode(mode);
-}
-#endif
-
-/**
- * icnss_ce_request_irq() - register an irq handler
- * @ce_id: ce_id
- * @handler: handler
- * @flags: flags to pass to the kernel api
- * @name: name
- * @context: context to pass to the irq handler
- *
- * Return: integer status
- */
-int icnss_ce_request_irq(int ce_id,
-	irqreturn_t (*handler)(int, void *),
-	unsigned long flags, const char *name,
-	void *context)
-{
-	if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
-		HIF_ERROR("%s: invalid ce_id = %d", __func__, ce_id);
-		return -EINVAL;
-	}
-
-	cnss_stub.stub[ce_id].irq_handler = handler;
-	cnss_stub.stub[ce_id].ce_id = ce_id;
-	cnss_stub.stub[ce_id].data = context;
-	cnss_stub.stub[ce_id].name = name;
-	cnss_stub.regged_irq |= (1 << ce_id);
-	return 0;
-}
-
-/**
- * icnss_ce_free_irq() - icnss_unregister_irq
- * @ce_id: the ce_id that the irq belongs to
- * @context: context with witch the irq was requested.
- * Return: integer status
- */
-int icnss_ce_free_irq(int ce_id, void *context)
-{
-	if (ce_id >= ICNSS_MAX_IRQ_REGISTRATIONS) {
-		HIF_ERROR("%s: invalid ce_id = %d", __func__, ce_id);
-		return -EINVAL;
-	}
-
-	if (cnss_stub.stub[ce_id].data != context) {
-		HIF_ERROR("%s: context match failure for ce_id %d",
-		__func__, ce_id);
-		return -EINVAL;
-	}
-
-	if (cnss_stub.regged_irq & (1 << ce_id)) {
-		cnss_stub.stub[ce_id].irq_handler = NULL;
-		cnss_stub.stub[ce_id].ce_id = 0;
-		cnss_stub.stub[ce_id].data = 0;
-		cnss_stub.stub[ce_id].name = NULL;
-		cnss_stub.regged_irq &= ~(1 << ce_id);
-	}
-	return 0;
-}
-
-/**
- * icnss_dispatch_one_ce_irq() - icnss_dispatch_one_ce_irq
- * @ce_id: ce_id
- *
- * Return: irqreturn_t
- */
-static irqreturn_t icnss_dispatch_one_ce_irq(int ce_id)
-{
-	irqreturn_t ret = IRQ_NONE;
-
-	if (cnss_stub.stub[ce_id].irq_handler)
-		ret = cnss_stub.stub[ce_id].irq_handler(
-			icnss_get_irq_num(ce_id),
-			(void *)cnss_stub.stub[ce_id].data);
-	else
-		HIF_ERROR(
-			"%sd: error - ce_id = %d, no IRQ handler",
-			__func__, ce_id);
-
-	return ret;
-}
-
-/**
- * icnss_dispatch_ce_irq() - icnss_dispatch_ce_irq
- * @scn: scn
- *
- * Return: N/A
- */
-void icnss_dispatch_ce_irq(struct ol_softc *scn)
-{
-	uint32_t intr_summary;
-	int id;
-	irqreturn_t ret;
-
-	if (scn->hif_init_done != true)
-		return;
-
-	A_TARGET_ACCESS_BEGIN(scn);
-	intr_summary = CE_INTERRUPT_SUMMARY(scn);
-
-	if (intr_summary == 0) {
-		if ((scn->target_status != OL_TRGET_STATUS_RESET) &&
-			(!cdf_atomic_read(&scn->link_suspended))) {
-
-			hif_write32_mb(scn->mem +
-				(SOC_CORE_BASE_ADDRESS |
-				PCIE_INTR_ENABLE_ADDRESS),
-				HOST_GROUP0_MASK);
-
-			hif_read32_mb(scn->mem +
-					(SOC_CORE_BASE_ADDRESS |
-					PCIE_INTR_ENABLE_ADDRESS));
-		}
-		A_TARGET_ACCESS_END(scn);
-		return;
-	} else {
-		A_TARGET_ACCESS_END(scn);
-	}
-
-	scn->ce_irq_summary = intr_summary;
-	for (id = 0; intr_summary && (id < scn->ce_count); id++) {
-		if (intr_summary & (1 << id)) {
-			intr_summary &= ~(1 << id);
-			ret = icnss_dispatch_one_ce_irq(id);
-		}
-	}
-}
-
-/**
- * icnss_get_soc_info() - get soc info
- *
- * This function query the soc information from the platform
- * driver
- *
- * @info: struct icnss_soc_info
- *
- * Return: 0 for success
- */
-int icnss_get_soc_info(struct icnss_soc_info *info)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-
-	if (!scn) {
-		HIF_ERROR("%s: SCN = NULL", __func__);
-		return -EINVAL;
-	}
-	info->v_addr = scn->mem;
-	info->p_addr = scn->mem_pa;
-	info->version = 0;
-	return 0;
-}
-
-
-/* icnss_get_irq_num() - generate a number to represent an irq number
-*/
-static int icnss_get_irq_num(int ce_id)
-{
-	if (ce_id < CE_COUNT_MAX && ce_id >= 0)
-		return ce_id + 100;
-
-	pr_err("icnss: No irq registered for CE id %d\n", ce_id);
-	return -EINVAL;
-}
-
-int icnss_get_ce_id(int irq)
-{
-	int ce_id = irq - 100;
-	if (ce_id < CE_COUNT_MAX && ce_id >= 0)
-		return ce_id;
-
-	pr_err("icnss: No matching CE id for irq %d\n", irq);
-	return -EINVAL;
-}
-#endif /* HIF_PCI */

core/hif/src/icnss_stub/icnss_stub.h

@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifdef HIF_PCI
-#ifndef _ICNSS_WLAN_H_
-#define _ICNSS_WLAN_H_
-
-#include <linux/device.h>
-#include <linux/pci.h>
-#include <linux/irqreturn.h>
-
-#define ICNSS_MAX_IRQ_REGISTRATIONS 12
-
-/**
- * struct ce_tgt_pipe_cfg
- *
- * @pipenum: pipe_num
- * @pipedir: pipe_dir
- * @nentries: nentries
- * @nbytes_max: nbytes_max
- * @flags: flags
- * @reserved: reserved
- */
-struct ce_tgt_pipe_cfg {
-	uint32_t pipe_num;
-	uint32_t pipe_dir;
-	uint32_t nentries;
-	uint32_t nbytes_max;
-	uint32_t flags;
-	uint32_t reserved;
-};
-
-/**
- * struct ce_svc_pipe_cfg
- *
- * @service_id: service_id
- * @pipedir: pipedir
- * @pipenum: pipenum
- */
-struct ce_svc_pipe_cfg {
-	uint32_t service_id;
-	uint32_t pipedir;
-	uint32_t pipenum;
-};
-
-/**
- * struct icnss_shadow_reg_cfg
- *
- * @ce_id: Copy engine id
- * @reg_offset: Register offset
- */
-struct icnss_shadow_reg_cfg {
-	u16 ce_id;
-	u16 reg_offset;
-};
-/**
- * struct icnss_wlan_enable_cfg
- *
- * @num_ce_tgt_cfg: num_ce_tgt_cfg
- * @ce_tgt_cfg: ce_tgt_cfg
- * @num_ce_svc_pipe_cfg: num_ce_svc_pipe_cfg
- * @ce_svc_cfg: ce_svc_cfg
- */
-struct icnss_wlan_enable_cfg {
-	uint32_t num_ce_tgt_cfg;
-	struct ce_tgt_pipe_cfg *ce_tgt_cfg;
-	uint32_t num_ce_svc_pipe_cfg;
-	struct ce_svc_pipe_cfg *ce_svc_cfg;
-	u32 num_shadow_reg_cfg;
-	struct icnss_shadow_reg_cfg *shadow_reg_cfg;
-};
-
-/**
- * enum driver_mode
- *
- * @driver_mode: driver_mode
- */
-enum icnss_driver_mode {
-	ICNSS_MISSION,
-	ICNSS_FTM,
-	ICNSS_EPPING,
-};
-
-/**
- * struct icnss_soc_info
- *
- * @v_addr: virtual address
- * @p_addr: physical address
- * @ver: version
- */
-struct icnss_soc_info {
-	void __iomem *v_addr;
-	phys_addr_t p_addr;
-	uint32_t version;
-};
-
-int icnss_wlan_enable(struct icnss_wlan_enable_cfg *config,
-	enum icnss_driver_mode mode, const char *host_version);
-int icnss_wlan_disable(enum icnss_driver_mode mode);
-int icnss_set_fw_debug_mode(bool mode);
-int icnss_ce_request_irq(int ce_id,
-	irqreturn_t (*handler)(int ce_id, void *arg),
-	unsigned long flags, const char *name, void *context);
-int icnss_ce_free_irq(int irq, void *context);
-void icnss_enable_irq(unsigned int ce_id);
-void icnss_disable_irq(unsigned int ce_id);
-int icnss_get_soc_info(struct icnss_soc_info *info);
-int icnss_get_ce_id(int irq);
-#endif /* _ICNSS_WLAN_H_ */
-#endif /* HIF_PCI */
-

core/hif/src/mp_dev.c

@@ -1,327 +0,0 @@
-/*
- * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include "hif_io32.h"
-#include "hif_debug.h"
-
-/*chaninfo*/
-#define  CHANINFOMEM_S2_READ_MASK               0x00000008
-#define  CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK   0x00000001
-#define  CHANINFO_CTRL_CHANINFOMEM_BW_MASK      0x00000030
-#define  MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK   0x00000007
-
-/*agc*/
-#define GAINS_MIN_OFFSETS_CF_AGC_HIST_ENABLE_MASK              0x00040000
-#define GAINS_MIN_OFFSETS_CF_AGC_HIST_GC_MASK                  0x00080000
-#define GAINS_MIN_OFFSETS_CF_AGC_HIST_VOTING_MASK              0x00100000
-#define GAINS_MIN_OFFSETS_CF_AGC_HIST_PHY_ERR_MASK             0x00200000
-#define  AGC_HISTORY_DUMP_MASK (\
-	GAINS_MIN_OFFSETS_CF_AGC_HIST_ENABLE_MASK| \
-	GAINS_MIN_OFFSETS_CF_AGC_HIST_GC_MASK| \
-	GAINS_MIN_OFFSETS_CF_AGC_HIST_VOTING_MASK| \
-	GAINS_MIN_OFFSETS_CF_AGC_HIST_PHY_ERR_MASK \
-	)
-
-#define BB_chaninfo_ctrl         0x1a370
-#define BB_multichain_enable     0x1a2a0
-#define BB_chn_tables_intf_addr  0x19894
-#define BB_chn1_tables_intf_addr 0x1a894
-#define BB_chn_tables_intf_data  0x19898
-#define BB_chn1_tables_intf_data 0x1a898
-#define BB_gains_min_offsets     0x19e08
-#define BB_chaninfo_tab_b0       0x03200
-#define BB_chaninfo_tab_b1       0x03300
-#define BB_watchdog_status       0x1a7c0
-#define BB_watchdog_ctrl_1       0x1a7c4
-#define BB_watchdog_ctrl_2       0x1a7c8
-#define BB_watchdog_status_B     0x1a7e0
-
-
-#define PHY_BB_CHN_TABLES_INTF_ADDR 0x19894
-#define PHY_BB_CHN_TABLES_INTF_DATA 0x19898
-
-#define PHY_BB_CHN1_TABLES_INTF_ADDR 0x1a894
-#define PHY_BB_CHN1_TABLES_INTF_DATA 0x1a898
-
-
-struct priv_ctrl_ctx {
-	uint32_t chaninfo_ctrl_orig;
-	uint32_t gain_min_offsets_orig;
-	uint32_t anyreg_start;
-	uint32_t anyreg_len;
-};
-
-static struct priv_ctrl_ctx g_priv_dump_ctx;
-
-static INLINE void set_target_reg_bits(void __iomem *mem, uint32_t reg,
-				       uint32_t bitmask, uint32_t val)
-{
-	uint32_t value = hif_read32_mb(mem + (reg));
-	uint32_t shift = 0;
-	value &= ~(bitmask);
-	while (!((bitmask >> shift) & 0x01))
-		shift++;
-
-	value |= (((val) << shift) & (bitmask));
-	hif_write32_mb(mem + (reg), value);
-}
-
-static INLINE uint32_t get_target_reg_bits(void __iomem *mem,
-					   uint32_t reg, uint32_t bitmask)
-{
-	uint32_t value = hif_read32_mb(mem + (reg));
-	uint32_t shift = 0;
-	while (!((bitmask >> shift) & 0x01))
-		shift++;
-
-	return (value >> shift) & bitmask;
-}
-
-void priv_start_cap_chaninfo(struct ol_softc *scn)
-{
-	set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
-			    CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK, 1);
-}
-
-void priv_start_agc(struct ol_softc *scn)
-{
-	g_priv_dump_ctx.gain_min_offsets_orig =
-		hif_read32_mb(scn->mem + BB_gains_min_offsets);
-	set_target_reg_bits(scn->mem, BB_gains_min_offsets,
-			    AGC_HISTORY_DUMP_MASK,
-			    0x0f);
-}
-
-void priv_stop_agc(struct ol_softc *scn)
-{
-	set_target_reg_bits(scn->mem, BB_gains_min_offsets,
-			    AGC_HISTORY_DUMP_MASK,
-			    0);
-}
-
-void priv_dump_chaninfo(struct ol_softc *scn)
-{
-	uint32_t bw, val;
-	uint32_t len, i, tmp;
-	uint32_t chain_mask;
-	uint32_t chain0, chain1;
-
-	chain_mask =
-		get_target_reg_bits(scn->mem, BB_multichain_enable,
-				    MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK);
-	chain0 = chain_mask & 1;
-	chain1 = chain_mask & 2;
-
-	HIF_TRACE("%s: E", __func__);
-	bw = get_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
-				 CHANINFO_CTRL_CHANINFOMEM_BW_MASK);
-
-	if (bw == 0)
-		len = 53;
-	else if (bw == 1)
-		len = 57;
-	else if (bw == 2)
-		len = 59 * 2 - 1;
-	else
-		len = 60 * 2 + 61 * 2;
-
-	/*
-	 * each tone is 16 bit valid, write to 32bit buffer each.
-	 * bw==0(legacy20): 53 tones.
-	 * bw==1(ht/vht20): 57 tones.
-	 * bw==2(ht/vht40): 59+58 tones.
-	 * bw==3(vht80): 60*2+61*2 tones.
-	 */
-
-	if (chain0) {
-		hif_write32_mb(scn->mem + BB_chn_tables_intf_addr,
-			      0x80003200);
-	}
-	if (chain1) {
-		hif_write32_mb(scn->mem + BB_chn1_tables_intf_addr,
-			      0x80003200);
-	}
-
-	set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
-			CHANINFOMEM_S2_READ_MASK, 0);
-
-	if (chain0) {
-		if (bw < 2) {
-			len = (bw == 0) ? 53 : 57;
-			for (i = 0; i < len; i++) {
-				val =
-					hif_read32_mb(scn->mem +
-						     BB_chn_tables_intf_data) &
-					0x0000ffff;
-				cdf_print("0x%x\t", val);
-				if (i % 4 == 0)
-					cdf_print("\n");
-			}
-		} else {
-			len = (bw == 2) ? 59 : 60;
-			for (i = 0; i < len; i++) {
-				tmp =
-					hif_read32_mb(scn->mem +
-						     BB_chn_tables_intf_data);
-				cdf_print("0x%x\t", ((tmp >> 16) & 0x0000ffff));
-				cdf_print("0x%x\t", (tmp & 0x0000ffff));
-				if (i % 2 == 0)
-					cdf_print("\n");
-			}
-			if (bw > 2) {
-				/* bw == 3 for vht80 */
-				hif_write32_mb(scn->mem +
-					      BB_chn_tables_intf_addr,
-					      0x80003300);
-				len = 61;
-				for (i = 0; i < len; i++) {
-					tmp =
-						hif_read32_mb(scn->mem +
-						     BB_chn_tables_intf_data);
-					cdf_print("0x%x\t",
-					       ((tmp >> 16) & 0x0000ffff));
-					cdf_print("0x%x\t", (tmp & 0x0000ffff));
-					if (i % 2 == 0)
-						cdf_print("\n");
-				}
-			}
-		}
-	}
-	if (chain1) {
-		if (bw < 2) {
-			len = (bw == 0) ? 53 : 57;
-			for (i = 0; i < len; i++) {
-				val =
-					hif_read32_mb(scn->mem +
-						BB_chn1_tables_intf_data) &
-					0x0000ffff;
-				cdf_print("0x%x\t", val);
-				if (i % 4 == 0)
-					cdf_print("\n");
-			}
-		} else {
-			len = (bw == 2) ? 59 : 60;
-			for (i = 0; i < len; i++) {
-				tmp =
-					hif_read32_mb(scn->mem +
-						     BB_chn1_tables_intf_data);
-				cdf_print("0x%x\n", (tmp >> 16) & 0x0000ffff);
-				cdf_print("0x%x\n", tmp & 0x0000ffff);
-				if (i % 2 == 0)
-					cdf_print("\n");
-			}
-			if (bw > 2) {
-				/* bw == 3 for vht80 */
-				hif_write32_mb(scn->mem +
-					      BB_chn1_tables_intf_addr,
-					      0x80003300);
-				len = 61;
-				for (i = 0; i < len; i++) {
-					tmp =
-						hif_read32_mb(scn->mem +
-						     BB_chn1_tables_intf_data);
-					cdf_print("0x%x\t",
-					       ((tmp >> 16) & 0x0000ffff));
-					cdf_print("0x%x\t", (tmp & 0x0000ffff));
-					if (i % 2 == 0)
-						cdf_print("\n");
-				}
-			}
-		}
-	}
-	HIF_TRACE("%s: X", __func__);
-}
-
-void priv_dump_agc(struct ol_softc *scn)
-{
-	int i, len = 30;        /* check this value for Rome and Peregrine */
-	uint32_t chain0, chain1, chain_mask, val;
-
-	A_TARGET_ACCESS_BEGIN(scn);
-
-	chain_mask =
-		get_target_reg_bits(scn->mem, BB_multichain_enable,
-				    MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK);
-	chain0 = chain_mask & 1;
-	chain1 = chain_mask & 2;
-
-	len = len << 1;         /* each agc item is 64bit, total*2 */
-	priv_stop_agc(scn);
-
-	set_target_reg_bits(scn->mem, BB_chaninfo_ctrl,
-			CHANINFOMEM_S2_READ_MASK, 0);
-
-	HIF_TRACE("%s: AGC history buffer dump: E", __func__);
-	if (chain0) {
-		for (i = 0; i < len; i++) {
-			hif_write32_mb(scn->mem +
-				PHY_BB_CHN_TABLES_INTF_ADDR,
-				BB_chaninfo_tab_b0 + i * 4);
-			val = hif_read32_mb(scn->mem +
-				PHY_BB_CHN_TABLES_INTF_DATA);
-			cdf_print("0x%x\t", val);
-			if (i % 4 == 0)
-				cdf_print("\n");
-		}
-	}
-	if (chain1) {
-		for (i = 0; i < len; i++) {
-			hif_write32_mb(scn->mem +
-				PHY_BB_CHN1_TABLES_INTF_ADDR,
-				BB_chaninfo_tab_b0 + i * 4);
-			val = hif_read32_mb(scn->mem +
-				PHY_BB_CHN1_TABLES_INTF_DATA);
-			cdf_print("0x%x\t", val);
-			if (i % 4 == 0)
-				cdf_print("\n");
-		}
-	}
-	HIF_TRACE("%s: AGC history buffer dump X", __func__);
-	/* restore original value */
-	hif_write32_mb(scn->mem + BB_gains_min_offsets,
-		      g_priv_dump_ctx.gain_min_offsets_orig);
-
-	A_TARGET_ACCESS_END(scn);
-
-	return;
-}
-
-void priv_dump_bbwatchdog(struct ol_softc *scn)
-{
-	uint32_t val;
-
-	HIF_TRACE("%s: BB watchdog dump E", __func__);
-	val = hif_read32_mb(scn->mem + BB_watchdog_status);
-	cdf_print("0x%x\t", val);
-	val = hif_read32_mb(scn->mem + BB_watchdog_ctrl_1);
-	cdf_print("0x%x\t", val);
-	val = hif_read32_mb(scn->mem + BB_watchdog_ctrl_2);
-	cdf_print("0x%x\t", val);
-	val = hif_read32_mb(scn->mem + BB_watchdog_status_B);
-	cdf_print("0x%x", val);
-	HIF_TRACE("%s: BB watchdog dump X", __func__);
-}

core/hif/src/mp_dev.h

@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __MP_DEV_H__
-#define __MP_DEV_H__
-void priv_start_agc(struct ol_softc *scn);
-void priv_dump_agc(struct ol_softc *scn);
-void priv_start_cap_chaninfo(struct ol_softc *scn);
-void priv_dump_chaninfo(struct ol_softc *scn);
-void priv_dump_bbwatchdog(struct ol_softc *scn);
-void hif_shut_down_device(struct ol_softc *scn);
-#endif /* __MP_DEV_H__ */

core/hif/src/pcie/cnss_stub.h

@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __CNSS_STUB_H__
-#define __CNSS_STUB_H__
-
-#ifndef CONFIG_CNSS
-inline void cnss_wlan_pci_link_down(void) {}
-
-inline int cnss_pcie_shadow_control(struct pci_dev *dev, bool enable)
-{
-	return 0;
-}
-
-#endif
-#endif /* __CNSS_STUB_H__ */

core/hif/src/pcie/hif_io32_pci.h

@@ -1,312 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __HIF_IO32_PCI_H__
-#define __HIF_IO32_PCI_H__
-
-#ifdef HIF_PCI
-
-#include "hif.h"
-#include "regtable.h"
-#include "ce_reg.h"
-#include "cdf_atomic.h"
-#include "if_pci.h"
-/*
- * For maximum performance and no power management, set this to 1.
- * For power management at the cost of performance, set this to 0.
- */
-#define CONFIG_ATH_PCIE_MAX_PERF 0
-
-/*
- * For keeping the target awake till the driver is
- * loaded, set this to 1
- */
-#define CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 1
-
-/*
- * When CONFIG_ATH_PCIE_MAX_PERF is 0:
- * To use LIKELY hints, set this to 1 (slightly better performance, more power)
- * To ignore "LIKELY" hints, set this to 0 (slightly worse performance,
- * less power)
- */
-#if defined(CONFIG_ATH_PCIE_MAX_PERF)
-#define CONFIG_ATH_PCIE_ACCESS_LIKELY 0
-#else
-#define CONFIG_ATH_PCIE_ACCESS_LIKELY 1
-#endif
-
-/*
- * PCI-E L1 ASPPM sub-states
- * To enable clock gating in L1 state, set this to 1.
- * (less power, slightly more wakeup latency)
- * To disable clock gating in L1 state, set this to 0. (slighly more power)
- */
-#define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 1
-
-/*
- * PCIE_ACCESS_LOG_NUM specifies the number of
- * read/write records to store
- */
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-#define PCIE_ACCESS_LOG_NUM 500
-#endif
-
-/* 64-bit MSI support */
-#define CONFIG_PCIE_64BIT_MSI 0
-
-/* BAR0 ready checking for AR6320v2 */
-#define PCIE_BAR0_READY_CHECKING 0
-
-/* AXI gating when L1, L2 to reduce power consumption */
-#define CONFIG_PCIE_ENABLE_AXI_CLK_GATE 0
-
-#define hif_read32_mb(addr)         ioread32((void __iomem *)addr)
-#define hif_write32_mb(addr, value) \
-	iowrite32((u32)(value), (void __iomem *)(addr))
-
-extern int hif_target_sleep_state_adjust(struct ol_softc *scn,
-					 bool sleep_ok,
-					 bool wait_for_it);
-
-#if CONFIG_ATH_PCIE_MAX_PERF
-#define A_TARGET_ACCESS_BEGIN(scn) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_END(scn) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_OK(scn) 1
-
-#define A_TARGET_ACCESS_LIKELY(scn) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_UNLIKELY(scn) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_READ(scn, offset) \
-	hif_read32_mb(scn->mem + (offset))
-
-void war_pci_write32(char *addr, u32 offset, u32 value);
-#define A_TARGET_WRITE(scn, offset, value) \
-	war_pci_write32(scn->mem, (offset), (value))
-
-#define A_TARGET_ACCESS_BEGIN_RET(scn) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_BEGIN_RET_PTR(scn) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_END_RET(scn)	\
-	do {struct ol_softc *unused = scn; \
-		unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_END_RET_EXT(scn, val) \
-	do {struct ol_softc *unused = scn; \
-	    unused = unused; } while (0)
-
-#define A_TARGET_ACCESS_END_RET_PTR(scn) \
-	do {struct ol_softc *unused = scn; \
-		unused = unused; } while (0)
-
-#else                           /* CONFIG_ATH_PCIE_MAX_PERF */
-
-void war_pci_write32(char *addr, u32 offset, u32 value);
-
-#define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val) \
-do { \
-	if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
-		Q_TARGET_ACCESS_BEGIN(scn) < 0) \
-		val = -1; \
-} while (0)
-
-#define A_TARGET_ACCESS_BEGIN_RET(scn) \
-do { \
-	if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
-	    Q_TARGET_ACCESS_BEGIN(scn) < 0) \
-		return ATH_ISR_NOSCHED; \
-} while (0)
-
-#define A_TARGET_ACCESS_BEGIN_RET_PTR(scn) \
-do { \
-	if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
-	    Q_TARGET_ACCESS_BEGIN(scn) < 0) \
-		return NULL; \
-} while (0)
-
-#define A_TARGET_ACCESS_BEGIN(scn) \
-do { \
-	if (Q_TARGET_ACCESS_BEGIN(scn) < 0) \
-		return; \
-} while (0)
-
-#define Q_TARGET_ACCESS_BEGIN(scn) \
-	hif_target_sleep_state_adjust(scn, false, true)
-
-#define A_TARGET_ACCESS_END_RET(scn)	\
-do { \
-	if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
-	    Q_TARGET_ACCESS_END(scn) < 0) \
-		return ATH_ISR_NOSCHED; \
-} while (0)
-
-#define A_TARGET_ACCESS_END_RET_EXT(scn, val) \
-do { \
-	if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
-	    Q_TARGET_ACCESS_END(scn) < 0) \
-		val = -1; \
-} while (0)
-
-#define A_TARGET_ACCESS_END_RET_PTR(scn) \
-do { \
-	if (!WLAN_IS_EPPING_ENABLED(cds_get_conparam()) && \
-	    Q_TARGET_ACCESS_END(scn) < 0) \
-		return NULL; \
-} while (0)
-#define A_TARGET_ACCESS_END(scn) \
-do { \
-	if (Q_TARGET_ACCESS_END(scn) < 0) \
-		return; \
-} while (0)
-
-#define Q_TARGET_ACCESS_END(scn) \
-	hif_target_sleep_state_adjust(scn, true, false)
-
-#define A_TARGET_ACCESS_OK(scn) hif_target_forced_awake(scn)
-
-#if CONFIG_ATH_PCIE_ACCESS_LIKELY
-#define A_TARGET_ACCESS_LIKELY(scn) \
-	hif_target_sleep_state_adjust(scn, false, false)
-#define A_TARGET_ACCESS_UNLIKELY(scn) \
-	hif_target_sleep_state_adjust(scn, true, false)
-#else                           /* CONFIG_ATH_PCIE_ACCESS_LIKELY */
-#define A_TARGET_ACCESS_LIKELY(scn) \
-	do { \
-		unsigned long unused = (unsigned long)(scn); \
-		unused = unused; \
-	} while (0)
-
-#define A_TARGET_ACCESS_UNLIKELY(scn) \
-	do { \
-		unsigned long unused = (unsigned long)(scn); \
-		unused = unused; \
-	} while (0)
-#endif /* CONFIG_ATH_PCIE_ACCESS_LIKELY */
-
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-extern uint32_t hif_target_read_checked(struct ol_softc *scn,
-					uint32_t offset);
-extern void hif_target_write_checked(struct ol_softc *scn, uint32_t offset,
-				     uint32_t value);
-#define A_TARGET_READ(scn, offset) \
-	hif_target_read_checked(scn, (offset))
-#define A_TARGET_WRITE(scn, offset, value) \
-	hif_target_write_checked(scn, (offset), (value))
-#else                           /* CONFIG_ATH_PCIE_ACCESS_DEBUG */
-#define A_TARGET_READ(scn, offset) \
-	hif_read32_mb(scn->mem + (offset))
-#define A_TARGET_WRITE(scn, offset, value) \
-	war_pci_write32(scn->mem, (offset), (value))
-#endif
-#endif /* CONFIG_ATH_PCIE_MAX_PERF */
-
-
-irqreturn_t hif_fw_interrupt_handler(int irq, void *arg);
-
-/**
- * ce_irq_enable() - ce_irq_enable
- * @scn: ol_softc
- * @ce_id: ce_id
- *
- * Return: void
- */
-static inline void ce_irq_enable(struct ol_softc *scn, int ce_id)
-{
-	uint32_t tmp = 1 << ce_id;
-	struct hif_pci_softc *sc = scn->hif_sc;
-
-	cdf_spin_lock_irqsave(&scn->irq_lock);
-	scn->ce_irq_summary &= ~tmp;
-	if (scn->ce_irq_summary == 0) {
-		/* Enable Legacy PCI line interrupts */
-		if (LEGACY_INTERRUPTS(sc) &&
-			(scn->target_status != OL_TRGET_STATUS_RESET) &&
-			(!cdf_atomic_read(&scn->link_suspended))) {
-
-			hif_write32_mb(scn->mem +
-				(SOC_CORE_BASE_ADDRESS |
-				PCIE_INTR_ENABLE_ADDRESS),
-				HOST_GROUP0_MASK);
-
-			hif_read32_mb(scn->mem +
-					(SOC_CORE_BASE_ADDRESS |
-					PCIE_INTR_ENABLE_ADDRESS));
-		}
-	}
-	if (scn->hif_init_done == true)
-		A_TARGET_ACCESS_END(scn);
-	cdf_spin_unlock_irqrestore(&scn->irq_lock);
-
-	/* check for missed firmware crash */
-	hif_fw_interrupt_handler(0, scn);
-}
-/**
- * ce_irq_disable() - ce_irq_disable
- * @scn: ol_softc
- * @ce_id: ce_id
- *
- * Return: void
- */
-static inline void ce_irq_disable(struct ol_softc *scn, int ce_id)
-{
-	/* For Rome only need to wake up target */
-	A_TARGET_ACCESS_BEGIN(scn);
-}
-/**
- * soc_wake_reset() - soc_wake_reset
- * @scn: ol_softc
- *
- * Return: void
- */
-static inline void soc_wake_reset(struct ol_softc *scn)
-{
-	hif_write32_mb(scn->mem +
-		PCIE_LOCAL_BASE_ADDRESS +
-		PCIE_SOC_WAKE_ADDRESS,
-		PCIE_SOC_WAKE_RESET);
-}
-#endif /* HIF_PCI */
-#endif /* __HIF_IO32_PCI_H__ */

core/hif/src/pcie/if_pci.c

@@ -1,3309 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include <osdep.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/if_arp.h>
-#ifdef CONFIG_PCI_MSM
-#include <linux/msm_pcie.h>
-#endif
-#include "hif_io32.h"
-#include "if_pci.h"
-#include "hif.h"
-#include "hif_main.h"
-#include "ce_api.h"
-#include "ce_internal.h"
-#include "ce_reg.h"
-#include "bmi_msg.h"            /* TARGET_TYPE_ */
-#include "regtable.h"
-#include "ol_fw.h"
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <osapi_linux.h>
-#include "cds_api.h"
-#include "cdf_status.h"
-#include "cds_sched.h"
-#include "wma_api.h"
-#include "cdf_atomic.h"
-#include "wlan_hdd_power.h"
-#include "wlan_hdd_main.h"
-#ifdef CONFIG_CNSS
-#include <net/cnss.h>
-#else
-#include "cnss_stub.h"
-#endif
-#include "epping_main.h"
-#include "mp_dev.h"
-#include "hif_debug.h"
-
-#ifndef REMOVE_PKT_LOG
-#include "ol_txrx_types.h"
-#include "pktlog_ac_api.h"
-#include "pktlog_ac.h"
-#endif
-#include "if_pci_internal.h"
-#include "icnss_stub.h"
-#include "ce_tasklet.h"
-#include "cds_concurrency.h"
-
-/* Maximum ms timeout for host to wake up target */
-#define PCIE_WAKE_TIMEOUT 1000
-#define RAMDUMP_EVENT_TIMEOUT 2500
-
-unsigned int msienable = 0;
-module_param(msienable, int, 0644);
-
-int hif_pci_war1 = 0;
-static DEFINE_SPINLOCK(pciwar_lock);
-
-#ifndef REMOVE_PKT_LOG
-struct ol_pl_os_dep_funcs *g_ol_pl_os_dep_funcs = NULL;
-#endif
-
-/* Setting SOC_GLOBAL_RESET during driver unload causes intermittent
- * PCIe data bus error
- * As workaround for this issue - changing the reset sequence to
- * use TargetCPU warm reset * instead of SOC_GLOBAL_RESET
- */
-#define CPU_WARM_RESET_WAR
-/*
- * Top-level interrupt handler for all PCI interrupts from a Target.
- * When a block of MSI interrupts is allocated, this top-level handler
- * is not used; instead, we directly call the correct sub-handler.
- */
-struct ce_irq_reg_table {
-	uint32_t irq_enable;
-	uint32_t irq_status;
-};
-
-#if !defined(QCA_WIFI_3_0_ADRASTEA)
-static inline void cnss_intr_notify_q6(void)
-{
-}
-#endif
-
-#if !defined(QCA_WIFI_3_0_ADRASTEA)
-static inline void *cnss_get_target_smem(void)
-{
-	return NULL;
-}
-#endif
-
-#ifndef QCA_WIFI_3_0_ADRASTEA
-static inline void hif_pci_route_adrastea_interrupt(struct hif_pci_softc *sc)
-{
-	return;
-}
-#else
-void hif_pci_route_adrastea_interrupt(struct hif_pci_softc *sc)
-{
-	struct ol_softc *scn = sc->ol_sc;
-	unsigned int target_enable0, target_enable1;
-	unsigned int target_cause0, target_cause1;
-
-	target_enable0 = hif_read32_mb(sc->mem + Q6_ENABLE_REGISTER_0);
-	target_enable1 = hif_read32_mb(sc->mem + Q6_ENABLE_REGISTER_1);
-	target_cause0 = hif_read32_mb(sc->mem + Q6_CAUSE_REGISTER_0);
-	target_cause1 = hif_read32_mb(sc->mem + Q6_CAUSE_REGISTER_1);
-
-	if ((target_enable0 & target_cause0) ||
-	    (target_enable1 & target_cause1)) {
-		hif_write32_mb(sc->mem + Q6_ENABLE_REGISTER_0, 0);
-		hif_write32_mb(sc->mem + Q6_ENABLE_REGISTER_1, 0);
-
-		if (scn->notice_send)
-			cnss_intr_notify_q6();
-	}
-}
-#endif
-
-static irqreturn_t hif_pci_interrupt_handler(int irq, void *arg)
-{
-	struct hif_pci_softc *sc = (struct hif_pci_softc *)arg;
-	struct ol_softc *scn = sc->ol_sc;
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	volatile int tmp;
-	uint16_t val;
-	uint32_t bar0;
-	uint32_t fw_indicator_address, fw_indicator;
-	bool ssr_irq = false;
-	unsigned int host_cause, host_enable;
-
-	if (LEGACY_INTERRUPTS(sc)) {
-		if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
-			return IRQ_HANDLED;
-
-		if (ADRASTEA_BU) {
-			host_enable = hif_read32_mb(sc->mem +
-						    PCIE_INTR_ENABLE_ADDRESS);
-			host_cause = hif_read32_mb(sc->mem +
-						   PCIE_INTR_CAUSE_ADDRESS);
-			if (!(host_enable & host_cause)) {
-				hif_pci_route_adrastea_interrupt(sc);
-				return IRQ_HANDLED;
-			}
-		}
-
-		/* Clear Legacy PCI line interrupts
-		 * IMPORTANT: INTR_CLR regiser has to be set
-		 * after INTR_ENABLE is set to 0,
-		 * otherwise interrupt can not be really cleared */
-		hif_write32_mb(sc->mem +
-			      (SOC_CORE_BASE_ADDRESS |
-			       PCIE_INTR_ENABLE_ADDRESS), 0);
-
-		hif_write32_mb(sc->mem +
-			      (SOC_CORE_BASE_ADDRESS | PCIE_INTR_CLR_ADDRESS),
-			       ADRASTEA_BU ?
-			       (host_enable & host_cause) :
-			      HOST_GROUP0_MASK);
-
-		if (ADRASTEA_BU)
-			hif_write32_mb(sc->mem + 0x2f100c , (host_cause >> 1));
-
-		/* IMPORTANT: this extra read transaction is required to
-		 * flush the posted write buffer */
-		if (!ADRASTEA_BU) {
-		tmp =
-			hif_read32_mb(sc->mem +
-				     (SOC_CORE_BASE_ADDRESS |
-				      PCIE_INTR_ENABLE_ADDRESS));
-
-		if (tmp == 0xdeadbeef) {
-			HIF_ERROR("BUG(%s): SoC returns 0xdeadbeef!!",
-			       __func__);
-
-			pci_read_config_word(sc->pdev, PCI_VENDOR_ID, &val);
-			HIF_ERROR("%s: PCI Vendor ID = 0x%04x",
-			       __func__, val);
-
-			pci_read_config_word(sc->pdev, PCI_DEVICE_ID, &val);
-			HIF_ERROR("%s: PCI Device ID = 0x%04x",
-			       __func__, val);
-
-			pci_read_config_word(sc->pdev, PCI_COMMAND, &val);
-			HIF_ERROR("%s: PCI Command = 0x%04x", __func__,
-			       val);
-
-			pci_read_config_word(sc->pdev, PCI_STATUS, &val);
-			HIF_ERROR("%s: PCI Status = 0x%04x", __func__,
-			       val);
-
-			pci_read_config_dword(sc->pdev, PCI_BASE_ADDRESS_0,
-					      &bar0);
-			HIF_ERROR("%s: PCI BAR0 = 0x%08x", __func__,
-			       bar0);
-
-			HIF_ERROR("%s: RTC_STATE_ADDRESS = 0x%08x",
-				  __func__,
-				  hif_read32_mb(sc->mem +
-						PCIE_LOCAL_BASE_ADDRESS
-						+ RTC_STATE_ADDRESS));
-			HIF_ERROR("%s: PCIE_SOC_WAKE_ADDRESS = 0x%08x",
-				  __func__,
-				  hif_read32_mb(sc->mem +
-						PCIE_LOCAL_BASE_ADDRESS
-						+ PCIE_SOC_WAKE_ADDRESS));
-			HIF_ERROR("%s: 0x80008 = 0x%08x, 0x8000c = 0x%08x",
-				  __func__,
-				  hif_read32_mb(sc->mem + 0x80008),
-				  hif_read32_mb(sc->mem + 0x8000c));
-			HIF_ERROR("%s: 0x80010 = 0x%08x, 0x80014 = 0x%08x",
-				  __func__,
-				  hif_read32_mb(sc->mem + 0x80010),
-				  hif_read32_mb(sc->mem + 0x80014));
-			HIF_ERROR("%s: 0x80018 = 0x%08x, 0x8001c = 0x%08x",
-				  __func__,
-				  hif_read32_mb(sc->mem + 0x80018),
-				  hif_read32_mb(sc->mem + 0x8001c));
-			CDF_BUG(0);
-		}
-
-		PCI_CLR_CAUSE0_REGISTER(sc);
-		}
-
-		if (HAS_FW_INDICATOR) {
-			fw_indicator_address = hif_state->fw_indicator_address;
-			fw_indicator = A_TARGET_READ(scn, fw_indicator_address);
-			if ((fw_indicator != ~0) &&
-			   (fw_indicator & FW_IND_EVENT_PENDING))
-				ssr_irq = true;
-		}
-
-		if (Q_TARGET_ACCESS_END(scn) < 0)
-			return IRQ_HANDLED;
-	}
-	/* TBDXXX: Add support for WMAC */
-
-	if (ssr_irq) {
-		sc->irq_event = irq;
-		cdf_atomic_set(&scn->tasklet_from_intr, 1);
-
-		cdf_atomic_inc(&scn->active_tasklet_cnt);
-		tasklet_schedule(&sc->intr_tq);
-	} else {
-		icnss_dispatch_ce_irq(scn);
-	}
-
-	return IRQ_HANDLED;
-}
-
-static irqreturn_t hif_pci_msi_fw_handler(int irq, void *arg)
-{
-	struct hif_pci_softc *sc = (struct hif_pci_softc *)arg;
-
-	(irqreturn_t) hif_fw_interrupt_handler(sc->irq_event, sc->ol_sc);
-
-	return IRQ_HANDLED;
-}
-
-bool hif_targ_is_awake(struct ol_softc *scn, void *__iomem *mem)
-{
-	HIF_PCI_TARG_IS_AWAKE(scn, mem);
-}
-
-bool hif_pci_targ_is_present(struct ol_softc *scn, void *__iomem *mem)
-{
-	return 1;               /* FIX THIS */
-}
-
-/**
- * hif_pci_cancel_deferred_target_sleep() - cancels the defered target sleep
- * @scn: ol_softc
- *
- * Return: void
- */
-#if CONFIG_ATH_PCIE_MAX_PERF == 0
-void hif_pci_cancel_deferred_target_sleep(struct ol_softc *scn)
-{
-	struct HIF_CE_state *hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	A_target_id_t pci_addr = scn->mem;
-
-	cdf_spin_lock_irqsave(&hif_state->keep_awake_lock);
-	/*
-	 * If the deferred sleep timer is running cancel it
-	 * and put the soc into sleep.
-	 */
-	if (hif_state->fake_sleep == true) {
-		cdf_softirq_timer_cancel(&hif_state->sleep_timer);
-		if (hif_state->verified_awake == false) {
-			hif_write32_mb(pci_addr + PCIE_LOCAL_BASE_ADDRESS +
-				      PCIE_SOC_WAKE_ADDRESS,
-				      PCIE_SOC_WAKE_RESET);
-		}
-		hif_state->fake_sleep = false;
-	}
-	cdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock);
-}
-#else
-inline void hif_pci_cancel_deferred_target_sleep(struct ol_softc *scn)
-{
-	return;
-}
-#endif
-
-#define A_PCIE_LOCAL_REG_READ(mem, addr) \
-	hif_read32_mb((char *)(mem) + \
-	PCIE_LOCAL_BASE_ADDRESS + (uint32_t)(addr))
-
-#define A_PCIE_LOCAL_REG_WRITE(mem, addr, val) \
-	hif_write32_mb(((char *)(mem) + \
-	PCIE_LOCAL_BASE_ADDRESS + (uint32_t)(addr)), (val))
-
-#define ATH_PCI_RESET_WAIT_MAX 10       /* Ms */
-static void hif_pci_device_reset(struct hif_pci_softc *sc)
-{
-	void __iomem *mem = sc->mem;
-	int i;
-	uint32_t val;
-	struct ol_softc *scn = sc->ol_sc;
-
-	if (!scn->hostdef)
-		return;
-
-	/* NB: Don't check resetok here.  This form of reset
-	 * is integral to correct operation. */
-
-	if (!SOC_GLOBAL_RESET_ADDRESS) {
-		return;
-	}
-
-	if (!mem) {
-		return;
-	}
-
-	HIF_ERROR("%s: Reset Device", __func__);
-
-	/*
-	 * NB: If we try to write SOC_GLOBAL_RESET_ADDRESS without first
-	 * writing WAKE_V, the Target may scribble over Host memory!
-	 */
-	A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS,
-			       PCIE_SOC_WAKE_V_MASK);
-	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
-		if (hif_targ_is_awake(scn, mem))
-			break;
-
-		cdf_mdelay(1);
-	}
-
-	/* Put Target, including PCIe, into RESET. */
-	val = A_PCIE_LOCAL_REG_READ(mem, SOC_GLOBAL_RESET_ADDRESS);
-	val |= 1;
-	A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS, val);
-	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
-		if (A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS) &
-		    RTC_STATE_COLD_RESET_MASK)
-			break;
-
-		cdf_mdelay(1);
-	}
-
-	/* Pull Target, including PCIe, out of RESET. */
-	val &= ~1;
-	A_PCIE_LOCAL_REG_WRITE(mem, SOC_GLOBAL_RESET_ADDRESS, val);
-	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
-		if (!
-		    (A_PCIE_LOCAL_REG_READ(mem, RTC_STATE_ADDRESS) &
-		     RTC_STATE_COLD_RESET_MASK))
-			break;
-
-		cdf_mdelay(1);
-	}
-
-	A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
-}
-
-/* CPU warm reset function
- * Steps:
- * 1. Disable all pending interrupts - so no pending interrupts on WARM reset
- * 2. Clear the FW_INDICATOR_ADDRESS -so Traget CPU intializes FW
- *    correctly on WARM reset
- * 3. Clear TARGET CPU LF timer interrupt
- * 4. Reset all CEs to clear any pending CE tarnsactions
- * 5. Warm reset CPU
- */
-void hif_pci_device_warm_reset(struct hif_pci_softc *sc)
-{
-	void __iomem *mem = sc->mem;
-	int i;
-	uint32_t val;
-	uint32_t fw_indicator;
-	struct ol_softc *scn = sc->ol_sc;
-
-	/* NB: Don't check resetok here.  This form of reset is
-	 * integral to correct operation. */
-
-	if (!mem) {
-		return;
-	}
-
-	HIF_INFO_MED("%s: Target Warm Reset", __func__);
-
-	/*
-	 * NB: If we try to write SOC_GLOBAL_RESET_ADDRESS without first
-	 * writing WAKE_V, the Target may scribble over Host memory!
-	 */
-	A_PCIE_LOCAL_REG_WRITE(mem, PCIE_SOC_WAKE_ADDRESS,
-			       PCIE_SOC_WAKE_V_MASK);
-	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
-		if (hif_targ_is_awake(scn, mem))
-			break;
-		cdf_mdelay(1);
-	}
-
-	/*
-	 * Disable Pending interrupts
-	 */
-	val =
-		hif_read32_mb(mem +
-			     (SOC_CORE_BASE_ADDRESS |
-			      PCIE_INTR_CAUSE_ADDRESS));
-	HIF_INFO_MED("%s: Host Intr Cause reg 0x%x : value : 0x%x", __func__,
-		    (SOC_CORE_BASE_ADDRESS | PCIE_INTR_CAUSE_ADDRESS), val);
-	/* Target CPU Intr Cause */
-	val = hif_read32_mb(mem + (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS));
-	HIF_INFO_MED("%s: Target CPU Intr Cause 0x%x", __func__, val);
-
-	val =
-		hif_read32_mb(mem +
-			     (SOC_CORE_BASE_ADDRESS |
-			      PCIE_INTR_ENABLE_ADDRESS));
-	hif_write32_mb((mem +
-		       (SOC_CORE_BASE_ADDRESS | PCIE_INTR_ENABLE_ADDRESS)), 0);
-	hif_write32_mb((mem + (SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS)),
-		      HOST_GROUP0_MASK);
-
-	cdf_mdelay(100);
-
-	/* Clear FW_INDICATOR_ADDRESS */
-	if (HAS_FW_INDICATOR) {
-		fw_indicator = hif_read32_mb(mem + FW_INDICATOR_ADDRESS);
-		hif_write32_mb(mem + FW_INDICATOR_ADDRESS, 0);
-	}
-
-	/* Clear Target LF Timer interrupts */
-	val =
-		hif_read32_mb(mem +
-			     (RTC_SOC_BASE_ADDRESS +
-			      SOC_LF_TIMER_CONTROL0_ADDRESS));
-	HIF_INFO_MED("%s: addr 0x%x :  0x%x", __func__,
-	       (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS), val);
-	val &= ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
-	hif_write32_mb(mem +
-		      (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS),
-		      val);
-
-	/* Reset CE */
-	val =
-		hif_read32_mb(mem +
-			     (RTC_SOC_BASE_ADDRESS |
-			      SOC_RESET_CONTROL_ADDRESS));
-	val |= SOC_RESET_CONTROL_CE_RST_MASK;
-	hif_write32_mb((mem +
-		       (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS)),
-		      val);
-	val =
-		hif_read32_mb(mem +
-			     (RTC_SOC_BASE_ADDRESS |
-			      SOC_RESET_CONTROL_ADDRESS));
-	cdf_mdelay(10);
-
-	/* CE unreset */
-	val &= ~SOC_RESET_CONTROL_CE_RST_MASK;
-	hif_write32_mb(mem + (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS),
-		      val);
-	val =
-		hif_read32_mb(mem +
-			     (RTC_SOC_BASE_ADDRESS |
-			      SOC_RESET_CONTROL_ADDRESS));
-	cdf_mdelay(10);
-
-	/* Read Target CPU Intr Cause */
-	val = hif_read32_mb(mem + (SOC_CORE_BASE_ADDRESS | CPU_INTR_ADDRESS));
-	HIF_INFO_MED("%s: Target CPU Intr Cause after CE reset 0x%x",
-		    __func__, val);
-
-	/* CPU warm RESET */
-	val =
-		hif_read32_mb(mem +
-			     (RTC_SOC_BASE_ADDRESS |
-			      SOC_RESET_CONTROL_ADDRESS));
-	val |= SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
-	hif_write32_mb(mem + (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS),
-		      val);
-	val =
-		hif_read32_mb(mem +
-			     (RTC_SOC_BASE_ADDRESS |
-			      SOC_RESET_CONTROL_ADDRESS));
-	HIF_INFO_MED("%s: RESET_CONTROL after cpu warm reset 0x%x",
-		    __func__, val);
-
-	cdf_mdelay(100);
-	HIF_INFO_MED("%s: Target Warm reset complete", __func__);
-
-}
-
-#ifndef QCA_WIFI_3_0
-int hif_check_fw_reg(struct ol_softc *scn)
-{
-	struct hif_pci_softc *sc = scn->hif_sc;
-	void __iomem *mem = sc->mem;
-	uint32_t val;
-
-	A_TARGET_ACCESS_BEGIN_RET(scn);
-	val = hif_read32_mb(mem + FW_INDICATOR_ADDRESS);
-	A_TARGET_ACCESS_END_RET(scn);
-
-	HIF_INFO_MED("%s: FW_INDICATOR register is 0x%x", __func__, val);
-
-	if (val & FW_IND_HELPER)
-		return 0;
-
-	return 1;
-}
-#endif
-
-int hif_check_soc_status(struct ol_softc *scn)
-{
-	uint16_t device_id;
-	uint32_t val;
-	uint16_t timeout_count = 0;
-	struct hif_pci_softc *sc = scn->hif_sc;
-
-	/* Check device ID from PCIe configuration space for link status */
-	pci_read_config_word(sc->pdev, PCI_DEVICE_ID, &device_id);
-	if (device_id != sc->devid) {
-		HIF_ERROR("%s: device ID does match (read 0x%x, expect 0x%x)",
-			  __func__, device_id, sc->devid);
-		return -EACCES;
-	}
-
-	/* Check PCIe local register for bar/memory access */
-	val = hif_read32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
-			   RTC_STATE_ADDRESS);
-	HIF_INFO_MED("%s: RTC_STATE_ADDRESS is %08x", __func__, val);
-
-	/* Try to wake up taget if it sleeps */
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
-		PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
-	HIF_INFO_MED("%s: PCIE_SOC_WAKE_ADDRESS is %08x", __func__,
-		hif_read32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
-		PCIE_SOC_WAKE_ADDRESS));
-
-	/* Check if taget can be woken up */
-	while (!hif_targ_is_awake(scn, sc->mem)) {
-		if (timeout_count >= PCIE_WAKE_TIMEOUT) {
-			HIF_ERROR("%s: wake up timeout, %08x, %08x",
-				__func__,
-				hif_read32_mb(sc->mem +
-					     PCIE_LOCAL_BASE_ADDRESS +
-					     RTC_STATE_ADDRESS),
-				hif_read32_mb(sc->mem +
-					     PCIE_LOCAL_BASE_ADDRESS +
-					PCIE_SOC_WAKE_ADDRESS));
-			return -EACCES;
-		}
-
-		hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
-			      PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
-
-		cdf_mdelay(100);
-		timeout_count += 100;
-	}
-
-	/* Check Power register for SoC internal bus issues */
-	val =
-		hif_read32_mb(sc->mem + RTC_SOC_BASE_ADDRESS +
-			     SOC_POWER_REG_OFFSET);
-	HIF_INFO_MED("%s: Power register is %08x", __func__, val);
-
-	return 0;
-}
-
-/**
- * hif_dump_pci_registers(): dump PCI debug registers
- *
- * This function dumps pci debug registers
- *
- * @scn: struct ol_softc
- *
- * Return: void
- */
-static void hif_dump_pci_registers(struct ol_softc *scn)
-{
-	struct hif_pci_softc *sc = scn->hif_sc;
-	void __iomem *mem = sc->mem;
-	uint32_t val, i, j;
-	uint32_t wrapper_idx[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9 };
-	uint32_t ce_base;
-
-	A_TARGET_ACCESS_BEGIN(scn);
-
-	/* DEBUG_INPUT_SEL_SRC = 0x6 */
-	val =
-		hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-			     WLAN_DEBUG_INPUT_SEL_OFFSET);
-	val &= ~WLAN_DEBUG_INPUT_SEL_SRC_MASK;
-	val |= WLAN_DEBUG_INPUT_SEL_SRC_SET(0x6);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_INPUT_SEL_OFFSET,
-		      val);
-
-	/* DEBUG_CONTROL_ENABLE = 0x1 */
-	val = hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-			   WLAN_DEBUG_CONTROL_OFFSET);
-	val &= ~WLAN_DEBUG_CONTROL_ENABLE_MASK;
-	val |= WLAN_DEBUG_CONTROL_ENABLE_SET(0x1);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS +
-		      WLAN_DEBUG_CONTROL_OFFSET, val);
-
-	HIF_INFO_MED("%s: Debug: inputsel: %x dbgctrl: %x", __func__,
-	       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-			    WLAN_DEBUG_INPUT_SEL_OFFSET),
-	       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-			    WLAN_DEBUG_CONTROL_OFFSET));
-
-	HIF_INFO_MED("%s: Debug CE", __func__);
-	/* Loop CE debug output */
-	/* AMBA_DEBUG_BUS_SEL = 0xc */
-	val = hif_read32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET);
-	val &= ~AMBA_DEBUG_BUS_SEL_MASK;
-	val |= AMBA_DEBUG_BUS_SEL_SET(0xc);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, val);
-
-	for (i = 0; i < sizeof(wrapper_idx) / sizeof(uint32_t); i++) {
-		/* For (i=1,2,3,4,8,9) write CE_WRAPPER_DEBUG_SEL = i */
-		val = hif_read32_mb(mem + CE_WRAPPER_BASE_ADDRESS +
-				   CE_WRAPPER_DEBUG_OFFSET);
-		val &= ~CE_WRAPPER_DEBUG_SEL_MASK;
-		val |= CE_WRAPPER_DEBUG_SEL_SET(wrapper_idx[i]);
-		hif_write32_mb(mem + CE_WRAPPER_BASE_ADDRESS +
-			      CE_WRAPPER_DEBUG_OFFSET, val);
-
-		HIF_INFO_MED("%s: ce wrapper: %d amdbg: %x cewdbg: %x",
-			    __func__, wrapper_idx[i],
-			    hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-				AMBA_DEBUG_BUS_OFFSET),
-			    hif_read32_mb(mem + CE_WRAPPER_BASE_ADDRESS +
-				CE_WRAPPER_DEBUG_OFFSET));
-
-		if (wrapper_idx[i] <= 7) {
-			for (j = 0; j <= 5; j++) {
-				ce_base = CE_BASE_ADDRESS(wrapper_idx[i]);
-				/* For (j=0~5) write CE_DEBUG_SEL = j */
-				val =
-					hif_read32_mb(mem + ce_base +
-						     CE_DEBUG_OFFSET);
-				val &= ~CE_DEBUG_SEL_MASK;
-				val |= CE_DEBUG_SEL_SET(j);
-				hif_write32_mb(mem + ce_base + CE_DEBUG_OFFSET,
-					      val);
-
-				/* read (@gpio_athr_wlan_reg)
-				 * WLAN_DEBUG_OUT_DATA */
-				val = hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-						   WLAN_DEBUG_OUT_OFFSET);
-				val = WLAN_DEBUG_OUT_DATA_GET(val);
-
-				HIF_INFO_MED("%s: module%d: cedbg: %x out: %x",
-					    __func__, j,
-					    hif_read32_mb(mem + ce_base +
-						    CE_DEBUG_OFFSET), val);
-			}
-		} else {
-			/* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */
-			val =
-				hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-					     WLAN_DEBUG_OUT_OFFSET);
-			val = WLAN_DEBUG_OUT_DATA_GET(val);
-
-			HIF_INFO_MED("%s: out: %x", __func__, val);
-		}
-	}
-
-	HIF_INFO_MED("%s: Debug PCIe:", __func__);
-	/* Loop PCIe debug output */
-	/* Write AMBA_DEBUG_BUS_SEL = 0x1c */
-	val = hif_read32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET);
-	val &= ~AMBA_DEBUG_BUS_SEL_MASK;
-	val |= AMBA_DEBUG_BUS_SEL_SET(0x1c);
-	hif_write32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, val);
-
-	for (i = 0; i <= 8; i++) {
-		/* For (i=1~8) write AMBA_DEBUG_BUS_PCIE_DEBUG_SEL = i */
-		val =
-			hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-				     AMBA_DEBUG_BUS_OFFSET);
-		val &= ~AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
-		val |= AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(i);
-		hif_write32_mb(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET,
-			      val);
-
-		/* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */
-		val =
-			hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-				     WLAN_DEBUG_OUT_OFFSET);
-		val = WLAN_DEBUG_OUT_DATA_GET(val);
-
-		HIF_INFO_MED("%s: amdbg: %x out: %x %x", __func__,
-		       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-				    WLAN_DEBUG_OUT_OFFSET), val,
-		       hif_read32_mb(mem + GPIO_BASE_ADDRESS +
-				    WLAN_DEBUG_OUT_OFFSET));
-	}
-
-	A_TARGET_ACCESS_END(scn);
-}
-
-/**
- * hif_dump_registers(): dump bus debug registers
- *
- * This function dumps hif bus debug registers
- *
- * @scn: struct ol_softc
- *
- * Return: 0 for success or error code
- */
-int hif_dump_registers(struct ol_softc *scn)
-{
-	int status;
-
-	status = hif_dump_ce_registers(scn);
-	if (status)
-		return status;
-	hif_dump_pci_registers(scn);
-
-	return 0;
-}
-
-/*
- * Handler for a per-engine interrupt on a PARTICULAR CE.
- * This is used in cases where each CE has a private
- * MSI interrupt.
- */
-static irqreturn_t ce_per_engine_handler(int irq, void *arg)
-{
-	struct hif_pci_softc *sc = (struct hif_pci_softc *)arg;
-	int CE_id = irq - MSI_ASSIGN_CE_INITIAL;
-
-	/*
-	 * NOTE: We are able to derive CE_id from irq because we
-	 * use a one-to-one mapping for CE's 0..5.
-	 * CE's 6 & 7 do not use interrupts at all.
-	 *
-	 * This mapping must be kept in sync with the mapping
-	 * used by firmware.
-	 */
-
-	ce_per_engine_service(sc->ol_sc, CE_id);
-
-	return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_SLUB_DEBUG_ON
-
-/* worker thread to schedule wlan_tasklet in SLUB debug build */
-static void reschedule_tasklet_work_handler(struct work_struct *recovery)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct hif_pci_softc *sc;
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: tasklet scn is null", __func__);
-		return;
-	}
-
-	sc = scn->hif_sc;
-
-	if (scn->hif_init_done == false) {
-		HIF_ERROR("%s: wlan driver is unloaded", __func__);
-		return;
-	}
-
-	tasklet_schedule(&sc->intr_tq);
-	return;
-}
-
-static DECLARE_WORK(reschedule_tasklet_work, reschedule_tasklet_work_handler);
-
-#endif
-
-static void wlan_tasklet(unsigned long data)
-{
-	struct hif_pci_softc *sc = (struct hif_pci_softc *)data;
-	struct ol_softc *scn = sc->ol_sc;
-
-	if (scn->hif_init_done == false)
-		goto end;
-
-	if (cdf_atomic_read(&scn->link_suspended))
-		goto end;
-
-	if (!ADRASTEA_BU) {
-		(irqreturn_t) hif_fw_interrupt_handler(sc->irq_event, scn);
-		if (sc->ol_sc->target_status == OL_TRGET_STATUS_RESET)
-			goto end;
-	}
-
-end:
-	cdf_atomic_set(&scn->tasklet_from_intr, 0);
-	cdf_atomic_dec(&scn->active_tasklet_cnt);
-}
-
-#ifdef FEATURE_RUNTIME_PM
-#define HIF_PCI_RUNTIME_PM_STATS(_s, _sc, _name) \
-	seq_printf(_s, "%30s: %u\n", #_name, _sc->pm_stats._name)
-
-/**
- * hif_pci_runtime_pm_warn() - Runtime PM Debugging API
- * @sc: hif_pci_softc context
- * @msg: log message
- *
- * log runtime pm stats when something seems off.
- *
- * Return: void
- */
-void hif_pci_runtime_pm_warn(struct hif_pci_softc *sc, const char *msg)
-{
-	struct hif_pm_runtime_lock *ctx;
-
-	HIF_ERROR("%s: usage_count: %d, pm_state: %d, prevent_suspend_cnt: %d",
-			msg, atomic_read(&sc->dev->power.usage_count),
-			atomic_read(&sc->pm_state),
-			sc->prevent_suspend_cnt);
-
-	HIF_ERROR("runtime_status: %d, runtime_error: %d, disable_depth: %d autosuspend_delay: %d",
-			sc->dev->power.runtime_status,
-			sc->dev->power.runtime_error,
-			sc->dev->power.disable_depth,
-			sc->dev->power.autosuspend_delay);
-
-	HIF_ERROR("runtime_get: %u, runtime_put: %u, request_resume: %u",
-			sc->pm_stats.runtime_get, sc->pm_stats.runtime_put,
-			sc->pm_stats.request_resume);
-
-	HIF_ERROR("allow_suspend: %u, prevent_suspend: %u",
-			sc->pm_stats.allow_suspend,
-			sc->pm_stats.prevent_suspend);
-
-	HIF_ERROR("prevent_suspend_timeout: %u, allow_suspend_timeout: %u",
-			sc->pm_stats.prevent_suspend_timeout,
-			sc->pm_stats.allow_suspend_timeout);
-
-	HIF_ERROR("Suspended: %u, resumed: %u count",
-			sc->pm_stats.suspended,
-			sc->pm_stats.resumed);
-
-	HIF_ERROR("suspend_err: %u, runtime_get_err: %u",
-			sc->pm_stats.suspend_err,
-			sc->pm_stats.runtime_get_err);
-
-	HIF_ERROR("Active Wakeup Sources preventing Runtime Suspend: ");
-
-	list_for_each_entry(ctx, &sc->prevent_suspend_list, list) {
-		HIF_ERROR("source %s; timeout %d ms", ctx->name, ctx->timeout);
-	}
-
-	WARN_ON(1);
-}
-
-/**
- * hif_pci_pm_runtime_debugfs_show(): show debug stats for runtimepm
- * @s: file to print to
- * @data: unused
- *
- * debugging tool added to the debug fs for displaying runtimepm stats
- *
- * Return: 0
- */
-static int hif_pci_pm_runtime_debugfs_show(struct seq_file *s, void *data)
-{
-	struct hif_pci_softc *sc = s->private;
-	static const char * const autopm_state[] = {"NONE", "ON", "INPROGRESS",
-		"SUSPENDED"};
-	unsigned int msecs_age;
-	int pm_state = atomic_read(&sc->pm_state);
-	unsigned long timer_expires, flags;
-	struct hif_pm_runtime_lock *ctx;
-
-	seq_printf(s, "%30s: %s\n", "Runtime PM state",
-			autopm_state[pm_state]);
-	seq_printf(s, "%30s: %pf\n", "Last Resume Caller",
-			sc->pm_stats.last_resume_caller);
-
-	if (pm_state == HIF_PM_RUNTIME_STATE_SUSPENDED) {
-		msecs_age = jiffies_to_msecs(
-				jiffies - sc->pm_stats.suspend_jiffies);
-		seq_printf(s, "%30s: %d.%03ds\n", "Suspended Since",
-				msecs_age / 1000, msecs_age % 1000);
-	}
-
-	seq_printf(s, "%30s: %d\n", "PM Usage count",
-			atomic_read(&sc->dev->power.usage_count));
-
-	seq_printf(s, "%30s: %u\n", "prevent_suspend_cnt",
-			sc->prevent_suspend_cnt);
-
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, suspended);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, suspend_err);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, resumed);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, runtime_get);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, runtime_put);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, request_resume);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, prevent_suspend);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, allow_suspend);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, prevent_suspend_timeout);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, allow_suspend_timeout);
-	HIF_PCI_RUNTIME_PM_STATS(s, sc, runtime_get_err);
-
-	timer_expires = sc->runtime_timer_expires;
-	if (timer_expires > 0) {
-		msecs_age = jiffies_to_msecs(timer_expires - jiffies);
-		seq_printf(s, "%30s: %d.%03ds\n", "Prevent suspend timeout",
-				msecs_age / 1000, msecs_age % 1000);
-	}
-
-	spin_lock_irqsave(&sc->runtime_lock, flags);
-	if (list_empty(&sc->prevent_suspend_list)) {
-		spin_unlock_irqrestore(&sc->runtime_lock, flags);
-		return 0;
-	}
-
-	seq_printf(s, "%30s: ", "Active Wakeup_Sources");
-	list_for_each_entry(ctx, &sc->prevent_suspend_list, list) {
-		seq_printf(s, "%s", ctx->name);
-		if (ctx->timeout)
-			seq_printf(s, "(%d ms)", ctx->timeout);
-		seq_puts(s, " ");
-	}
-	seq_puts(s, "\n");
-	spin_unlock_irqrestore(&sc->runtime_lock, flags);
-
-	return 0;
-}
-#undef HIF_PCI_RUNTIME_PM_STATS
-
-/**
- * hif_pci_autopm_open() - open a debug fs file to access the runtime pm stats
- * @inode
- * @file
- *
- * Return: linux error code of single_open.
- */
-static int hif_pci_runtime_pm_open(struct inode *inode, struct file *file)
-{
-	return single_open(file, hif_pci_pm_runtime_debugfs_show,
-			inode->i_private);
-}
-
-#ifdef WLAN_OPEN_SOURCE
-static const struct file_operations hif_pci_runtime_pm_fops = {
-	.owner          = THIS_MODULE,
-	.open           = hif_pci_runtime_pm_open,
-	.release        = single_release,
-	.read           = seq_read,
-	.llseek         = seq_lseek,
-};
-
-/**
- * hif_runtime_pm_debugfs_create() - creates runtimepm debugfs entry
- * @sc: pci context
- *
- * creates a debugfs entry to debug the runtime pm feature.
- */
-static void hif_runtime_pm_debugfs_create(struct hif_pci_softc *sc)
-{
-	sc->pm_dentry = debugfs_create_file("cnss_runtime_pm",
-					S_IRUSR, NULL, sc,
-					&hif_pci_runtime_pm_fops);
-}
-/**
- * hif_runtime_pm_debugfs_remove() - removes runtimepm debugfs entry
- * @sc: pci context
- *
- * removes the debugfs entry to debug the runtime pm feature.
- */
-static void hif_runtime_pm_debugfs_remove(struct hif_pci_softc *sc)
-{
-	debugfs_remove(sc->pm_dentry);
-}
-#else
-static inline void hif_runtime_pm_debugfs_create(struct hif_pci_softc *sc)
-{
-}
-static inline void hif_runtime_pm_debugfs_remove(struct hif_pci_softc *sc)
-{
-}
-#endif
-
-static void hif_pm_runtime_lock_timeout_fn(unsigned long data);
-
-/**
- * hif_pm_runtime_start(): start the runtime pm
- * @sc: pci context
- *
- * After this call, runtime pm will be active.
- */
-static void hif_pm_runtime_start(struct hif_pci_softc *sc)
-{
-	struct ol_softc *ol_sc;
-
-	ol_sc = sc->ol_sc;
-
-	if (!ol_sc->enable_runtime_pm) {
-		HIF_INFO("%s: RUNTIME PM is disabled in ini\n", __func__);
-		return;
-	}
-
-	if (cds_get_conparam() == CDF_FTM_MODE ||
-			WLAN_IS_EPPING_ENABLED(cds_get_conparam())) {
-		HIF_INFO("%s: RUNTIME PM is disabled for FTM/EPPING mode\n",
-				__func__);
-		return;
-	}
-
-	setup_timer(&sc->runtime_timer, hif_pm_runtime_lock_timeout_fn,
-			(unsigned long)sc);
-
-	HIF_INFO("%s: Enabling RUNTIME PM, Delay: %d ms", __func__,
-			ol_sc->runtime_pm_delay);
-
-	cnss_runtime_init(sc->dev, ol_sc->runtime_pm_delay);
-	cdf_atomic_set(&sc->pm_state, HIF_PM_RUNTIME_STATE_ON);
-	hif_runtime_pm_debugfs_create(sc);
-}
-
-/**
- * hif_pm_runtime_stop(): stop runtime pm
- * @sc: pci context
- *
- * Turns off runtime pm and frees corresponding resources
- * that were acquired by hif_runtime_pm_start().
- */
-static void hif_pm_runtime_stop(struct hif_pci_softc *sc)
-{
-	struct ol_softc *ol_sc = sc->ol_sc;
-
-	if (!ol_sc->enable_runtime_pm)
-		return;
-
-	if (cds_get_conparam() == CDF_FTM_MODE ||
-			WLAN_IS_EPPING_ENABLED(cds_get_conparam()))
-		return;
-
-	cnss_runtime_exit(sc->dev);
-	cnss_pm_runtime_request(sc->dev, CNSS_PM_RUNTIME_RESUME);
-
-	cdf_atomic_set(&sc->pm_state, HIF_PM_RUNTIME_STATE_NONE);
-
-	hif_runtime_pm_debugfs_remove(sc);
-	del_timer_sync(&sc->runtime_timer);
-	/* doesn't wait for penting trafic unlike cld-2.0 */
-}
-
-/**
- * hif_pm_runtime_open(): initialize runtime pm
- * @sc: pci data structure
- *
- * Early initialization
- */
-static void hif_pm_runtime_open(struct hif_pci_softc *sc)
-{
-	spin_lock_init(&sc->runtime_lock);
-
-	cdf_atomic_init(&sc->pm_state);
-	sc->prevent_linkdown_lock =
-		hif_runtime_lock_init("linkdown suspend disabled");
-	cdf_atomic_set(&sc->pm_state, HIF_PM_RUNTIME_STATE_NONE);
-	INIT_LIST_HEAD(&sc->prevent_suspend_list);
-}
-
-/**
- * hif_pm_runtime_close(): close runtime pm
- * @sc: pci bus handle
- *
- * ensure runtime_pm is stopped before closing the driver
- */
-static void hif_pm_runtime_close(struct hif_pci_softc *sc)
-{
-	if (cdf_atomic_read(&sc->pm_state) == HIF_PM_RUNTIME_STATE_NONE)
-		return;
-	else
-		hif_pm_runtime_stop(sc);
-}
-
-
-#else
-
-static void hif_pm_runtime_close(struct hif_pci_softc *sc) {}
-static void hif_pm_runtime_open(struct hif_pci_softc *sc) {}
-static void hif_pm_runtime_start(struct hif_pci_softc *sc) {}
-static void hif_pm_runtime_stop(struct hif_pci_softc *sc) {}
-#endif
-
-/**
- * hif_enable_power_management(): enable power management
- * @hif_ctx: hif context
- *
- * Currently only does runtime pm.  Eventually this function could
- * consolidate other power state features such as only letting
- * the soc sleep after the driver finishes loading and re-enabling
- * aspm (hif_enable_power_gating).
- */
-void hif_enable_power_management(void *hif_ctx)
-{
-	struct hif_pci_softc *pci_ctx;
-
-	if (hif_ctx == NULL) {
-		HIF_ERROR("%s, hif_ctx null", __func__);
-		return;
-	}
-
-	pci_ctx = ((struct ol_softc *)hif_ctx)->hif_sc;
-
-	hif_pm_runtime_start(pci_ctx);
-}
-
-/**
- * hif_disable_power_management(): disable power management
- * @hif_ctx: hif context
- *
- * Currently disables runtime pm. Should be updated to behave
- * if runtime pm is not started. Should be updated to take care
- * of aspm and soc sleep for driver load.
- */
-void hif_disable_power_management(void *hif_ctx)
-{
-	struct hif_pci_softc *pci_ctx;
-
-	if (hif_ctx == NULL) {
-		HIF_ERROR("%s, hif_ctx null", __func__);
-		return;
-	}
-
-	pci_ctx = ((struct ol_softc *)hif_ctx)->hif_sc;
-
-	hif_pm_runtime_stop(pci_ctx);
-}
-
-#define ATH_PCI_PROBE_RETRY_MAX 3
-/**
- * hif_bus_open(): hif_bus_open
- * @scn: scn
- * @bus_type: bus type
- *
- * Return: n/a
- */
-CDF_STATUS hif_bus_open(struct ol_softc *ol_sc, enum ath_hal_bus_type bus_type)
-{
-	struct hif_pci_softc *sc;
-
-	sc = cdf_mem_malloc(sizeof(*sc));
-	if (!sc) {
-		HIF_ERROR("%s: no mem", __func__);
-		return CDF_STATUS_E_NOMEM;
-	}
-	ol_sc->hif_sc = (void *)sc;
-	sc->ol_sc = ol_sc;
-	ol_sc->bus_type = bus_type;
-	hif_pm_runtime_open(sc);
-
-	cdf_spinlock_init(&ol_sc->irq_lock);
-
-	return CDF_STATUS_SUCCESS;
-}
-
-/**
- * hif_bus_close(): hif_bus_close
- *
- * Return: n/a
- */
-void hif_bus_close(struct ol_softc *ol_sc)
-{
-	struct hif_pci_softc *sc;
-
-	if (ol_sc == NULL) {
-		HIF_ERROR("%s: ol_softc is NULL", __func__);
-		return;
-	}
-	sc = ol_sc->hif_sc;
-	if (sc == NULL)
-		return;
-
-	hif_pm_runtime_close(sc);
-	cdf_mem_free(sc);
-	ol_sc->hif_sc = NULL;
-}
-
-#define BAR_NUM 0
-
-int hif_enable_pci(struct hif_pci_softc *sc,
-		struct pci_dev *pdev,
-		const struct pci_device_id *id)
-{
-	void __iomem *mem;
-	int ret = 0;
-	uint16_t device_id;
-	struct ol_softc *ol_sc = sc->ol_sc;
-
-	pci_read_config_word(pdev,PCI_DEVICE_ID,&device_id);
-	if(device_id != id->device)  {
-		HIF_ERROR(
-		   "%s: dev id mismatch, config id = 0x%x, probing id = 0x%x",
-		   __func__, device_id, id->device);
-		/* pci link is down, so returing with error code */
-		return -EIO;
-	}
-
-	/* FIXME: temp. commenting out assign_resource
-	 * call for dev_attach to work on 2.6.38 kernel
-	 */
-#if (!defined(__LINUX_ARM_ARCH__))
-	if (pci_assign_resource(pdev, BAR_NUM)) {
-		HIF_ERROR("%s: pci_assign_resource error", __func__);
-		return -EIO;
-	}
-#endif
-	if (pci_enable_device(pdev)) {
-		HIF_ERROR("%s: pci_enable_device error",
-			   __func__);
-		return -EIO;
-	}
-
-	/* Request MMIO resources */
-	ret = pci_request_region(pdev, BAR_NUM, "ath");
-	if (ret) {
-		HIF_ERROR("%s: PCI MMIO reservation error", __func__);
-		ret = -EIO;
-		goto err_region;
-	}
-#ifdef CONFIG_ARM_LPAE
-	/* if CONFIG_ARM_LPAE is enabled, we have to set 64 bits mask
-	 * for 32 bits device also. */
-	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
-	if (ret) {
-		HIF_ERROR("%s: Cannot enable 64-bit pci DMA", __func__);
-		goto err_dma;
-	}
-	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
-	if (ret) {
-		HIF_ERROR("%s: Cannot enable 64-bit DMA", __func__);
-		goto err_dma;
-	}
-#else
-	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
-	if (ret) {
-		HIF_ERROR("%s: Cannot enable 32-bit pci DMA", __func__);
-		goto err_dma;
-	}
-	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
-	if (ret) {
-		HIF_ERROR("%s: Cannot enable 32-bit consistent DMA!",
-			   __func__);
-		goto err_dma;
-	}
-#endif
-
-	PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, 0x188);
-
-	/* Set bus master bit in PCI_COMMAND to enable DMA */
-	pci_set_master(pdev);
-
-	/* Arrange for access to Target SoC registers. */
-	mem = pci_iomap(pdev, BAR_NUM, 0);
-	if (!mem) {
-		HIF_ERROR("%s: PCI iomap error", __func__);
-		ret = -EIO;
-		goto err_iomap;
-	}
-	sc->mem = mem;
-	sc->pdev = pdev;
-	sc->dev = &pdev->dev;
-	ol_sc->aps_osdev.bdev = pdev;
-	ol_sc->aps_osdev.device = &pdev->dev;
-	ol_sc->aps_osdev.bc.bc_handle = (void *)mem;
-	ol_sc->aps_osdev.bc.bc_bustype = HAL_BUS_TYPE_PCI;
-	sc->devid = id->device;
-	sc->cacheline_sz = dma_get_cache_alignment();
-	/* Get RAM dump memory address and size */
-	GET_VIRT_RAMDUMP_MEM(ol_sc);
-	ol_sc->mem = mem;
-	sc->pci_enabled = true;
-	return ret;
-
-err_iomap:
-	pci_clear_master(pdev);
-err_dma:
-	pci_release_region(pdev, BAR_NUM);
-err_region:
-	pci_disable_device(pdev);
-	return ret;
-}
-
-void hif_disable_pci(struct hif_pci_softc *sc)
-{
-	struct ol_softc *ol_sc;
-
-	if (!sc)
-		return;
-
-	ol_sc = sc->ol_sc;
-	if (ol_sc == NULL) {
-		HIF_ERROR("%s: ol_sc = NULL", __func__);
-		return;
-	}
-	pci_set_drvdata(sc->pdev, NULL);
-	hif_pci_device_reset(sc);
-	pci_iounmap(sc->pdev, sc->mem);
-	sc->mem = NULL;
-	ol_sc->mem = NULL;
-	pci_clear_master(sc->pdev);
-	pci_release_region(sc->pdev, BAR_NUM);
-	pci_disable_device(sc->pdev);
-}
-
-int hif_pci_probe_tgt_wakeup(struct hif_pci_softc *sc)
-{
-	int ret = 0;
-	int targ_awake_limit = 500;
-#ifndef QCA_WIFI_3_0
-	uint32_t fw_indicator;
-#endif
-	struct ol_softc *scn = sc->ol_sc;
-	/*
-	 * Verify that the Target was started cleanly.*
-	 * The case where this is most likely is with an AUX-powered
-	 * Target and a Host in WoW mode. If the Host crashes,
-	 * loses power, or is restarted (without unloading the driver)
-	 * then the Target is left (aux) powered and running.  On a
-	 * subsequent driver load, the Target is in an unexpected state.
-	 * We try to catch that here in order to reset the Target and
-	 * retry the probe.
-	 */
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
-				  PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_V_MASK);
-	while (!hif_targ_is_awake(scn, sc->mem)) {
-		if (0 == targ_awake_limit) {
-			HIF_ERROR("%s: target awake timeout", __func__);
-			ret = -EAGAIN;
-			goto end;
-		}
-		cdf_mdelay(1);
-		targ_awake_limit--;
-	}
-
-#if PCIE_BAR0_READY_CHECKING
-	{
-		int wait_limit = 200;
-		/* Synchronization point: wait the BAR0 is configured */
-		while (wait_limit-- &&
-			   !(hif_read32_mb(sc->mem +
-					  PCIE_LOCAL_BASE_ADDRESS +
-					  PCIE_SOC_RDY_STATUS_ADDRESS) \
-					  & PCIE_SOC_RDY_STATUS_BAR_MASK)) {
-			cdf_mdelay(10);
-		}
-		if (wait_limit < 0) {
-			/* AR6320v1 doesn't support checking of BAR0 configuration,
-				 takes one sec to wait BAR0 ready */
-			HIF_INFO_MED("%s: AR6320v1 waits two sec for BAR0",
-				    __func__);
-		}
-    }
-#endif
-
-#ifndef QCA_WIFI_3_0
-	fw_indicator = hif_read32_mb(sc->mem + FW_INDICATOR_ADDRESS);
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
-				  PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
-
-	if (fw_indicator & FW_IND_INITIALIZED) {
-		HIF_ERROR("%s: Target is in an unknown state. EAGAIN",
-			   __func__);
-		ret = -EAGAIN;
-		goto end;
-	}
-#endif
-
-end:
-	return ret;
-}
-
-static void wlan_tasklet_msi(unsigned long data)
-{
-	struct hif_tasklet_entry *entry = (struct hif_tasklet_entry *)data;
-	struct hif_pci_softc *sc = (struct hif_pci_softc *) entry->hif_handler;
-	struct ol_softc *scn = sc->ol_sc;
-
-	if (sc->ol_sc->hif_init_done == false)
-		goto irq_handled;
-
-	if (cdf_atomic_read(&sc->ol_sc->link_suspended))
-		goto irq_handled;
-
-	cdf_atomic_inc(&scn->active_tasklet_cnt);
-
-	if (entry->id == HIF_MAX_TASKLET_NUM) {
-		/* the last tasklet is for fw IRQ */
-		(irqreturn_t)hif_fw_interrupt_handler(sc->irq_event, sc->ol_sc);
-		if (sc->ol_sc->target_status == OL_TRGET_STATUS_RESET)
-			goto irq_handled;
-	} else if (entry->id < sc->ol_sc->ce_count) {
-		ce_per_engine_service(sc->ol_sc, entry->id);
-	} else {
-		HIF_ERROR("%s: ERROR - invalid CE_id = %d",
-		       __func__, entry->id);
-	}
-	return;
-
-irq_handled:
-	cdf_atomic_dec(&scn->active_tasklet_cnt);
-
-}
-
-int hif_configure_msi(struct hif_pci_softc *sc)
-{
-	int ret = 0;
-	int num_msi_desired;
-	int rv = -1;
-	struct ol_softc *scn = sc->ol_sc;
-
-	HIF_TRACE("%s: E", __func__);
-
-	num_msi_desired = MSI_NUM_REQUEST; /* Multiple MSI */
-	if (num_msi_desired < 1) {
-		HIF_ERROR("%s: MSI is not configured", __func__);
-		return -EINVAL;
-	}
-
-	if (num_msi_desired > 1) {
-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
-		rv = pci_enable_msi_range(sc->pdev, num_msi_desired,
-						num_msi_desired);
-#else
-		rv = pci_enable_msi_block(sc->pdev, num_msi_desired);
-#endif
-	}
-	HIF_TRACE("%s: num_msi_desired = %d, available_msi = %d",
-		  __func__, num_msi_desired, rv);
-
-	if (rv == 0 || rv >= HIF_MAX_TASKLET_NUM) {
-		int i;
-
-		sc->num_msi_intrs = HIF_MAX_TASKLET_NUM;
-		sc->tasklet_entries[HIF_MAX_TASKLET_NUM -1].hif_handler =
-			(void *)sc;
-		sc->tasklet_entries[HIF_MAX_TASKLET_NUM -1].id =
-			HIF_MAX_TASKLET_NUM;
-		tasklet_init(&sc->intr_tq, wlan_tasklet_msi,
-			 (unsigned long)&sc->tasklet_entries[
-			 HIF_MAX_TASKLET_NUM -1]);
-		ret = request_irq(sc->pdev->irq + MSI_ASSIGN_FW,
-				  hif_pci_msi_fw_handler,
-				  IRQF_SHARED, "wlan_pci", sc);
-		if(ret) {
-			HIF_ERROR("%s: request_irq failed", __func__);
-			goto err_intr;
-		}
-		for (i = 0; i <= scn->ce_count; i++) {
-			sc->tasklet_entries[i].hif_handler = (void *)sc;
-			sc->tasklet_entries[i].id = i;
-			tasklet_init(&sc->intr_tq, wlan_tasklet_msi,
-				 (unsigned long)&sc->tasklet_entries[i]);
-			ret = request_irq((sc->pdev->irq +
-					   i + MSI_ASSIGN_CE_INITIAL),
-					  ce_per_engine_handler, IRQF_SHARED,
-					  "wlan_pci", sc);
-			if(ret) {
-				HIF_ERROR("%s: request_irq failed", __func__);
-				goto err_intr;
-			}
-		}
-	} else if (rv > 0) {
-		HIF_TRACE("%s: use single msi", __func__);
-
-		if ((ret = pci_enable_msi(sc->pdev)) < 0) {
-			HIF_ERROR("%s: single MSI allocation failed",
-				  __func__);
-			/* Try for legacy PCI line interrupts */
-			sc->num_msi_intrs = 0;
-		} else {
-			sc->num_msi_intrs = 1;
-			tasklet_init(&sc->intr_tq,
-				wlan_tasklet, (unsigned long)sc);
-			ret = request_irq(sc->pdev->irq,
-					  hif_pci_interrupt_handler,
-					  IRQF_SHARED, "wlan_pci", sc);
-			if(ret) {
-				HIF_ERROR("%s: request_irq failed", __func__);
-				goto err_intr;
-			}
-		}
-	} else {
-		sc->num_msi_intrs = 0;
-		ret = -EIO;
-		HIF_ERROR("%s: do not support MSI, rv = %d", __func__, rv);
-	}
-	if ((ret = pci_enable_msi(sc->pdev)) < 0) {
-		HIF_ERROR("%s: single MSI interrupt allocation failed",
-			  __func__);
-		/* Try for legacy PCI line interrupts */
-		sc->num_msi_intrs = 0;
-	} else {
-		sc->num_msi_intrs = 1;
-		tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc);
-		ret = request_irq(sc->pdev->irq,
-				  hif_pci_interrupt_handler, IRQF_SHARED,
-				  "wlan_pci", sc);
-		if(ret) {
-			HIF_ERROR("%s: request_irq failed", __func__);
-			goto err_intr;
-		}
-	}
-
-	if (ret == 0) {
-		hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
-			  PCIE_INTR_ENABLE_ADDRESS),
-			  HOST_GROUP0_MASK);
-		hif_write32_mb(sc->mem +
-			  PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS,
-			  PCIE_SOC_WAKE_RESET);
-	}
-	HIF_TRACE("%s: X, ret = %d", __func__, ret);
-
-	return ret;
-
-err_intr:
-if (sc->num_msi_intrs >= 1)
-		pci_disable_msi(sc->pdev);
-	return ret;
-}
-
-static int hif_pci_configure_legacy_irq(struct hif_pci_softc *sc)
-{
-	int ret = 0;
-	struct ol_softc *scn = sc->ol_sc;
-
-	HIF_TRACE("%s: E", __func__);
-
-	/* do notn support MSI or MSI IRQ failed */
-	tasklet_init(&sc->intr_tq, wlan_tasklet, (unsigned long)sc);
-	ret = request_irq(sc->pdev->irq,
-			  hif_pci_interrupt_handler, IRQF_SHARED,
-			  "wlan_pci", sc);
-	if(ret) {
-		HIF_ERROR("%s: request_irq failed, ret = %d", __func__, ret);
-		goto end;
-	}
-	/* Use Legacy PCI Interrupts */
-	hif_write32_mb(sc->mem+(SOC_CORE_BASE_ADDRESS |
-		  PCIE_INTR_ENABLE_ADDRESS),
-		  HOST_GROUP0_MASK);
-	hif_write32_mb(sc->mem + PCIE_LOCAL_BASE_ADDRESS +
-		      PCIE_SOC_WAKE_ADDRESS,
-		  PCIE_SOC_WAKE_RESET);
-end:
-	CDF_TRACE(CDF_MODULE_ID_HIF, CDF_TRACE_LEVEL_ERROR,
-			  "%s: X, ret = %d", __func__, ret);
-	return ret;
-}
-
-/**
- * hif_nointrs(): disable IRQ
- *
- * This function stops interrupt(s)
- *
- * @scn: struct ol_softc
- *
- * Return: none
- */
-void hif_nointrs(struct ol_softc *scn)
-{
-	int i;
-	struct hif_pci_softc *sc = scn->hif_sc;
-
-	if (scn->request_irq_done == false)
-		return;
-	if (sc->num_msi_intrs > 0) {
-		/* MSI interrupt(s) */
-		for (i = 0; i < sc->num_msi_intrs; i++) {
-			free_irq(sc->pdev->irq + i, sc);
-		}
-		sc->num_msi_intrs = 0;
-	} else {
-		/* Legacy PCI line interrupt */
-		free_irq(sc->pdev->irq, sc);
-	}
-	ce_unregister_irq(scn->hif_hdl, 0xfff);
-	scn->request_irq_done = false;
-}
-
-/**
- * hif_disable_bus(): hif_disable_bus
- *
- * This function disables the bus
- *
- * @bdev: bus dev
- *
- * Return: none
- */
-void hif_disable_bus(void *bdev)
-{
-	struct pci_dev *pdev = bdev;
-	struct hif_pci_softc *sc = pci_get_drvdata(pdev);
-	struct ol_softc *scn;
-	void __iomem *mem;
-
-	/* Attach did not succeed, all resources have been
-	 * freed in error handler
-	 */
-	if (!sc)
-		return;
-
-	scn = sc->ol_sc;
-
-	if (ADRASTEA_BU) {
-		hif_write32_mb(sc->mem + PCIE_INTR_ENABLE_ADDRESS, 0);
-		hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS,
-			       HOST_GROUP0_MASK);
-	}
-
-	mem = (void __iomem *)sc->mem;
-	if (mem) {
-		pci_disable_msi(pdev);
-		hif_dump_pipe_debug_count(scn);
-		hif_deinit_cdf_ctx(scn);
-		if (scn->athdiag_procfs_inited) {
-			athdiag_procfs_remove();
-			scn->athdiag_procfs_inited = false;
-		}
-		pci_set_drvdata(pdev, NULL);
-		pci_iounmap(pdev, mem);
-		scn->mem = NULL;
-		pci_release_region(pdev, BAR_NUM);
-		pci_clear_master(pdev);
-		pci_disable_device(pdev);
-	}
-	HIF_INFO("%s: X", __func__);
-}
-
-#define OL_ATH_PCI_PM_CONTROL 0x44
-
-#ifdef FEATURE_RUNTIME_PM
-/**
- * hif_runtime_prevent_linkdown() - prevent or allow a runtime pm from occuring
- * @scn: hif context
- * @flag: prevent linkdown if true otherwise allow
- *
- * this api should only be called as part of bus prevent linkdown
- */
-static void hif_runtime_prevent_linkdown(struct ol_softc *scn, bool flag)
-{
-	struct hif_pci_softc *sc = scn->hif_sc;
-
-	if (flag)
-		hif_pm_runtime_prevent_suspend(scn, sc->prevent_linkdown_lock);
-	else
-		hif_pm_runtime_allow_suspend(scn, sc->prevent_linkdown_lock);
-}
-#else
-static void hif_runtime_prevent_linkdown(struct ol_softc *scn, bool flag)
-{
-}
-#endif
-
-#if defined(CONFIG_CNSS) && defined(CONFIG_PCI_MSM)
-/**
- * hif_bus_prevent_linkdown(): allow or permit linkdown
- * @flag: true prevents linkdown, false allows
- *
- * Calls into the platform driver to vote against taking down the
- * pcie link.
- *
- * Return: n/a
- */
-void hif_bus_prevent_linkdown(struct ol_softc *scn, bool flag)
-{
-	HIF_ERROR("wlan: %s pcie power collapse",
-			(flag ? "disable" : "enable"));
-	hif_runtime_prevent_linkdown(scn, flag);
-	cnss_wlan_pm_control(flag);
-}
-#else
-void hif_bus_prevent_linkdown(struct ol_softc *scn, bool flag)
-{
-	HIF_ERROR("wlan: %s pcie power collapse",
-			(flag ? "disable" : "enable"));
-	hif_runtime_prevent_linkdown(scn, flag);
-}
-#endif
-
-/**
- * hif_drain_tasklets(): wait untill no tasklet is pending
- * @scn: hif context
- *
- * Let running tasklets clear pending trafic.
- *
- * Return: 0 if no bottom half is in progress when it returns.
- *   -EFAULT if it times out.
- */
-static inline int hif_drain_tasklets(struct ol_softc *scn)
-{
-	uint32_t ce_drain_wait_cnt = 0;
-
-	while (cdf_atomic_read(&scn->active_tasklet_cnt)) {
-		if (++ce_drain_wait_cnt > HIF_CE_DRAIN_WAIT_CNT) {
-			HIF_ERROR("%s: CE still not done with access",
-			       __func__);
-
-			return -EFAULT;
-		}
-		HIF_INFO("%s: Waiting for CE to finish access", __func__);
-		msleep(10);
-	}
-	return 0;
-}
-
-/**
- * hif_bus_suspend_link_up() - suspend the bus
- *
- * Configures the pci irq line as a wakeup source.
- *
- * Return: 0 for success and non-zero for failure
- */
-static int hif_bus_suspend_link_up(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct pci_dev *pdev;
-	int status;
-
-	if (!scn)
-		return -EFAULT;
-
-	pdev = scn->aps_osdev.bdev;
-
-	status = hif_drain_tasklets(scn);
-	if (status != 0)
-		return status;
-
-	if (unlikely(enable_irq_wake(pdev->irq))) {
-		HIF_ERROR("%s: Fail to enable wake IRQ!", __func__);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-/**
- * hif_bus_resume_link_up() - hif bus resume API
- *
- * This function disables the wakeup source.
- *
- * Return: 0 for success and non-zero for failure
- */
-static int hif_bus_resume_link_up(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct pci_dev *pdev;
-
-	if (!scn)
-		return -EFAULT;
-
-	pdev = scn->aps_osdev.bdev;
-	if (!pdev) {
-		HIF_ERROR("%s: pci_dev is null", __func__);
-		return -EFAULT;
-	}
-
-	if (unlikely(disable_irq_wake(pdev->irq))) {
-		HIF_ERROR("%s: Fail to disable wake IRQ!", __func__);
-		return -EFAULT;
-	}
-
-	return 0;
-}
-
-/**
- * hif_bus_suspend_link_down() - suspend the bus
- *
- * Suspends the hif layer taking care of draining recieve queues and
- * shutting down copy engines if needed. Ensures opy engine interrupts
- * are disabled when it returns.  Prevents register access after it
- * returns.
- *
- * Return: 0 for success and non-zero for failure
- */
-static int hif_bus_suspend_link_down(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct pci_dev *pdev;
-	struct HIF_CE_state *hif_state;
-	int status = 0;
-
-	if (!scn)
-		return -EFAULT;
-
-	pdev = scn->aps_osdev.bdev;
-
-	hif_state = (struct HIF_CE_state *)scn->hif_hdl;
-	if (!hif_state) {
-		HIF_ERROR("%s: hif_state is null", __func__);
-		return -EFAULT;
-	}
-
-	disable_irq(pdev->irq);
-
-	status = hif_drain_tasklets(scn);
-	if (status != 0) {
-		enable_irq(pdev->irq);
-		return status;
-	}
-
-	/* Stop the HIF Sleep Timer */
-	hif_cancel_deferred_target_sleep(scn);
-
-	cdf_atomic_set(&scn->link_suspended, 1);
-
-	return 0;
-}
-
-/**
- * hif_bus_resume_link_down() - hif bus resume API
- *
- * This function resumes the bus reenabling interupts.
- *
- * Return: 0 for success and non-zero for failure
- */
-static int hif_bus_resume_link_down(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct pci_dev *pdev;
-
-	if (!scn)
-		return -EFAULT;
-
-	pdev = scn->aps_osdev.bdev;
-	if (!pdev) {
-		HIF_ERROR("%s: pci_dev is null", __func__);
-		return -EFAULT;
-	}
-
-	cdf_atomic_set(&scn->link_suspended, 0);
-
-	enable_irq(pdev->irq);
-
-	return 0;
-}
-
-/**
- * hif_bus_suspend(): prepare hif for suspend
- *
- * chose suspend type based on link suspend voting.
- *
- * Return: 0 for success and non-zero error code for failure
- */
-int hif_bus_suspend(void)
-{
-	if (hif_can_suspend_link())
-		return hif_bus_suspend_link_down();
-	else
-		return hif_bus_suspend_link_up();
-}
-
-/**
- * hif_bus_resume(): prepare hif for resume
- *
- * chose suspend type based on link suspend voting.
- *
- * Return: 0 for success and non-zero error code for failure
- */
-int hif_bus_resume(void)
-{
-	if (hif_can_suspend_link())
-		return hif_bus_resume_link_down();
-	else
-		return hif_bus_resume_link_up();
-}
-
-#ifdef FEATURE_RUNTIME_PM
-/**
- * __hif_runtime_pm_set_state(): utility function
- * @state: state to set
- *
- * indexes into the runtime pm state and sets it.
- */
-static void __hif_runtime_pm_set_state(enum hif_pm_runtime_state state)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct hif_pci_softc *sc;
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: HIF_CTX not initialized",
-		       __func__);
-		return;
-	}
-
-	sc = scn->hif_sc;
-	cdf_atomic_set(&sc->pm_state, state);
-
-}
-#endif
-
-#ifdef FEATURE_RUNTIME_PM
-/**
- * hif_runtime_pm_set_state_inprogress(): adjust runtime pm state
- *
- * Notify hif that a runtime pm opperation has started
- */
-static void hif_runtime_pm_set_state_inprogress(void)
-{
-	__hif_runtime_pm_set_state(HIF_PM_RUNTIME_STATE_INPROGRESS);
-}
-
-/**
- * hif_runtime_pm_set_state_on():  adjust runtime pm state
- *
- * Notify hif that a the runtime pm state should be on
- */
-static void hif_runtime_pm_set_state_on(void)
-{
-	__hif_runtime_pm_set_state(HIF_PM_RUNTIME_STATE_ON);
-}
-
-/**
- * hif_runtime_pm_set_state_suspended():  adjust runtime pm state
- *
- * Notify hif that a runtime suspend attempt has been completed successfully
- */
-static void hif_runtime_pm_set_state_suspended(void)
-{
-	__hif_runtime_pm_set_state(HIF_PM_RUNTIME_STATE_SUSPENDED);
-}
-
-static inline struct hif_pci_softc *get_sc(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: Could not disable ASPM scn is null",
-		       __func__);
-		return NULL;
-	}
-
-	return scn->hif_sc;
-}
-
-/**
- * hif_log_runtime_suspend_success() - log a successful runtime suspend
- */
-static void hif_log_runtime_suspend_success(void)
-{
-	struct hif_pci_softc *sc = get_sc();
-	if (sc == NULL)
-		return;
-
-	sc->pm_stats.suspended++;
-	sc->pm_stats.suspend_jiffies = jiffies;
-}
-
-/**
- * hif_log_runtime_suspend_failure() - log a failed runtime suspend
- *
- * log a failed runtime suspend
- * mark last busy to prevent immediate runtime suspend
- */
-static void hif_log_runtime_suspend_failure(void)
-{
-	struct hif_pci_softc *sc = get_sc();
-	if (sc == NULL)
-		return;
-
-	sc->pm_stats.suspend_err++;
-}
-
-/**
- * hif_log_runtime_resume_success() - log a successful runtime resume
- *
- * log a successfull runtime resume
- * mark last busy to prevent immediate runtime suspend
- */
-static void hif_log_runtime_resume_success(void)
-{
-	struct hif_pci_softc *sc = get_sc();
-	if (sc == NULL)
-		return;
-
-	sc->pm_stats.resumed++;
-}
-
-/**
- * hif_process_runtime_suspend_failure() - bookkeeping of suspend failure
- *
- * Record the failure.
- * mark last busy to delay a retry.
- * adjust the runtime_pm state.
- */
-void hif_process_runtime_suspend_failure(void)
-{
-	struct hif_pci_softc *sc = get_sc();
-
-	hif_log_runtime_suspend_failure();
-	if (sc != NULL)
-		hif_pm_runtime_mark_last_busy(sc->dev);
-	hif_runtime_pm_set_state_on();
-}
-
-/**
- * hif_pre_runtime_suspend() - bookkeeping before beginning runtime suspend
- *
- * Makes sure that the pci link will be taken down by the suspend opperation.
- * If the hif layer is configured to leave the bus on, runtime suspend will
- * not save any power.
- *
- * Set the runtime suspend state to in progress.
- *
- * return -EINVAL if the bus won't go down.  otherwise return 0
- */
-int hif_pre_runtime_suspend(void)
-{
-	if (!hif_can_suspend_link()) {
-		HIF_ERROR("Runtime PM not supported for link up suspend");
-		return -EINVAL;
-	}
-
-	hif_runtime_pm_set_state_inprogress();
-	return 0;
-}
-
-/**
- * hif_process_runtime_suspend_success() - bookkeeping of suspend success
- *
- * Record the success.
- * adjust the runtime_pm state
- */
-void hif_process_runtime_suspend_success(void)
-{
-	hif_runtime_pm_set_state_suspended();
-	hif_log_runtime_suspend_success();
-}
-
-/**
- * hif_pre_runtime_resume() - bookkeeping before beginning runtime resume
- *
- * update the runtime pm state.
- */
-void hif_pre_runtime_resume(void)
-{
-	hif_runtime_pm_set_state_inprogress();
-}
-
-/**
- * hif_process_runtime_resume_success() - bookkeeping after a runtime resume
- *
- * record the success.
- * adjust the runtime_pm state
- */
-void hif_process_runtime_resume_success(void)
-{
-	struct hif_pci_softc *sc = get_sc();
-
-	hif_log_runtime_resume_success();
-	if (sc != NULL)
-		hif_pm_runtime_mark_last_busy(sc->dev);
-	hif_runtime_pm_set_state_on();
-}
-#endif
-
-/**
- * hif_runtime_suspend() - do the bus suspend part of a runtime suspend
- *
- * Return: 0 for success and non-zero error code for failure
- */
-int hif_runtime_suspend(void)
-{
-	return hif_bus_suspend();
-}
-
-#ifdef WLAN_FEATURE_FASTPATH
-/**
- * hif_fastpath_resume() - resume fastpath for runtimepm
- *
- * ensure that the fastpath write index register is up to date
- * since runtime pm may cause ce_send_fast to skip the register
- * write.
- */
-static void hif_fastpath_resume(void)
-{
-	struct ol_softc *scn =
-		(struct ol_softc *)cds_get_context(CDF_MODULE_ID_HIF);
-	struct CE_state *ce_state;
-
-	if (!scn)
-		return;
-
-	if (scn->fastpath_mode_on) {
-		if (Q_TARGET_ACCESS_BEGIN(scn)) {
-			ce_state = scn->ce_id_to_state[CE_HTT_H2T_MSG];
-			cdf_spin_lock_bh(&ce_state->ce_index_lock);
-
-			/*war_ce_src_ring_write_idx_set */
-			CE_SRC_RING_WRITE_IDX_SET(scn, ce_state->ctrl_addr,
-					ce_state->src_ring->write_index);
-			cdf_spin_unlock_bh(&ce_state->ce_index_lock);
-			Q_TARGET_ACCESS_END(scn);
-		}
-	}
-}
-#else
-static void hif_fastpath_resume(void) {}
-#endif
-
-
-/**
- * hif_runtime_resume() - do the bus resume part of a runtime resume
- *
- *  Return: 0 for success and non-zero error code for failure
- */
-int hif_runtime_resume(void)
-{
-	int status = hif_bus_resume();
-
-	hif_fastpath_resume();
-
-	return status;
-}
-
-void hif_disable_isr(void *ol_sc)
-{
-	struct ol_softc *scn = (struct ol_softc *)ol_sc;
-	struct hif_pci_softc *sc = scn->hif_sc;
-
-	hif_nointrs(ol_sc);
-#if CONFIG_PCIE_64BIT_MSI
-	OS_FREE_CONSISTENT(&scn->aps_osdev, 4,
-			   scn->msi_magic, scn->msi_magic_dma,
-			   OS_GET_DMA_MEM_CONTEXT(scn, MSI_dmacontext));
-	scn->msi_magic = NULL;
-	scn->msi_magic_dma = 0;
-#endif
-	/* Cancel the pending tasklet */
-	ce_tasklet_kill(scn->hif_hdl);
-	tasklet_kill(&sc->intr_tq);
-	cdf_atomic_set(&scn->active_tasklet_cnt, 0);
-}
-
-/* Function to reset SoC */
-void hif_reset_soc(void *ol_sc)
-{
-	struct ol_softc *scn = (struct ol_softc *)ol_sc;
-	struct hif_pci_softc *sc = scn->hif_sc;
-
-#if defined(CPU_WARM_RESET_WAR)
-	/* Currently CPU warm reset sequence is tested only for AR9888_REV2
-	 * Need to enable for AR9888_REV1 once CPU warm reset sequence is
-	 * verified for AR9888_REV1
-	 */
-	if (scn->target_version == AR9888_REV2_VERSION) {
-		hif_pci_device_warm_reset(sc);
-	} else {
-		hif_pci_device_reset(sc);
-	}
-#else
-	hif_pci_device_reset(sc);
-#endif
-}
-
-void hif_disable_aspm(void)
-{
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct hif_pci_softc *sc;
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: Could not disable ASPM scn is null",
-		       __func__);
-		return;
-	}
-
-	sc = scn->hif_sc;
-
-	/* Disable ASPM when pkt log is enabled */
-	pci_read_config_dword(sc->pdev, 0x80, &scn->lcr_val);
-	pci_write_config_dword(sc->pdev, 0x80, (scn->lcr_val & 0xffffff00));
-}
-
-/**
- * hif_enable_power_gating(): enable HW power gating
- *
- * This function enables HW gating
- *
- * Return: none
- */
-void hif_enable_power_gating(void *hif_ctx)
-{
-	struct ol_softc *scn = hif_ctx;
-	struct hif_pci_softc *sc;
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: Could not disable ASPM scn is null",
-		       __func__);
-		return;
-	}
-	sc = scn->hif_sc;
-
-	/* Re-enable ASPM after firmware/OTP download is complete */
-	pci_write_config_dword(sc->pdev, 0x80, scn->lcr_val);
-	if (scn->pkt_log_init == false) {
-		PKT_LOG_MOD_INIT(scn);
-		scn->pkt_log_init = true;
-	}
-}
-
-#ifdef CONFIG_PCI_MSM
-static inline void hif_msm_pcie_debug_info(struct hif_pci_softc *sc)
-{
-	msm_pcie_debug_info(sc->pdev, 13, 1, 0, 0, 0);
-	msm_pcie_debug_info(sc->pdev, 13, 2, 0, 0, 0);
-}
-#else
-static inline void hif_msm_pcie_debug_info(struct hif_pci_softc *sc) {};
-#endif
-
-/*
- * For now, we use simple on-demand sleep/wake.
- * Some possible improvements:
- *  -Use the Host-destined A_INUM_PCIE_AWAKE interrupt rather than spin/delay
- *   (or perhaps spin/delay for a short while, then convert to sleep/interrupt)
- *   Careful, though, these functions may be used by
- *  interrupt handlers ("atomic")
- *  -Don't use host_reg_table for this code; instead use values directly
- *  -Use a separate timer to track activity and allow Target to sleep only
- *   if it hasn't done anything for a while; may even want to delay some
- *   processing for a short while in order to "batch" (e.g.) transmit
- *   requests with completion processing into "windows of up time".  Costs
- *   some performance, but improves power utilization.
- *  -On some platforms, it might be possible to eliminate explicit
- *   sleep/wakeup. Instead, take a chance that each access works OK. If not,
- *   recover from the failure by forcing the Target awake.
- *  -Change keep_awake_count to an atomic_t in order to avoid spin lock
- *   overhead in some cases. Perhaps this makes more sense when
- *   CONFIG_ATH_PCIE_ACCESS_LIKELY is used and less sense when LIKELY is
- *   disabled.
- *  -It is possible to compile this code out and simply force the Target
- *   to remain awake.  That would yield optimal performance at the cost of
- *   increased power. See CONFIG_ATH_PCIE_MAX_PERF.
- *
- * Note: parameter wait_for_it has meaning only when waking (when sleep_ok==0).
- */
-/**
- * hif_target_sleep_state_adjust() - on-demand sleep/wake
- * @scn: ol_softc pointer.
- * @sleep_ok: bool
- * @wait_for_it: bool
- *
- * Output the pipe error counts of each pipe to log file
- *
- * Return: int
- */
-#if ((CONFIG_ATH_PCIE_MAX_PERF == 0) && CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD)
-int
-hif_target_sleep_state_adjust(struct ol_softc *scn,
-			      bool sleep_ok, bool wait_for_it)
-{
-	struct HIF_CE_state *hif_state = scn->hif_hdl;
-	A_target_id_t pci_addr = scn->mem;
-	static int max_delay;
-	struct hif_pci_softc *sc = scn->hif_sc;
-	static int debug;
-
-	if (scn->recovery)
-		return -EACCES;
-
-	if (cdf_atomic_read(&scn->link_suspended)) {
-		HIF_ERROR("%s:invalid access, PCIe link is down", __func__);
-		debug = true;
-		CDF_ASSERT(0);
-		return -EACCES;
-	}
-
-	if (debug) {
-		wait_for_it = true;
-		HIF_ERROR("%s: doing debug for invalid access, PCIe link is suspended",
-				__func__);
-		CDF_ASSERT(0);
-	}
-
-	if (sleep_ok) {
-		cdf_spin_lock_irqsave(&hif_state->keep_awake_lock);
-		hif_state->keep_awake_count--;
-		if (hif_state->keep_awake_count == 0) {
-			/* Allow sleep */
-			hif_state->verified_awake = false;
-			hif_state->sleep_ticks = cdf_system_ticks();
-		}
-		if (hif_state->fake_sleep == false) {
-			/* Set the Fake Sleep */
-			hif_state->fake_sleep = true;
-
-			/* Start the Sleep Timer */
-			cdf_softirq_timer_cancel(&hif_state->sleep_timer);
-			cdf_softirq_timer_start(&hif_state->sleep_timer,
-				HIF_SLEEP_INACTIVITY_TIMER_PERIOD_MS);
-		}
-		cdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock);
-	} else {
-		cdf_spin_lock_irqsave(&hif_state->keep_awake_lock);
-
-		if (hif_state->fake_sleep) {
-			hif_state->verified_awake = true;
-		} else {
-			if (hif_state->keep_awake_count == 0) {
-				/* Force AWAKE */
-				hif_write32_mb(pci_addr +
-					      PCIE_LOCAL_BASE_ADDRESS +
-					      PCIE_SOC_WAKE_ADDRESS,
-					      PCIE_SOC_WAKE_V_MASK);
-			}
-		}
-		hif_state->keep_awake_count++;
-		cdf_spin_unlock_irqrestore(&hif_state->keep_awake_lock);
-
-		if (wait_for_it && !hif_state->verified_awake) {
-#define PCIE_SLEEP_ADJUST_TIMEOUT 8000  /* 8Ms */
-			int tot_delay = 0;
-			int curr_delay = 5;
-
-			for (;; ) {
-				if (hif_targ_is_awake(scn, pci_addr)) {
-					hif_state->verified_awake = true;
-					break;
-				} else
-				if (!hif_pci_targ_is_present
-					    (scn, pci_addr)) {
-					break;
-				}
-				if (tot_delay > PCIE_SLEEP_ADJUST_TIMEOUT) {
-					uint16_t val;
-					uint32_t bar;
-
-					HIF_ERROR("%s: keep_awake_count = %d",
-					       __func__,
-					       hif_state->keep_awake_count);
-
-					pci_read_config_word(sc->pdev,
-							     PCI_VENDOR_ID,
-							     &val);
-					HIF_ERROR("%s: PCI Vendor ID = 0x%04x",
-					       __func__, val);
-
-					pci_read_config_word(sc->pdev,
-							     PCI_DEVICE_ID,
-							     &val);
-					HIF_ERROR("%s: PCI Device ID = 0x%04x",
-					       __func__, val);
-
-					pci_read_config_word(sc->pdev,
-							     PCI_COMMAND, &val);
-					HIF_ERROR("%s: PCI Command = 0x%04x",
-					       __func__, val);
-
-					pci_read_config_word(sc->pdev,
-							     PCI_STATUS, &val);
-					HIF_ERROR("%s: PCI Status = 0x%04x",
-					       __func__, val);
-
-					pci_read_config_dword(sc->pdev,
-						PCI_BASE_ADDRESS_0, &bar);
-					HIF_ERROR("%s: PCI BAR 0 = 0x%08x",
-					       __func__, bar);
-
-					HIF_ERROR("%s: SOC_WAKE_ADDR 0%08x",
-						__func__,
-						hif_read32_mb(pci_addr +
-						PCIE_LOCAL_BASE_ADDRESS
-						+ PCIE_SOC_WAKE_ADDRESS));
-					HIF_ERROR("%s: RTC_STATE_ADDR 0x%08x",
-						__func__,
-						hif_read32_mb(pci_addr +
-						PCIE_LOCAL_BASE_ADDRESS
-						+ RTC_STATE_ADDRESS));
-
-					HIF_ERROR("%s:error, wakeup target",
-						__func__);
-					hif_msm_pcie_debug_info(sc);
-					if (!sc->ol_sc->enable_self_recovery)
-						CDF_BUG(0);
-					scn->recovery = true;
-					cds_set_recovery_in_progress(true);
-					cnss_wlan_pci_link_down();
-					return -EACCES;
-				}
-
-				OS_DELAY(curr_delay);
-				tot_delay += curr_delay;
-
-				if (curr_delay < 50)
-					curr_delay += 5;
-			}
-
-			/*
-			 * NB: If Target has to come out of Deep Sleep,
-			 * this may take a few Msecs. Typically, though
-			 * this delay should be <30us.
-			 */
-			if (tot_delay > max_delay)
-				max_delay = tot_delay;
-		}
-	}
-
-	if (debug && hif_state->verified_awake) {
-		debug = 0;
-		HIF_ERROR("%s: INTR_ENABLE_REG = 0x%08x, INTR_CAUSE_REG = 0x%08x, CPU_INTR_REG = 0x%08x, INTR_CLR_REG = 0x%08x, CE_INTERRUPT_SUMMARY_REG = 0x%08x",
-			__func__,
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
-				PCIE_INTR_ENABLE_ADDRESS),
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
-				PCIE_INTR_CAUSE_ADDRESS),
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
-				CPU_INTR_ADDRESS),
-			hif_read32_mb(sc->mem + SOC_CORE_BASE_ADDRESS +
-				PCIE_INTR_CLR_ADDRESS),
-			hif_read32_mb(sc->mem + CE_WRAPPER_BASE_ADDRESS +
-				CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
-	}
-
-	return 0;
-}
-#else
-inline int
-hif_target_sleep_state_adjust(struct ol_softc *scn,
-			      bool sleep_ok, bool wait_for_it)
-{
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
-uint32_t hif_target_read_checked(struct ol_softc *scn, uint32_t offset)
-{
-	uint32_t value;
-	void *addr;
-
-	if (!A_TARGET_ACCESS_OK(scn))
-		hi_fdebug();
-
-	addr = scn->mem + offset;
-	value = A_PCI_READ32(addr);
-
-	{
-		unsigned long irq_flags;
-		int idx = pcie_access_log_seqnum % PCIE_ACCESS_LOG_NUM;
-
-		spin_lock_irqsave(&pcie_access_log_lock, irq_flags);
-		pcie_access_log[idx].seqnum = pcie_access_log_seqnum;
-		pcie_access_log[idx].is_write = false;
-		pcie_access_log[idx].addr = addr;
-		pcie_access_log[idx].value = value;
-		pcie_access_log_seqnum++;
-		spin_unlock_irqrestore(&pcie_access_log_lock, irq_flags);
-	}
-
-	return value;
-}
-
-void
-hif_target_write_checked(struct ol_softc *scn, uint32_t offset, uint32_t value)
-{
-	void *addr;
-
-	if (!A_TARGET_ACCESS_OK(scn))
-		hi_fdebug();
-
-	addr = scn->mem + (offset);
-	hif_write32_mb(addr, value);
-
-	{
-		unsigned long irq_flags;
-		int idx = pcie_access_log_seqnum % PCIE_ACCESS_LOG_NUM;
-
-		spin_lock_irqsave(&pcie_access_log_lock, irq_flags);
-		pcie_access_log[idx].seqnum = pcie_access_log_seqnum;
-		pcie_access_log[idx].is_write = true;
-		pcie_access_log[idx].addr = addr;
-		pcie_access_log[idx].value = value;
-		pcie_access_log_seqnum++;
-		spin_unlock_irqrestore(&pcie_access_log_lock, irq_flags);
-	}
-}
-
-/**
- * hi_fdebug() - not needed in PCI
- *
- *
- * Return: n/a
- */
-void hi_fdebug(void)
-{
-	/* BUG_ON(1); */
-}
-
-/**
- * hif_target_dump_access_log() - dump access log
- *
- * dump access log
- *
- * Return: n/a
- */
-void hif_target_dump_access_log(void)
-{
-	int idx, len, start_idx, cur_idx;
-	unsigned long irq_flags;
-
-	spin_lock_irqsave(&pcie_access_log_lock, irq_flags);
-	if (pcie_access_log_seqnum > PCIE_ACCESS_LOG_NUM) {
-		len = PCIE_ACCESS_LOG_NUM;
-		start_idx = pcie_access_log_seqnum % PCIE_ACCESS_LOG_NUM;
-	} else {
-		len = pcie_access_log_seqnum;
-		start_idx = 0;
-	}
-
-	for (idx = 0; idx < len; idx++) {
-		cur_idx = (start_idx + idx) % PCIE_ACCESS_LOG_NUM;
-		HIF_ERROR("%s: idx:%d sn:%u wr:%d addr:%p val:%u.",
-		       __func__, idx,
-		       pcie_access_log[cur_idx].seqnum,
-		       pcie_access_log[cur_idx].is_write,
-		       pcie_access_log[cur_idx].addr,
-		       pcie_access_log[cur_idx].value);
-	}
-
-	pcie_access_log_seqnum = 0;
-	spin_unlock_irqrestore(&pcie_access_log_lock, irq_flags);
-}
-#endif
-
-/**
- * war_pci_write32() - PCIe io32 write workaround
- * @addr: addr
- * @offset: offset
- * @value: value
- *
- * iowrite32
- *
- * Return: int
- */
-void war_pci_write32(char *addr, uint32_t offset, uint32_t value)
-{
-	if (hif_pci_war1) {
-		unsigned long irq_flags;
-
-		spin_lock_irqsave(&pciwar_lock, irq_flags);
-
-		(void)ioread32((void __iomem *)(addr + offset + 4));
-		(void)ioread32((void __iomem *)(addr + offset + 4));
-		(void)ioread32((void __iomem *)(addr + offset + 4));
-		iowrite32((uint32_t) (value), (void __iomem *)(addr + offset));
-
-		spin_unlock_irqrestore(&pciwar_lock, irq_flags);
-	} else {
-		iowrite32((uint32_t) (value), (void __iomem *)(addr + offset));
-	}
-}
-
-/**
- * hif_configure_irq(): configure interrupt
- *
- * This function configures interrupt(s)
- *
- * @sc: PCIe control struct
- * @hif_hdl: struct HIF_CE_state
- *
- * Return: 0 - for success
- */
-int hif_configure_irq(struct hif_pci_softc *sc)
-{
-	int ret = 0;
-	struct ol_softc *scn = sc->ol_sc;
-
-	HIF_TRACE("%s: E", __func__);
-
-	if (ENABLE_MSI) {
-		ret = hif_configure_msi(sc);
-		if (ret == 0)
-			goto end;
-	}
-	/* MSI failed. Try legacy irq */
-	ret = hif_pci_configure_legacy_irq(sc);
-	if (ret < 0) {
-		HIF_ERROR("%s: hif_pci_configure_legacy_irq error = %d",
-			__func__, ret);
-		return ret;
-	}
-end:
-	scn->request_irq_done = true;
-	return 0;
-}
-
-/**
- * hif_target_sync() : ensure the target is ready
- * @scn: hif controll structure
- *
- * Informs fw that we plan to use legacy interupts so that
- * it can begin booting. Ensures that the fw finishes booting
- * before continuing. Should be called before trying to write
- * to the targets other registers for the first time.
- *
- * Return: none
- */
-void hif_target_sync(struct ol_softc *scn)
-{
-	hif_write32_mb(scn->mem+(SOC_CORE_BASE_ADDRESS |
-				PCIE_INTR_ENABLE_ADDRESS),
-				PCIE_INTR_FIRMWARE_MASK);
-
-	hif_write32_mb(scn->mem + PCIE_LOCAL_BASE_ADDRESS +
-			PCIE_SOC_WAKE_ADDRESS,
-			PCIE_SOC_WAKE_V_MASK);
-	while (!hif_targ_is_awake(scn, scn->mem))
-		;
-
-	if (HAS_FW_INDICATOR) {
-		int wait_limit = 500;
-		int fw_ind = 0;
-		HIF_TRACE("%s: Loop checking FW signal", __func__);
-		while (1) {
-			fw_ind = hif_read32_mb(scn->hif_sc->mem +
-					FW_INDICATOR_ADDRESS);
-			if (fw_ind & FW_IND_INITIALIZED)
-				break;
-			if (wait_limit-- < 0)
-				break;
-			hif_write32_mb(scn->mem+(SOC_CORE_BASE_ADDRESS |
-				PCIE_INTR_ENABLE_ADDRESS),
-				PCIE_INTR_FIRMWARE_MASK);
-
-			cdf_mdelay(10);
-		}
-		if (wait_limit < 0)
-			HIF_TRACE("%s: FW signal timed out",
-					__func__);
-		else
-			HIF_TRACE("%s: Got FW signal, retries = %x",
-					__func__, 500-wait_limit);
-	}
-	hif_write32_mb(scn->mem + PCIE_LOCAL_BASE_ADDRESS +
-			PCIE_SOC_WAKE_ADDRESS, PCIE_SOC_WAKE_RESET);
-}
-
-/**
- * hif_enable_bus(): enable bus
- *
- * This function enables the bus
- *
- * @ol_sc: soft_sc struct
- * @dev: device pointer
- * @bdev: bus dev pointer
- * bid: bus id pointer
- * type: enum hif_enable_type such as HIF_ENABLE_TYPE_PROBE
- * Return: CDF_STATUS
- */
-CDF_STATUS hif_enable_bus(struct ol_softc *ol_sc,
-			  struct device *dev, void *bdev,
-			  const hif_bus_id *bid,
-			  enum hif_enable_type type)
-{
-	int ret = 0;
-	uint32_t hif_type, target_type;
-	struct hif_pci_softc *sc;
-	uint16_t revision_id;
-	uint32_t lcr_val;
-	int probe_again = 0;
-	struct pci_dev *pdev = bdev;
-	const struct pci_device_id *id = bid;
-
-	HIF_TRACE("%s: con_mode = 0x%x, device_id = 0x%x",
-		  __func__, cds_get_conparam(), id->device);
-
-	ol_sc = cds_get_context(CDF_MODULE_ID_HIF);
-	if (!ol_sc) {
-		HIF_ERROR("%s: hif_ctx is NULL", __func__);
-		return CDF_STATUS_E_NOMEM;
-	}
-	sc = ol_sc->hif_sc;
-	ol_sc->aps_osdev.bdev = pdev;
-
-	sc->pdev = pdev;
-	sc->dev = &pdev->dev;
-	ol_sc->aps_osdev.bdev = pdev;
-	ol_sc->aps_osdev.device = &pdev->dev;
-	ol_sc->aps_osdev.bc.bc_handle = (void *)ol_sc->mem;
-	ol_sc->aps_osdev.bc.bc_bustype = type;
-	sc->devid = id->device;
-	sc->cacheline_sz = dma_get_cache_alignment();
-again:
-	ret = hif_enable_pci(sc, pdev, id);
-	if (ret < 0) {
-		HIF_ERROR("%s: ERROR - hif_enable_pci error = %d",
-		       __func__, ret);
-		goto err_enable_pci;
-	}
-	HIF_TRACE("%s: hif_enable_pci done", __func__);
-
-	/* Temporary FIX: disable ASPM on peregrine.
-	 * Will be removed after the OTP is programmed
-	 */
-	pci_read_config_dword(pdev, 0x80, &lcr_val);
-	pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
-
-	device_disable_async_suspend(&pdev->dev);
-	pci_read_config_word(pdev, 0x08, &revision_id);
-
-	ret = hif_get_device_type(id->device, revision_id,
-						&hif_type, &target_type);
-	if (ret < 0) {
-		HIF_ERROR("%s: invalid device id/revision_id", __func__);
-		goto err_tgtstate;
-	}
-	HIF_TRACE("%s: hif_type = 0x%x, target_type = 0x%x",
-		  __func__, hif_type, target_type);
-
-	hif_register_tbl_attach(sc->ol_sc, hif_type);
-	target_register_tbl_attach(sc->ol_sc, target_type);
-
-	ret = hif_pci_probe_tgt_wakeup(sc);
-	if (ret < 0) {
-		HIF_ERROR("%s: ERROR - hif_pci_prob_wakeup error = %d",
-			   __func__, ret);
-		if (ret == -EAGAIN)
-			probe_again++;
-		goto err_tgtstate;
-	}
-	HIF_TRACE("%s: hif_pci_probe_tgt_wakeup done", __func__);
-
-	ol_sc->target_type = target_type;
-	sc->soc_pcie_bar0 = pci_resource_start(pdev, BAR_NUM);
-	if (!sc->soc_pcie_bar0) {
-		HIF_ERROR("%s: ERROR - cannot get CE BAR0", __func__);
-		ret = -EIO;
-		goto err_tgtstate;
-	}
-	ol_sc->mem_pa = sc->soc_pcie_bar0;
-
-	BUG_ON(pci_get_drvdata(sc->pdev) != NULL);
-	pci_set_drvdata(sc->pdev, sc);
-
-	ret = hif_init_cdf_ctx(ol_sc);
-	if (ret != 0) {
-		HIF_ERROR("%s: cannot init CDF", __func__);
-		goto err_tgtstate;
-	}
-
-	hif_target_sync(ol_sc);
-	return 0;
-
-err_tgtstate:
-	hif_deinit_cdf_ctx(ol_sc);
-	hif_disable_pci(sc);
-	sc->pci_enabled = false;
-	HIF_ERROR("%s: error, hif_disable_pci done", __func__);
-	return CDF_STATUS_E_ABORTED;
-
-err_enable_pci:
-	if (probe_again && (probe_again <= ATH_PCI_PROBE_RETRY_MAX)) {
-		int delay_time;
-
-		HIF_INFO("%s: pci reprobe", __func__);
-		/* 10, 40, 90, 100, 100, ... */
-		delay_time = max(100, 10 * (probe_again * probe_again));
-		cdf_mdelay(delay_time);
-		goto again;
-	}
-	return ret;
-}
-
-/**
- * hif_get_target_type(): Get the target type
- *
- * This function is used to query the target type.
- *
- * @ol_sc: ol_softc struct pointer
- * @dev: device pointer
- * @bdev: bus dev pointer
- * @bid: bus id pointer
- * @hif_type: HIF type such as HIF_TYPE_QCA6180
- * @target_type: target type such as TARGET_TYPE_QCA6180
- *
- * Return: 0 for success
- */
-int hif_get_target_type(struct ol_softc *ol_sc, struct device *dev,
-	void *bdev, const hif_bus_id *bid, uint32_t *hif_type,
-	uint32_t *target_type)
-{
-	uint16_t revision_id;
-	struct pci_dev *pdev = bdev;
-	const struct pci_device_id *id = bid;
-
-	pci_read_config_word(pdev, 0x08, &revision_id);
-	return hif_get_device_type(id->device, revision_id,
-			hif_type, target_type);
-}
-
-#ifdef FEATURE_RUNTIME_PM
-
-void hif_pm_runtime_get_noresume(void *hif_ctx)
-{
-	struct ol_softc *scn = hif_ctx;
-	struct hif_pci_softc *sc;
-
-	if (NULL == scn)
-		return;
-
-	sc = scn->hif_sc;
-	if (NULL == sc)
-		return;
-
-	sc->pm_stats.runtime_get++;
-	pm_runtime_get_noresume(sc->dev);
-}
-
-/**
- * hif_pm_runtime_get() - do a get opperation on the device
- *
- * A get opperation will prevent a runtime suspend untill a
- * corresponding put is done.  This api should be used when sending
- * data.
- *
- * CONTRARY TO THE REGULAR RUNTIME PM, WHEN THE BUS IS SUSPENDED,
- * THIS API WILL ONLY REQUEST THE RESUME AND NOT TO A GET!!!
- *
- * return: success if the bus is up and a get has been issued
- *   otherwise an error code.
- */
-int hif_pm_runtime_get(void *hif_ctx)
-{
-	struct ol_softc *scn = hif_ctx;
-	struct hif_pci_softc *sc;
-	int ret;
-	int pm_state;
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: Could not do runtime get, scn is null",
-				__func__);
-		return -EFAULT;
-	}
-	sc = scn->hif_sc;
-
-	pm_state = cdf_atomic_read(&sc->pm_state);
-
-	if (pm_state  == HIF_PM_RUNTIME_STATE_ON ||
-			pm_state == HIF_PM_RUNTIME_STATE_NONE) {
-		sc->pm_stats.runtime_get++;
-		ret = __hif_pm_runtime_get(sc->dev);
-
-		/* Get can return 1 if the device is already active, just return
-		 * success in that case
-		 */
-		if (ret > 0)
-			ret = 0;
-
-		if (ret)
-			hif_pm_runtime_put(hif_ctx);
-
-		if (ret && ret != -EINPROGRESS) {
-			sc->pm_stats.runtime_get_err++;
-			HIF_ERROR("%s: Runtime Get PM Error in pm_state:%d ret: %d",
-				__func__, cdf_atomic_read(&sc->pm_state), ret);
-		}
-
-		return ret;
-	}
-
-	sc->pm_stats.request_resume++;
-	sc->pm_stats.last_resume_caller = (void *)_RET_IP_;
-	ret = hif_pm_request_resume(sc->dev);
-
-	return -EAGAIN;
-}
-
-/**
- * hif_pm_runtime_put() - do a put opperation on the device
- *
- * A put opperation will allow a runtime suspend after a corresponding
- * get was done.  This api should be used when sending data.
- *
- * This api will return a failure if runtime pm is stopped
- * This api will return failure if it would decrement the usage count below 0.
- *
- * return: CDF_STATUS_SUCCESS if the put is performed
- */
-int hif_pm_runtime_put(void *hif_ctx)
-{
-	struct ol_softc *scn = (struct ol_softc *)hif_ctx;
-	struct hif_pci_softc *sc;
-	int pm_state, usage_count;
-	unsigned long flags;
-	char *error = NULL;
-
-	if (NULL == scn) {
-		HIF_ERROR("%s: Could not do runtime put, scn is null",
-				__func__);
-		return -EFAULT;
-	}
-	sc = scn->hif_sc;
-
-	usage_count = atomic_read(&sc->dev->power.usage_count);
-
-	if (usage_count == 1) {
-		pm_state = cdf_atomic_read(&sc->pm_state);
-
-		if (pm_state == HIF_PM_RUNTIME_STATE_NONE)
-			error = "Ignoring unexpected put when runtime pm is disabled";
-
-	} else if (usage_count == 0) {
-		error = "PUT Without a Get Operation";
-	}
-
-	if (error) {
-		spin_lock_irqsave(&sc->runtime_lock, flags);
-		hif_pci_runtime_pm_warn(sc, error);
-		spin_unlock_irqrestore(&sc->runtime_lock, flags);
-		return -EINVAL;
-	}
-
-	sc->pm_stats.runtime_put++;
-
-	hif_pm_runtime_mark_last_busy(sc->dev);
-	hif_pm_runtime_put_auto(sc->dev);
-
-	return 0;
-}
-
-
-/**
- * __hif_pm_runtime_prevent_suspend() - prevent runtime suspend for a protocol reason
- * @hif_sc: pci context
- * @lock: runtime_pm lock being acquired
- *
- * Return 0 if successful.
- */
-static int __hif_pm_runtime_prevent_suspend(struct hif_pci_softc
-		*hif_sc, struct hif_pm_runtime_lock *lock)
-{
-	int ret = 0;
-
-	/*
-	 * We shouldn't be setting context->timeout to zero here when
-	 * context is active as we will have a case where Timeout API's
-	 * for the same context called back to back.
-	 * eg: echo "1=T:10:T:20" > /d/cnss_runtime_pm
-	 * Set context->timeout to zero in hif_pm_runtime_prevent_suspend
-	 * API to ensure the timeout version is no more active and
-	 * list entry of this context will be deleted during allow suspend.
-	 */
-	if (lock->active)
-		return 0;
-
-	ret = __hif_pm_runtime_get(hif_sc->dev);
-
-	/**
-	 * The ret can be -EINPROGRESS, if Runtime status is RPM_RESUMING or
-	 * RPM_SUSPENDING. Any other negative value is an error.
-	 * We shouldn't be do runtime_put here as in later point allow
-	 * suspend gets called with the the context and there the usage count
-	 * is decremented, so suspend will be prevented.
-	 */
-
-	if (ret < 0 && ret != -EINPROGRESS) {
-		hif_sc->pm_stats.runtime_get_err++;
-		hif_pci_runtime_pm_warn(hif_sc,
-				"Prevent Suspend Runtime PM Error");
-	}
-
-	hif_sc->prevent_suspend_cnt++;
-
-	lock->active = true;
-
-	list_add_tail(&lock->list, &hif_sc->prevent_suspend_list);
-
-	hif_sc->pm_stats.prevent_suspend++;
-
-	HIF_ERROR("%s: in pm_state:%d ret: %d", __func__,
-			cdf_atomic_read(&hif_sc->pm_state), ret);
-
-	return ret;
-}
-
-static int __hif_pm_runtime_allow_suspend(struct hif_pci_softc *hif_sc,
-		struct hif_pm_runtime_lock *lock)
-{
-	int ret = 0;
-	int usage_count;
-
-	if (hif_sc->prevent_suspend_cnt == 0)
-		return ret;
-
-	if (!lock->active)
-		return ret;
-
-	usage_count = atomic_read(&hif_sc->dev->power.usage_count);
-
-	/*
-	 * During Driver unload, platform driver increments the usage
-	 * count to prevent any runtime suspend getting called.
-	 * So during driver load in HIF_PM_RUNTIME_STATE_NONE state the
-	 * usage_count should be one. Ideally this shouldn't happen as
-	 * context->active should be active for allow suspend to happen
-	 * Handling this case here to prevent any failures.
-	 */
-	if ((cdf_atomic_read(&hif_sc->pm_state) == HIF_PM_RUNTIME_STATE_NONE
-				&& usage_count == 1) || usage_count == 0) {
-		hif_pci_runtime_pm_warn(hif_sc,
-				"Allow without a prevent suspend");
-		return -EINVAL;
-	}
-
-	list_del(&lock->list);
-
-	hif_sc->prevent_suspend_cnt--;
-
-	lock->active = false;
-	lock->timeout = 0;
-
-	hif_pm_runtime_mark_last_busy(hif_sc->dev);
-	ret = hif_pm_runtime_put_auto(hif_sc->dev);
-
-	HIF_ERROR("%s: in pm_state:%d ret: %d", __func__,
-			cdf_atomic_read(&hif_sc->pm_state), ret);
-
-	hif_sc->pm_stats.allow_suspend++;
-	return ret;
-}
-
-/**
- * hif_pm_runtime_lock_timeout_fn() - callback the runtime lock timeout
- * @data: calback data that is the pci context
- *
- * if runtime locks are aquired with a timeout, this function releases
- * the locks when the last runtime lock expires.
- *
- * dummy implementation until lock acquisition is implemented.
- */
-static void hif_pm_runtime_lock_timeout_fn(unsigned long data)
-{
-	struct hif_pci_softc *hif_sc = (struct hif_pci_softc *)data;
-	unsigned long flags;
-	unsigned long timer_expires;
-	struct hif_pm_runtime_lock *context, *temp;
-
-	spin_lock_irqsave(&hif_sc->runtime_lock, flags);
-
-	timer_expires = hif_sc->runtime_timer_expires;
-
-	/* Make sure we are not called too early, this should take care of
-	 * following case
-	 *
-	 * CPU0                         CPU1 (timeout function)
-	 * ----                         ----------------------
-	 * spin_lock_irq
-	 *                              timeout function called
-	 *
-	 * mod_timer()
-	 *
-	 * spin_unlock_irq
-	 *                              spin_lock_irq
-	 */
-	if (timer_expires > 0 && !time_after(timer_expires, jiffies)) {
-		hif_sc->runtime_timer_expires = 0;
-		list_for_each_entry_safe(context, temp,
-				&hif_sc->prevent_suspend_list, list) {
-			if (context->timeout) {
-				__hif_pm_runtime_allow_suspend(hif_sc, context);
-				hif_sc->pm_stats.allow_suspend_timeout++;
-			}
-		}
-	}
-
-	spin_unlock_irqrestore(&hif_sc->runtime_lock, flags);
-}
-
-int hif_pm_runtime_prevent_suspend(void *ol_sc,
-		struct hif_pm_runtime_lock *data)
-{
-	struct ol_softc *sc = (struct ol_softc *)ol_sc;
-	struct hif_pci_softc *hif_sc = sc->hif_sc;
-	struct hif_pm_runtime_lock *context = data;
-	unsigned long flags;
-
-	if (!sc->enable_runtime_pm)
-		return 0;
-
-	if (!context)
-		return -EINVAL;
-
-	spin_lock_irqsave(&hif_sc->runtime_lock, flags);
-	context->timeout = 0;
-	__hif_pm_runtime_prevent_suspend(hif_sc, context);
-	spin_unlock_irqrestore(&hif_sc->runtime_lock, flags);
-
-	return 0;
-}
-
-int hif_pm_runtime_allow_suspend(void *ol_sc, struct hif_pm_runtime_lock *data)
-{
-	struct ol_softc *sc = (struct ol_softc *)ol_sc;
-	struct hif_pci_softc *hif_sc = sc->hif_sc;
-	struct hif_pm_runtime_lock *context = data;
-
-	unsigned long flags;
-
-	if (!sc->enable_runtime_pm)
-		return 0;
-
-	if (!context)
-		return -EINVAL;
-
-	spin_lock_irqsave(&hif_sc->runtime_lock, flags);
-
-	__hif_pm_runtime_allow_suspend(hif_sc, context);
-
-	/* The list can be empty as well in cases where
-	 * we have one context in the list and the allow
-	 * suspend came before the timer expires and we delete
-	 * context above from the list.
-	 * When list is empty prevent_suspend count will be zero.
-	 */
-	if (hif_sc->prevent_suspend_cnt == 0 &&
-			hif_sc->runtime_timer_expires > 0) {
-		del_timer(&hif_sc->runtime_timer);
-		hif_sc->runtime_timer_expires = 0;
-	}
-
-	spin_unlock_irqrestore(&hif_sc->runtime_lock, flags);
-
-	return 0;
-}
-
-/**
- * hif_pm_runtime_prevent_suspend_timeout() - Prevent runtime suspend timeout
- * @ol_sc: HIF context
- * @lock: which lock is being acquired
- * @delay: Timeout in milliseconds
- *
- * Prevent runtime suspend with a timeout after which runtime suspend would be
- * allowed. This API uses a single timer to allow the suspend and timer is
- * modified if the timeout is changed before timer fires.
- * If the timeout is less than autosuspend_delay then use mark_last_busy instead
- * of starting the timer.
- *
- * It is wise to try not to use this API and correct the design if possible.
- *
- * Return: 0 on success and negative error code on failure
- */
-int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc,
-		struct hif_pm_runtime_lock *lock, unsigned int delay)
-{
-	struct ol_softc *sc = (struct ol_softc *)ol_sc;
-	struct hif_pci_softc *hif_sc = sc->hif_sc;
-	int ret = 0;
-	unsigned long expires;
-	unsigned long flags;
-	struct hif_pm_runtime_lock *context = lock;
-
-	if (cds_is_load_unload_in_progress()) {
-		HIF_ERROR("%s: Load/unload in progress, ignore!",
-				__func__);
-		return -EINVAL;
-	}
-
-	if (cds_is_logp_in_progress()) {
-		HIF_ERROR("%s: LOGP in progress, ignore!", __func__);
-		return -EINVAL;
-	}
-
-	if (!sc->enable_runtime_pm)
-		return 0;
-
-	if (!context)
-		return -EINVAL;
-
-	/*
-	 * Don't use internal timer if the timeout is less than auto suspend
-	 * delay.
-	 */
-	if (delay <= hif_sc->dev->power.autosuspend_delay) {
-		hif_pm_request_resume(hif_sc->dev);
-		hif_pm_runtime_mark_last_busy(hif_sc->dev);
-		return ret;
-	}
-
-	expires = jiffies + msecs_to_jiffies(delay);
-	expires += !expires;
-
-	spin_lock_irqsave(&hif_sc->runtime_lock, flags);
-
-	context->timeout = delay;
-	ret = __hif_pm_runtime_prevent_suspend(hif_sc, context);
-	hif_sc->pm_stats.prevent_suspend_timeout++;
-
-	/* Modify the timer only if new timeout is after already configured
-	 * timeout
-	 */
-	if (time_after(expires, hif_sc->runtime_timer_expires)) {
-		mod_timer(&hif_sc->runtime_timer, expires);
-		hif_sc->runtime_timer_expires = expires;
-	}
-
-	spin_unlock_irqrestore(&hif_sc->runtime_lock, flags);
-
-	HIF_ERROR("%s: pm_state: %d delay: %dms ret: %d\n", __func__,
-			cdf_atomic_read(&hif_sc->pm_state), delay, ret);
-
-	return ret;
-}
-
-/**
- * hif_runtime_lock_init() - API to initialize Runtime PM context
- * @name: Context name
- *
- * This API initalizes the Runtime PM context of the caller and
- * return the pointer.
- *
- * Return: void *
- */
-struct hif_pm_runtime_lock *hif_runtime_lock_init(const char *name)
-{
-	struct hif_pm_runtime_lock *context;
-
-	context = cdf_mem_malloc(sizeof(*context));
-	if (!context) {
-		HIF_ERROR("%s: No memory for Runtime PM wakelock context\n",
-				__func__);
-		return NULL;
-	}
-
-	context->name = name ? name : "Default";
-	return context;
-}
-
-/**
- * hif_runtime_lock_deinit() - This API frees the runtime pm ctx
- * @data: Runtime PM context
- *
- * Return: void
- */
-void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *data)
-{
-	unsigned long flags;
-	struct hif_pm_runtime_lock *context = data;
-	struct ol_softc *scn = cds_get_context(CDF_MODULE_ID_HIF);
-	struct hif_pci_softc *sc;
-
-	if (!scn)
-		return;
-
-	sc = scn->hif_sc;
-
-	if (!sc)
-		return;
-
-	if (!context)
-		return;
-
-	/*
-	 * Ensure to delete the context list entry and reduce the usage count
-	 * before freeing the context if context is active.
-	 */
-	spin_lock_irqsave(&sc->runtime_lock, flags);
-	__hif_pm_runtime_allow_suspend(sc, context);
-	spin_unlock_irqrestore(&sc->runtime_lock, flags);
-
-	cdf_mem_free(context);
-}
-
-#endif /* FEATURE_RUNTIME_PM */

core/hif/src/pcie/if_pci.h

@@ -1,234 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __ATH_PCI_H__
-#define __ATH_PCI_H__
-
-#include <linux/version.h>
-#include <linux/semaphore.h>
-#include <linux/interrupt.h>
-
-#define ATH_DBG_DEFAULT   0
-#include <osdep.h>
-#include <ol_if_athvar.h>
-#include <athdefs.h>
-#include "osapi_linux.h"
-#include "hif.h"
-#include "cepci.h"
-
-struct CE_state;
-struct ol_softc;
-
-/* An address (e.g. of a buffer) in Copy Engine space. */
-
-#define HIF_MAX_TASKLET_NUM 11
-struct hif_tasklet_entry {
-	uint8_t id;        /* 0 - 9: maps to CE, 10: fw */
-	void *hif_handler; /* struct hif_pci_softc */
-};
-
-/**
- * enum hif_pm_runtime_state - Driver States for Runtime Power Management
- * HIF_PM_RUNTIME_STATE_NONE: runtime pm is off
- * HIF_PM_RUNTIME_STATE_ON: runtime pm is active and link is active
- * HIF_PM_RUNTIME_STATE_INPROGRESS: a runtime suspend or resume is in progress
- * HIF_PM_RUNTIME_STATE_SUSPENDED: the driver is runtime suspended
- */
-enum hif_pm_runtime_state {
-	HIF_PM_RUNTIME_STATE_NONE,
-	HIF_PM_RUNTIME_STATE_ON,
-	HIF_PM_RUNTIME_STATE_INPROGRESS,
-	HIF_PM_RUNTIME_STATE_SUSPENDED,
-};
-
-#ifdef FEATURE_RUNTIME_PM
-
-/**
- * struct hif_pm_runtime_lock - data structure for preventing runtime suspend
- * @list - global list of runtime locks
- * @active - true if this lock is preventing suspend
- * @name - character string for tracking this lock
- */
-struct hif_pm_runtime_lock {
-	struct list_head list;
-	bool active;
-	uint32_t timeout;
-	const char *name;
-};
-
-/* Debugging stats for Runtime PM */
-struct hif_pci_pm_stats {
-	u32 suspended;
-	u32 suspend_err;
-	u32 resumed;
-	u32 runtime_get;
-	u32 runtime_put;
-	u32 request_resume;
-	u32 allow_suspend;
-	u32 prevent_suspend;
-	u32 prevent_suspend_timeout;
-	u32 allow_suspend_timeout;
-	u32 runtime_get_err;
-	void *last_resume_caller;
-	unsigned long suspend_jiffies;
-};
-#endif
-
-struct hif_pci_softc {
-	void __iomem *mem;      /* PCI address. */
-	/* For efficiency, should be first in struct */
-
-	struct device *dev;
-	struct pci_dev *pdev;
-	struct ol_softc *ol_sc;
-	int num_msi_intrs;      /* number of MSI interrupts granted */
-	/* 0 --> using legacy PCI line interrupts */
-	struct tasklet_struct intr_tq;  /* tasklet */
-
-
-	int irq;
-	int irq_event;
-	int cacheline_sz;
-	u16 devid;
-	cdf_dma_addr_t soc_pcie_bar0;
-	struct hif_tasklet_entry tasklet_entries[HIF_MAX_TASKLET_NUM];
-	bool pci_enabled;
-#ifdef FEATURE_RUNTIME_PM
-	atomic_t pm_state;
-	uint32_t prevent_suspend_cnt;
-	struct hif_pci_pm_stats pm_stats;
-	struct work_struct pm_work;
-	spinlock_t runtime_lock;
-	struct timer_list runtime_timer;
-	struct list_head prevent_suspend_list;
-	unsigned long runtime_timer_expires;
-	struct hif_pm_runtime_lock *prevent_linkdown_lock;
-#ifdef WLAN_OPEN_SOURCE
-	struct dentry *pm_dentry;
-#endif
-#endif
-};
-
-bool hif_pci_targ_is_present(struct ol_softc *scn, void *__iomem *mem);
-void icnss_dispatch_ce_irq(struct ol_softc *scn);
-int hif_configure_irq(struct hif_pci_softc *sc);
-void hif_pci_cancel_deferred_target_sleep(struct ol_softc *scn);
-
-/*
- * A firmware interrupt to the Host is indicated by the
- * low bit of SCRATCH_3_ADDRESS being set.
- */
-#define FW_EVENT_PENDING_REG_ADDRESS SCRATCH_3_ADDRESS
-
-/*
- * Typically, MSI Interrupts are used with PCIe. To force use of legacy
- * "ABCD" PCI line interrupts rather than MSI, define
- * FORCE_LEGACY_PCI_INTERRUPTS.
- * Even when NOT forced, the driver may attempt to use legacy PCI interrupts
- * MSI allocation fails
- */
-#define LEGACY_INTERRUPTS(sc) ((sc)->num_msi_intrs == 0)
-
-/*
- * There may be some pending tx frames during platform suspend.
- * Suspend operation should be delayed until those tx frames are
- * transfered from the host to target. This macro specifies how
- * long suspend thread has to sleep before checking pending tx
- * frame count.
- */
-#define OL_ATH_TX_DRAIN_WAIT_DELAY     50       /* ms */
-
-#define HIF_CE_DRAIN_WAIT_DELAY        10       /* ms */
-/*
- * Wait time (in unit of OL_ATH_TX_DRAIN_WAIT_DELAY) for pending
- * tx frame completion before suspend. Refer: hif_pci_suspend()
- */
-#ifndef QCA_WIFI_3_0_EMU
-#define OL_ATH_TX_DRAIN_WAIT_CNT       10
-#else
-#define OL_ATH_TX_DRAIN_WAIT_CNT       60
-#endif
-
-#define HIF_CE_DRAIN_WAIT_CNT          20
-
-
-#ifdef FEATURE_RUNTIME_PM
-#include <linux/pm_runtime.h>
-
-#ifdef WLAN_OPEN_SOURCE
-static inline int hif_pm_request_resume(struct device *dev)
-{
-	return pm_request_resume(dev);
-}
-static inline int __hif_pm_runtime_get(struct device *dev)
-{
-	return pm_runtime_get(dev);
-}
-
-static inline int hif_pm_runtime_put_auto(struct device *dev)
-{
-	return pm_runtime_put_autosuspend(dev);
-}
-
-static inline void hif_pm_runtime_mark_last_busy(struct device *dev)
-{
-	pm_runtime_mark_last_busy(dev);
-}
-
-static inline int hif_pm_runtime_resume(struct device *dev)
-{
-	return pm_runtime_resume(dev);
-}
-#else
-static inline int hif_pm_request_resume(struct device *dev)
-{
-	return cnss_pm_runtime_request(dev, CNSS_PM_REQUEST_RESUME);
-}
-
-static inline int __hif_pm_runtime_get(struct device *dev)
-{
-	return cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_GET);
-}
-
-static inline int hif_pm_runtime_put_auto(struct device *dev)
-{
-	return cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_PUT_AUTO);
-}
-
-static inline void hif_pm_runtime_mark_last_busy(struct device *dev)
-{
-	cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_MARK_LAST_BUSY);
-}
-static inline int hif_pm_runtime_resume(struct device *dev)
-{
-	return cnss_pm_runtime_request(dev, CNSS_PM_RUNTIME_RESUME);
-}
-#endif /* WLAN_OPEN_SOURCE */
-#else
-static inline void hif_pm_runtime_mark_last_busy(struct device *dev) { }
-#endif /* FEATURE_RUNTIME_PM */
-#endif /* __ATH_PCI_H__ */

core/hif/src/pcie/if_pci_internal.h

@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef __IF_PCI_INTERNAL_H__
-#define __IF_PCI_INTERNAL_H__
-#ifdef CONFIG_CNSS
-#define HIF_REGISTER_DRIVER(wlan_drv_id) \
-	cnss_wlan_register_driver(wlan_drv_id)
-#define HIF_UNREGISTER_DRIVER(wlan_drv_id) \
-	cnss_wlan_unregister_driver(wlan_drv_id)
-#else
-#define HIF_REGISTER_DRIVER(wlan_drv_id) \
-	pci_register_driver(wlan_drv_id)
-#define HIF_UNREGISTER_DRIVER(wlan_drv_id) \
-	pci_unregister_driver(wlan_drv_id)
-#endif
-
-#ifdef DISABLE_L1SS_STATES
-#define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr) \
-{ \
-	uint32_t lcr_val; \
-	pci_read_config_dword(pdev, addr, &lcr_val); \
-	pci_write_config_dword(pdev, addr, (lcr_val & ~0x0000000f)); \
-}
-#else
-#define PCI_CFG_TO_DISABLE_L1SS_STATES(pdev, addr)
-#endif
-
-#if defined(CONFIG_CNSS) && !defined(QCA_WIFI_3_0)
-#define GET_VIRT_RAMDUMP_MEM(ol_sc) \
-{ \
-	ol_sc->ramdump_base = cnss_get_virt_ramdump_mem(&ol_sc->ramdump_size); \
-	if (ol_sc->ramdump_base == NULL || !ol_sc->ramdump_size) \
-		HIF_ERROR("%s: Failed to get RAM dump memory addr or size!", \
-			__func__); \
-}
-#else
-#define GET_VIRT_RAMDUMP_MEM(ol_sc)
-#endif
-
-#ifdef QCA_WIFI_3_0
-#define PCI_CLR_CAUSE0_REGISTER(sc) \
-{ \
-	uint32_t tmp_cause0; \
-	tmp_cause0 = hif_read32_mb(sc->mem + PCIE_INTR_CAUSE_ADDRESS); \
-	hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS, \
-		      PCIE_INTR_FIRMWARE_MASK | tmp_cause0); \
-	hif_read32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS); \
-	hif_write32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS, 0); \
-	hif_read32_mb(sc->mem + PCIE_INTR_CLR_ADDRESS); \
-}
-
-#define HIF_PCI_TARG_IS_AWAKE(scn, mem) \
-{ \
-	return 1; \
-}
-#else
-#define PCI_CLR_CAUSE0_REGISTER(sc)
-
-#define HIF_PCI_TARG_IS_AWAKE(scn, mem) \
-{ \
-	uint32_t val; \
-	if (scn->recovery) \
-		return false; \
-	val = hif_read32_mb(mem + PCIE_LOCAL_BASE_ADDRESS \
-		+ RTC_STATE_ADDRESS); \
-	return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; \
-}
-#endif
-
-#if !defined(REMOVE_PKT_LOG) && !defined(QVIT)
-#define PKT_LOG_MOD_INIT(ol_sc) \
-{ \
-	ol_txrx_pdev_handle pdev_txrx_handle; \
-	pdev_txrx_handle = cds_get_context(CDF_MODULE_ID_TXRX); \
-	if (cds_get_conparam() != CDF_GLOBAL_FTM_MODE && \
-	    !WLAN_IS_EPPING_ENABLED(cds_get_conparam())) { \
-		ol_pl_sethandle(&pdev_txrx_handle->pl_dev, ol_sc); \
-		if (pktlogmod_init(ol_sc)) \
-			HIF_ERROR("%s: pktlogmod_init failed", __func__); \
-	} \
-}
-#else
-#define PKT_LOG_MOD_INIT(ol_sc)
-#endif
-#endif /* __IF_PCI_INTERNAL_H__ */

core/hif/src/qca6180def.h

@@ -1,1008 +0,0 @@
-/*
- * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _QCA6180DEF_H_
-#define _QCA6180DEF_H_
-
-#define MISSING                                        0
-#define _PCIE_LOCAL_REG_BASE_ADDRESS                   0x1E8000
-#define _WIFI_RTC_REG_BASE_ADDRESS                     0x45000
-#define _RTC_SOC_REG_BASE_ADDRESS                      0x113000
-#define _GPIO_ATHR_WLAN_REG_BASE_ADDRESS               0x85000
-#define _SI_REG_BASE_ADDRESS                           0x84000
-#define _SOC_CORE_REG_BASE_ADDRESS                     0x113000
-#define _CE_REG_CSR_BASE_ADDRESS                       0x240000
-#define _CE0_CE_REG_CSR_BASE_ADDRESS                   0
-#define _CE_WRAPPER_REG_CSR_BASE_ADDRESS               0xC000
-#define _MAC_WIFICMN_REG_BASE_ADDRESS                  MISSING
-
-/* Base Addresses */
-#define QCA6180_RTC_SOC_BASE_ADDRESS                   0x00000000
-#define QCA6180_RTC_WMAC_BASE_ADDRESS                  0x00000000
-#define QCA6180_MAC_COEX_BASE_ADDRESS                  0x0000f000
-#define QCA6180_BT_COEX_BASE_ADDRESS                   0x00002000
-#define QCA6180_SOC_PCIE_BASE_ADDRESS                  0x00130000
-#define QCA6180_SOC_CORE_BASE_ADDRESS                  0x00000000
-#define QCA6180_WLAN_UART_BASE_ADDRESS                 0x00111000
-#define QCA6180_WLAN_SI_BASE_ADDRESS                   0x00010000
-#define QCA6180_WLAN_GPIO_BASE_ADDRESS                 0x00000000
-#define QCA6180_WLAN_ANALOG_INTF_BASE_ADDRESS          0x00000000
-#define QCA6180_WLAN_MAC_BASE_ADDRESS                  0x00000000
-#define QCA6180_EFUSE_BASE_ADDRESS                     0x00024000
-#define QCA6180_FPGA_REG_BASE_ADDRESS                  0x00039000
-#define QCA6180_WLAN_UART2_BASE_ADDRESS                0x00054c00
-#define QCA6180_CE_WRAPPER_BASE_ADDRESS                0x24C000
-#define QCA6180_CE0_BASE_ADDRESS                       0x240000
-#define QCA6180_CE1_BASE_ADDRESS                       0x241000
-#define QCA6180_CE2_BASE_ADDRESS                       0x242000
-#define QCA6180_CE3_BASE_ADDRESS                       0x243000
-#define QCA6180_CE4_BASE_ADDRESS                       0x244000
-#define QCA6180_CE5_BASE_ADDRESS                       0x245000
-#define QCA6180_CE6_BASE_ADDRESS                       0x246000
-#define QCA6180_CE7_BASE_ADDRESS                       0x247000
-#define QCA6180_CE8_BASE_ADDRESS                       0x248000
-#define QCA6180_CE9_BASE_ADDRESS                       0x249000
-#define QCA6180_CE10_BASE_ADDRESS                      0x24A000
-#define QCA6180_CE11_BASE_ADDRESS                      0x24B000
-#define QCA6180_A_SOC_PCIE_SOC_PCIE_REG                0x130000
-#define QCA6180_DBI_BASE_ADDRESS                       0x0003c000
-#define QCA6180_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS     0x00007800
-#define QCA6180_WIFICMN_BASE_ADDRESS                   0x00000000
-#define QCA6180_BOARD_DATA_SZ                          MISSING
-#define QCA6180_BOARD_EXT_DATA_SZ                      MISSING
-#define QCA6180_A_SOC_PCIE_PCIE_BAR0_START \
-	(0x030 + QCA6180_A_SOC_PCIE_SOC_PCIE_REG)
-#define QCA6180_A_SOC_CORE_SCRATCH_0_ADDRESS           0x00114000
-#define QCA6180_A_SOC_CORE_SCRATCH_1_ADDRESS           0x00114004
-#define QCA6180_A_SOC_CORE_SCRATCH_2_ADDRESS           0x00114008
-#define QCA6180_A_SOC_CORE_SCRATCH_3_ADDRESS           0x0011400c
-#define QCA6180_A_SOC_CORE_SCRATCH_4_ADDRESS           0x00114010
-#define QCA6180_A_SOC_CORE_SCRATCH_5_ADDRESS           0x00114014
-#define QCA6180_A_SOC_CORE_SCRATCH_6_ADDRESS           0x00114018
-#define QCA6180_A_SOC_CORE_SCRATCH_7_ADDRESS           0x0011401c
-#define QCA6180_A_SOC_CORE_SPARE_0_REGISTER            0x00113180
-#define QCA6180_PCIE_INTR_FIRMWARE_ROUTE_MASK          0xff
-#define QCA6180_SCRATCH_3_ADDRESS                      0x00113020
-#define QCA6180_TARG_DRAM_START                        0x00400000
-#define QCA6180_SOC_SYSTEM_SLEEP_OFFSET                0x000000c0
-#define QCA6180_SOC_RESET_CONTROL_OFFSET \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_SOC_CLOCK_CONTROL_OFFSET \
-	(0x00000028 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_SOC_CLOCK_CONTROL_SI0_CLK_MASK         0x00000001
-#define QCA6180_SOC_RESET_CONTROL_SI0_RST_MASK         0x00000001
-#define QCA6180_WLAN_GPIO_PIN0_ADDRESS \
-	(0x50 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN1_ADDRESS \
-	(0x54 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN0_CONFIG_MASK             0x00007800
-#define QCA6180_WLAN_GPIO_PIN1_CONFIG_MASK             0x00007800
-#define QCA6180_SOC_CPU_CLOCK_OFFSET                   0x00000020
-#define QCA6180_SOC_LPO_CAL_OFFSET \
-	(0xe0 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN10_ADDRESS \
-	(0x78 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN11_ADDRESS \
-	(0x7c + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN12_ADDRESS \
-	(0x80 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_GPIO_PIN13_ADDRESS \
-	(0x84 + _GPIO_ATHR_WLAN_REG_BASE_ADDRESS)
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_LSB             0
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_MASK            0x00000003
-#define QCA6180_SOC_LPO_CAL_ENABLE_LSB                 20
-#define QCA6180_SOC_LPO_CAL_ENABLE_MASK                0x00100000
-
-#define QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_LSB          0
-#define QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_MASK         0x00000001
-#define QCA6180_WLAN_RESET_CONTROL_COLD_RST_MASK       0x00000002
-#define QCA6180_WLAN_RESET_CONTROL_WARM_RST_MASK       0x00000001
-#define QCA6180_SI_CONFIG_BIDIR_OD_DATA_LSB            18
-#define QCA6180_SI_CONFIG_BIDIR_OD_DATA_MASK           0x00040000
-#define QCA6180_SI_CONFIG_I2C_LSB                      16
-#define QCA6180_SI_CONFIG_I2C_MASK                     0x00010000
-#define QCA6180_SI_CONFIG_POS_SAMPLE_LSB               7
-#define QCA6180_SI_CONFIG_POS_SAMPLE_MASK              0x00000080
-#define QCA6180_SI_CONFIG_INACTIVE_CLK_LSB             4
-#define QCA6180_SI_CONFIG_INACTIVE_CLK_MASK            0x00000010
-#define QCA6180_SI_CONFIG_INACTIVE_DATA_LSB            5
-#define QCA6180_SI_CONFIG_INACTIVE_DATA_MASK           0x00000020
-#define QCA6180_SI_CONFIG_DIVIDER_LSB                  0
-#define QCA6180_SI_CONFIG_DIVIDER_MASK                 0x0000000f
-#define QCA6180_SI_CONFIG_OFFSET    (0x00000000 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_TX_DATA0_OFFSET  (0x00000008 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_TX_DATA1_OFFSET  (0x0000000c + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_RX_DATA0_OFFSET  (0x00000010 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_RX_DATA1_OFFSET  (0x00000014 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_CS_OFFSET        (0x00000004 + _SI_REG_BASE_ADDRESS)
-#define QCA6180_SI_CS_DONE_ERR_MASK                    0x00000400
-#define QCA6180_SI_CS_DONE_INT_MASK                    0x00000200
-#define QCA6180_SI_CS_START_LSB                        8
-#define QCA6180_SI_CS_START_MASK                       0x00000100
-#define QCA6180_SI_CS_RX_CNT_LSB                       4
-#define QCA6180_SI_CS_RX_CNT_MASK                      0x000000f0
-#define QCA6180_SI_CS_TX_CNT_LSB                       0
-#define QCA6180_SI_CS_TX_CNT_MASK                      0x0000000f
-#define QCA6180_CE_COUNT                               8
-#define QCA6180_SR_WR_INDEX_ADDRESS   (0x003C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_DST_WATERMARK_ADDRESS (0x0050 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_RX_MSDU_END_4_FIRST_MSDU_LSB           14
-#define QCA6180_RX_MSDU_END_4_FIRST_MSDU_MASK          0x00004000
-#define QCA6180_RX_MPDU_START_0_SEQ_NUM_LSB            16
-#define QCA6180_RX_MPDU_START_0_SEQ_NUM_MASK           0x0fff0000
-#define QCA6180_RX_MPDU_START_2_PN_47_32_LSB           0
-#define QCA6180_RX_MPDU_START_2_PN_47_32_MASK          0x0000ffff
-#define QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB    16
-#define QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK   0xffff0000
-#define QCA6180_RX_MSDU_END_4_LAST_MSDU_LSB            15
-#define QCA6180_RX_MSDU_END_4_LAST_MSDU_MASK           0x00008000
-#define QCA6180_RX_ATTENTION_0_MCAST_BCAST_LSB         2
-#define QCA6180_RX_ATTENTION_0_MCAST_BCAST_MASK        0x00000004
-#define QCA6180_RX_ATTENTION_0_FRAGMENT_LSB            13
-#define QCA6180_RX_ATTENTION_0_FRAGMENT_MASK           0x00002000
-#define QCA6180_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK    0x08000000
-#define QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB    16
-#define QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK   0x00ff0000
-#define QCA6180_RX_MSDU_START_0_MSDU_LENGTH_LSB        0
-#define QCA6180_RX_MSDU_START_0_MSDU_LENGTH_MASK       0x00003fff
-
-#define QCA6180_RX_MSDU_START_2_DECAP_FORMAT_OFFSET    0x00000008
-#define QCA6180_RX_MSDU_START_2_DECAP_FORMAT_LSB       8
-#define QCA6180_RX_MSDU_START_2_DECAP_FORMAT_MASK      0x00000300
-#define QCA6180_RX_MPDU_START_0_ENCRYPTED_LSB          13
-#define QCA6180_RX_MPDU_START_0_ENCRYPTED_MASK         0x00002000
-#define QCA6180_RX_ATTENTION_0_MORE_DATA_MASK          0x00000400
-#define QCA6180_RX_ATTENTION_0_MSDU_DONE_MASK          0x80000000
-#define QCA6180_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK     0x00040000
-#define QCA6180_DST_WR_INDEX_ADDRESS  (0x0040 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SRC_WATERMARK_ADDRESS (0x004c + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SRC_WATERMARK_LOW_MASK                      0xffff0000
-#define QCA6180_SRC_WATERMARK_HIGH_MASK                     0x0000ffff
-#define QCA6180_DST_WATERMARK_LOW_MASK                      0xffff0000
-#define QCA6180_DST_WATERMARK_HIGH_MASK                     0x0000ffff
-#define QCA6180_CURRENT_SRRI_ADDRESS (0x0044 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CURRENT_DRRI_ADDRESS (0x0048 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK        0x00000002
-#define QCA6180_HOST_IS_SRC_RING_LOW_WATERMARK_MASK         0x00000004
-#define QCA6180_HOST_IS_DST_RING_HIGH_WATERMARK_MASK        0x00000008
-#define QCA6180_HOST_IS_DST_RING_LOW_WATERMARK_MASK         0x00000010
-#define QCA6180_HOST_IS_ADDRESS (0x0030 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_MISC_IS_ADDRESS (0x0038 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_HOST_IS_COPY_COMPLETE_MASK                  0x00000001
-#define QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS        0x0000
-#define QCA6180_CE_WRAPPER_INDEX_BASE_LOW                   0x0004
-#define QCA6180_CE_WRAPPER_INDEX_BASE_HIGH                  0x0008
-#define QCA6180_HOST_IE_ADDRESS (0x002C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_HOST_IE_COPY_COMPLETE_MASK                  0x00000001
-#define QCA6180_SR_BA_ADDRESS      (0x0000 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SR_BA_ADDRESS_HIGH (0x0004 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_SR_SIZE_ADDRESS    (0x0008 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_CTRL1_ADDRESS   (0x0018 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_CTRL1_DMAX_LENGTH_MASK                   0x0000ffff
-#define QCA6180_DR_BA_ADDRESS       (0x000C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_DR_BA_ADDRESS_HIGH  (0x000C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_DR_SIZE_ADDRESS     (0x0014 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_CMD_REGISTER     (0x0020 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_ADDRESS      (0x0058 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_ADDRESS_HIGH (0x005C + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_DATA         (0x0060 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_CE_MSI_ENABLE_BIT   16
-#define QCA6180_MISC_IE_ADDRESS     (0x0034 + _CE0_CE_REG_CSR_BASE_ADDRESS)
-#define QCA6180_MISC_IS_AXI_ERR_MASK                        0x00000100
-#define QCA6180_MISC_IS_DST_ADDR_ERR_MASK                   0x00000200
-#define QCA6180_MISC_IS_SRC_LEN_ERR_MASK                    0x00000100
-#define QCA6180_MISC_IS_DST_MAX_LEN_VIO_MASK                0x00000080
-#define QCA6180_MISC_IS_DST_RING_OVERFLOW_MASK              0x00000040
-#define QCA6180_MISC_IS_SRC_RING_OVERFLOW_MASK              0x00000020
-#define QCA6180_WRAPPER_INTERRUPT_SUMMARY_ADDR              0x0024D000
-#define QCA6180_SRC_WATERMARK_LOW_LSB                       16
-#define QCA6180_SRC_WATERMARK_HIGH_LSB                      0
-#define QCA6180_DST_WATERMARK_LOW_LSB                       16
-#define QCA6180_DST_WATERMARK_HIGH_LSB                      0
-#define QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK  0xfff000
-#define QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB   12
-#define QCA6180_CE_CTRL1_DMAX_LENGTH_LSB                    0
-#define QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK         0x00020000
-#define QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK         0x00040000
-#define QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB          17
-#define QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB          18
-#define QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK  0x0000004
-#define QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB   2
-#define QCA6180_SOC_GLOBAL_RESET_ADDRESS \
-	(0x0008 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_RTC_STATE_ADDRESS \
-	(0x0000 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_RTC_STATE_COLD_RESET_MASK                   0x400
-
-#define QCA6180_PCIE_SOC_WAKE_RESET                         0x00000000
-#define QCA6180_PCIE_SOC_WAKE_ADDRESS (0x0004 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_PCIE_SOC_WAKE_V_MASK                        0x00000001
-
-#define QCA6180_RTC_STATE_V_MASK                            0x00000007
-#define QCA6180_RTC_STATE_V_LSB                             0
-#define QCA6180_RTC_STATE_V_ON                              5
-#define QCA6180_PCIE_LOCAL_BASE_ADDRESS                     0x0
-#define QCA6180_FW_IND_EVENT_PENDING                        1
-#define QCA6180_FW_IND_INITIALIZED                          2
-#define QCA6180_FW_IND_HELPER                               4
-
-#define QCA6180_PCIE_INTR_ENABLE_ADDRESS (0x000c + _SOC_CORE_REG_BASE_ADDRESS)
-#define QCA6180_PCIE_INTR_CLR_ADDRESS    (0x001c + _SOC_CORE_REG_BASE_ADDRESS)
-#define QCA6180_PCIE_INTR_FIRMWARE_MASK                     0x00100000
-#define QCA6180_PCIE_INTR_CE0_MASK                          0x00000100
-#define QCA6180_PCIE_INTR_CE_MASK_ALL                       0x0000ff00
-#define QCA6180_PCIE_INTR_CAUSE_ADDRESS  (0x0014 + _SOC_CORE_REG_BASE_ADDRESS)
-
-#define QCA6180_CPU_INTR_ADDRESS                            0xffffffff
-#define QCA6180_SOC_LF_TIMER_CONTROL0_ADDRESS               0xffffffff
-#define QCA6180_SOC_LF_TIMER_CONTROL0_ENABLE_MASK           0xffffffff
-#define QCA6180_SOC_RESET_CONTROL_ADDRESS \
-	(0x00000000 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_SOC_RESET_CONTROL_CE_RST_MASK            0x0100
-#define QCA6180_SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
-#define QCA6180_CORE_CTRL_ADDRESS        (0x0000 + _SOC_CORE_REG_BASE_ADDRESS)
-#define QCA6180_CORE_CTRL_CPU_INTR_MASK                  0x00002000
-#define QCA6180_LOCAL_SCRATCH_OFFSET                     0x00000018
-#define QCA6180_CLOCK_GPIO_OFFSET                        0xffffffff
-#define QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_LSB             0
-#define QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_MASK            0
-#define QCA6180_SOC_CHIP_ID_ADDRESS                      0x000000f0
-#define QCA6180_SOC_CHIP_ID_VERSION_MASK                 0xfffc0000
-#define QCA6180_SOC_CHIP_ID_VERSION_LSB                  18
-#define QCA6180_SOC_CHIP_ID_REVISION_MASK                0x00000f00
-#define QCA6180_SOC_CHIP_ID_REVISION_LSB                 8
-#define QCA6180_SOC_POWER_REG_OFFSET                     0x0000010c
-
-/* Copy Engine Debug */
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
-#define QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
-#define QCA6180_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
-#define QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
-#define QCA6180_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
-#define QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
-#define QCA6180_WLAN_DEBUG_OUT_OFFSET                    0x00000110
-#define QCA6180_WLAN_DEBUG_OUT_DATA_MSB                  19
-#define QCA6180_WLAN_DEBUG_OUT_DATA_LSB                  0
-#define QCA6180_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
-#define QCA6180_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
-#define QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
-#define QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
-#define QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
-#define QCA6180_AMBA_DEBUG_BUS_SEL_MSB                   4
-#define QCA6180_AMBA_DEBUG_BUS_SEL_LSB                   0
-#define QCA6180_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
-#define QCA6180_CE_WRAPPER_DEBUG_OFFSET                  0x0008
-#define QCA6180_CE_WRAPPER_DEBUG_SEL_MSB                 4
-#define QCA6180_CE_WRAPPER_DEBUG_SEL_LSB                 0
-#define QCA6180_CE_WRAPPER_DEBUG_SEL_MASK                0x0000001f
-#define QCA6180_CE_DEBUG_OFFSET                          0x0054
-#define QCA6180_CE_DEBUG_SEL_MSB                         5
-#define QCA6180_CE_DEBUG_SEL_LSB                         0
-#define QCA6180_CE_DEBUG_SEL_MASK                        0x0000003f
-/* End */
-
-/* PLL start */
-#define QCA6180_EFUSE_OFFSET                             0x0000032c
-#define QCA6180_EFUSE_XTAL_SEL_MSB                       10
-#define QCA6180_EFUSE_XTAL_SEL_LSB                       8
-#define QCA6180_EFUSE_XTAL_SEL_MASK                      0x00000700
-#define QCA6180_BB_PLL_CONFIG_OFFSET                     0x000002f4
-#define QCA6180_BB_PLL_CONFIG_OUTDIV_MSB                 20
-#define QCA6180_BB_PLL_CONFIG_OUTDIV_LSB                 18
-#define QCA6180_BB_PLL_CONFIG_OUTDIV_MASK                0x001c0000
-#define QCA6180_BB_PLL_CONFIG_FRAC_MSB                   17
-#define QCA6180_BB_PLL_CONFIG_FRAC_LSB                   0
-#define QCA6180_BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
-#define QCA6180_WLAN_PLL_SETTLE_TIME_MSB                 10
-#define QCA6180_WLAN_PLL_SETTLE_TIME_LSB                 0
-#define QCA6180_WLAN_PLL_SETTLE_TIME_MASK                0x000007ff
-#define QCA6180_WLAN_PLL_SETTLE_OFFSET                   0x0018
-#define QCA6180_WLAN_PLL_SETTLE_SW_MASK                  0x000007ff
-#define QCA6180_WLAN_PLL_SETTLE_RSTMASK                  0xffffffff
-#define QCA6180_WLAN_PLL_SETTLE_RESET                    0x00000400
-#define QCA6180_WLAN_PLL_CONTROL_NOPWD_MSB               18
-#define QCA6180_WLAN_PLL_CONTROL_NOPWD_LSB               18
-#define QCA6180_WLAN_PLL_CONTROL_NOPWD_MASK              0x00040000
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_MSB              16
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_LSB              16
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_MASK             0x00010000
-#define QCA6180_WLAN_PLL_CONTROL_BYPASS_RESET            0x1
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MSB             15
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_LSB             14
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MASK            0x0000c000
-#define QCA6180_WLAN_PLL_CONTROL_CLK_SEL_RESET           0x0
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_MSB              13
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_LSB              10
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_MASK             0x00003c00
-#define QCA6180_WLAN_PLL_CONTROL_REFDIV_RESET            0x0
-#define QCA6180_WLAN_PLL_CONTROL_DIV_MSB                 9
-#define QCA6180_WLAN_PLL_CONTROL_DIV_LSB                 0
-#define QCA6180_WLAN_PLL_CONTROL_DIV_MASK                0x000003ff
-#define QCA6180_WLAN_PLL_CONTROL_DIV_RESET               0x11
-#define QCA6180_WLAN_PLL_CONTROL_OFFSET                  0x0014
-#define QCA6180_WLAN_PLL_CONTROL_SW_MASK                 0x001fffff
-#define QCA6180_WLAN_PLL_CONTROL_RSTMASK                 0xffffffff
-#define QCA6180_WLAN_PLL_CONTROL_RESET                   0x00010011
-#define QCA6180_SOC_CORE_CLK_CTRL_OFFSET                 0x00000114
-#define QCA6180_SOC_CORE_CLK_CTRL_DIV_MSB                2
-#define QCA6180_SOC_CORE_CLK_CTRL_DIV_LSB                0
-#define QCA6180_SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MSB         5
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_LSB         5
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MASK        0x00000020
-#define QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_RESET       0x0
-#define QCA6180_RTC_SYNC_STATUS_OFFSET                   0x0244
-#define QCA6180_SOC_CPU_CLOCK_OFFSET                     0x00000020
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_MSB               1
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_LSB               0
-#define QCA6180_SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
-/* PLL end */
-
-#define QCA6180_PCIE_INTR_CE_MASK(n)  (QCA6180_PCIE_INTR_CE0_MASK << (n))
-#define QCA6180_DRAM_BASE_ADDRESS     QCA6180_TARG_DRAM_START
-#define QCA6180_FW_INDICATOR_ADDRESS \
-	(QCA6180_WIFICMN_BASE_ADDRESS + QCA6180_SCRATCH_3_ADDRESS)
-#define QCA6180_SYSTEM_SLEEP_OFFSET       QCA6180_SOC_SYSTEM_SLEEP_OFFSET
-#define QCA6180_WLAN_SYSTEM_SLEEP_OFFSET  (0x002c + _WIFI_RTC_REG_BASE_ADDRESS)
-#define QCA6180_WLAN_RESET_CONTROL_OFFSET (0x0000 + _WIFI_RTC_REG_BASE_ADDRESS)
-#define QCA6180_CLOCK_CONTROL_OFFSET      QCA6180_SOC_CLOCK_CONTROL_OFFSET
-#define QCA6180_CLOCK_CONTROL_SI0_CLK_MASK \
-	QCA6180_SOC_CLOCK_CONTROL_SI0_CLK_MASK
-#define QCA6180_RESET_CONTROL_MBOX_RST_MASK 0x00000004
-#define QCA6180_RESET_CONTROL_SI0_RST_MASK \
-	QCA6180_SOC_RESET_CONTROL_SI0_RST_MASK
-#define QCA6180_GPIO_BASE_ADDRESS         QCA6180_WLAN_GPIO_BASE_ADDRESS
-#define QCA6180_GPIO_PIN0_OFFSET          QCA6180_WLAN_GPIO_PIN0_ADDRESS
-#define QCA6180_GPIO_PIN1_OFFSET          QCA6180_WLAN_GPIO_PIN1_ADDRESS
-#define QCA6180_GPIO_PIN0_CONFIG_MASK     QCA6180_WLAN_GPIO_PIN0_CONFIG_MASK
-#define QCA6180_GPIO_PIN1_CONFIG_MASK     QCA6180_WLAN_GPIO_PIN1_CONFIG_MASK
-#define QCA6180_SI_BASE_ADDRESS           0x00000000
-#define QCA6180_CPU_CLOCK_OFFSET          (0x20 + _RTC_SOC_REG_BASE_ADDRESS)
-#define QCA6180_LPO_CAL_OFFSET            QCA6180_SOC_LPO_CAL_OFFSET
-#define QCA6180_GPIO_PIN10_OFFSET         QCA6180_WLAN_GPIO_PIN10_ADDRESS
-#define QCA6180_GPIO_PIN11_OFFSET         QCA6180_WLAN_GPIO_PIN11_ADDRESS
-#define QCA6180_GPIO_PIN12_OFFSET         QCA6180_WLAN_GPIO_PIN12_ADDRESS
-#define QCA6180_GPIO_PIN13_OFFSET         QCA6180_WLAN_GPIO_PIN13_ADDRESS
-#define QCA6180_CPU_CLOCK_STANDARD_LSB    0
-#define QCA6180_CPU_CLOCK_STANDARD_MASK   0x1
-#define QCA6180_LPO_CAL_ENABLE_LSB        QCA6180_SOC_LPO_CAL_ENABLE_LSB
-#define QCA6180_LPO_CAL_ENABLE_MASK       QCA6180_SOC_LPO_CAL_ENABLE_MASK
-#define QCA6180_ANALOG_INTF_BASE_ADDRESS  QCA6180_WLAN_ANALOG_INTF_BASE_ADDRESS
-#define QCA6180_MBOX_BASE_ADDRESS         0x00008000
-#define QCA6180_INT_STATUS_ENABLE_ERROR_LSB             MISSING
-#define QCA6180_INT_STATUS_ENABLE_ERROR_MASK            MISSING
-#define QCA6180_INT_STATUS_ENABLE_CPU_LSB               MISSING
-#define QCA6180_INT_STATUS_ENABLE_CPU_MASK              MISSING
-#define QCA6180_INT_STATUS_ENABLE_COUNTER_LSB           MISSING
-#define QCA6180_INT_STATUS_ENABLE_COUNTER_MASK          MISSING
-#define QCA6180_INT_STATUS_ENABLE_MBOX_DATA_LSB         MISSING
-#define QCA6180_INT_STATUS_ENABLE_MBOX_DATA_MASK        MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB    MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK   MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB     MISSING
-#define QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK    MISSING
-#define QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_LSB       MISSING
-#define QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_MASK      MISSING
-#define QCA6180_INT_STATUS_ENABLE_ADDRESS               MISSING
-#define QCA6180_CPU_INT_STATUS_ENABLE_BIT_LSB           MISSING
-#define QCA6180_CPU_INT_STATUS_ENABLE_BIT_MASK          MISSING
-#define QCA6180_HOST_INT_STATUS_ADDRESS                 MISSING
-#define QCA6180_CPU_INT_STATUS_ADDRESS                  MISSING
-#define QCA6180_ERROR_INT_STATUS_ADDRESS                MISSING
-#define QCA6180_ERROR_INT_STATUS_WAKEUP_MASK            MISSING
-#define QCA6180_ERROR_INT_STATUS_WAKEUP_LSB             MISSING
-#define QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_MASK      MISSING
-#define QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_LSB       MISSING
-#define QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_MASK       MISSING
-#define QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_LSB        MISSING
-#define QCA6180_COUNT_DEC_ADDRESS                       MISSING
-#define QCA6180_HOST_INT_STATUS_CPU_MASK                MISSING
-#define QCA6180_HOST_INT_STATUS_CPU_LSB                 MISSING
-#define QCA6180_HOST_INT_STATUS_ERROR_MASK              MISSING
-#define QCA6180_HOST_INT_STATUS_ERROR_LSB               MISSING
-#define QCA6180_HOST_INT_STATUS_COUNTER_MASK            MISSING
-#define QCA6180_HOST_INT_STATUS_COUNTER_LSB             MISSING
-#define QCA6180_RX_LOOKAHEAD_VALID_ADDRESS              MISSING
-#define QCA6180_WINDOW_DATA_ADDRESS                     MISSING
-#define QCA6180_WINDOW_READ_ADDR_ADDRESS                MISSING
-#define QCA6180_WINDOW_WRITE_ADDR_ADDRESS               MISSING
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_0 \
-	(0x0024 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_1 \
-	(0x0028 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_2 \
-	(0x002C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_3 \
-	(0x0030 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_4 \
-	(0x0034 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_5 \
-	(0x0038 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_6 \
-	(0x003C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_7 \
-	(0x0040 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_8 \
-	(0x0044 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_9 \
-	(0x0048 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_10 \
-	(0x004C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_11 \
-	(0x0050 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_12 \
-	(0x0054 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_13 \
-	(0x0058 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_14 \
-	(0x005C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_15 \
-	(0x0060 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_16 \
-	(0x0064 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_17 \
-	(0x0068 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_18 \
-	(0x006C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_19 \
-	(0x0070 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_20 \
-	(0x0074 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_21 \
-	(0x0078 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_22 \
-	(0x007C + _PCIE_LOCAL_REG_BASE_ADDRESS)
-#define QCA6180_A_LOCAL_SHADOW_REG_VALUE_23 \
-	(0x0080 + _PCIE_LOCAL_REG_BASE_ADDRESS)
-
-
-/* Q6 iHelium emulation registers */
-#define QCA6180_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1	0x00113018
-#define QCA6180_A_SOC_CORE_SPARE_1_REGISTER	0x00113184
-#define QCA6180_A_SOC_CORE_PCIE_INTR_CLR_GRP1	0x00113020
-#define QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1	0x00113010
-#define QCA6180_A_SOC_PCIE_PCIE_SCRATCH_0	0x00130040
-#define QCA6180_A_SOC_PCIE_PCIE_SCRATCH_1	0x00130044
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE0_TARGET_IE	0x00240024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE0_TARGET_IS	0x00240028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE1_TARGET_IE	0x00241024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE1_TARGET_IS	0x00241028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE2_TARGET_IE	0x00242024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE2_TARGET_IS	0x00242028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE3_TARGET_IE	0x00243024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE3_TARGET_IS	0x00243028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE4_TARGET_IE	0x00244024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE4_TARGET_IS	0x00244028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE5_TARGET_IE	0x00245024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE5_TARGET_IS	0x00245028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE6_TARGET_IE	0x00246024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE6_TARGET_IS	0x00246028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE7_TARGET_IE	0x00247024
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE7_TARGET_IS	0x00247028
-#define QCA6180_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA	0x08
-#define QCA6180_A_SOC_PCIE_PCIE_SCRATCH_2	0x0013005C
-#define QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK        0x0
-/* end: Q6 iHelium emulation registers */
-
-struct targetdef_s qca6180_targetdef = {
-	.d_RTC_SOC_BASE_ADDRESS = QCA6180_RTC_SOC_BASE_ADDRESS,
-	.d_RTC_WMAC_BASE_ADDRESS = QCA6180_RTC_WMAC_BASE_ADDRESS,
-	.d_SYSTEM_SLEEP_OFFSET = QCA6180_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_OFFSET = QCA6180_WLAN_SYSTEM_SLEEP_OFFSET,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =
-	QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_LSB,
-	.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =
-	QCA6180_WLAN_SYSTEM_SLEEP_DISABLE_MASK,
-	.d_CLOCK_CONTROL_OFFSET = QCA6180_CLOCK_CONTROL_OFFSET,
-	.d_CLOCK_CONTROL_SI0_CLK_MASK = QCA6180_CLOCK_CONTROL_SI0_CLK_MASK,
-	.d_RESET_CONTROL_OFFSET = QCA6180_SOC_RESET_CONTROL_OFFSET,
-	.d_RESET_CONTROL_MBOX_RST_MASK = QCA6180_RESET_CONTROL_MBOX_RST_MASK,
-	.d_RESET_CONTROL_SI0_RST_MASK = QCA6180_RESET_CONTROL_SI0_RST_MASK,
-	.d_WLAN_RESET_CONTROL_OFFSET = QCA6180_WLAN_RESET_CONTROL_OFFSET,
-	.d_WLAN_RESET_CONTROL_COLD_RST_MASK =
-	QCA6180_WLAN_RESET_CONTROL_COLD_RST_MASK,
-	.d_WLAN_RESET_CONTROL_WARM_RST_MASK =
-	QCA6180_WLAN_RESET_CONTROL_WARM_RST_MASK,
-	.d_GPIO_BASE_ADDRESS = QCA6180_GPIO_BASE_ADDRESS,
-	.d_GPIO_PIN0_OFFSET = QCA6180_GPIO_PIN0_OFFSET,
-	.d_GPIO_PIN1_OFFSET = QCA6180_GPIO_PIN1_OFFSET,
-	.d_GPIO_PIN0_CONFIG_MASK = QCA6180_GPIO_PIN0_CONFIG_MASK,
-	.d_GPIO_PIN1_CONFIG_MASK = QCA6180_GPIO_PIN1_CONFIG_MASK,
-	.d_SI_CONFIG_BIDIR_OD_DATA_LSB = QCA6180_SI_CONFIG_BIDIR_OD_DATA_LSB,
-	.d_SI_CONFIG_BIDIR_OD_DATA_MASK = QCA6180_SI_CONFIG_BIDIR_OD_DATA_MASK,
-	.d_SI_CONFIG_I2C_LSB = QCA6180_SI_CONFIG_I2C_LSB,
-	.d_SI_CONFIG_I2C_MASK = QCA6180_SI_CONFIG_I2C_MASK,
-	.d_SI_CONFIG_POS_SAMPLE_LSB = QCA6180_SI_CONFIG_POS_SAMPLE_LSB,
-	.d_SI_CONFIG_POS_SAMPLE_MASK = QCA6180_SI_CONFIG_POS_SAMPLE_MASK,
-	.d_SI_CONFIG_INACTIVE_CLK_LSB = QCA6180_SI_CONFIG_INACTIVE_CLK_LSB,
-	.d_SI_CONFIG_INACTIVE_CLK_MASK = QCA6180_SI_CONFIG_INACTIVE_CLK_MASK,
-	.d_SI_CONFIG_INACTIVE_DATA_LSB = QCA6180_SI_CONFIG_INACTIVE_DATA_LSB,
-	.d_SI_CONFIG_INACTIVE_DATA_MASK = QCA6180_SI_CONFIG_INACTIVE_DATA_MASK,
-	.d_SI_CONFIG_DIVIDER_LSB = QCA6180_SI_CONFIG_DIVIDER_LSB,
-	.d_SI_CONFIG_DIVIDER_MASK = QCA6180_SI_CONFIG_DIVIDER_MASK,
-	.d_SI_BASE_ADDRESS = QCA6180_SI_BASE_ADDRESS,
-	.d_SI_CONFIG_OFFSET = QCA6180_SI_CONFIG_OFFSET,
-	.d_SI_TX_DATA0_OFFSET = QCA6180_SI_TX_DATA0_OFFSET,
-	.d_SI_TX_DATA1_OFFSET = QCA6180_SI_TX_DATA1_OFFSET,
-	.d_SI_RX_DATA0_OFFSET = QCA6180_SI_RX_DATA0_OFFSET,
-	.d_SI_RX_DATA1_OFFSET = QCA6180_SI_RX_DATA1_OFFSET,
-	.d_SI_CS_OFFSET = QCA6180_SI_CS_OFFSET,
-	.d_SI_CS_DONE_ERR_MASK = QCA6180_SI_CS_DONE_ERR_MASK,
-	.d_SI_CS_DONE_INT_MASK = QCA6180_SI_CS_DONE_INT_MASK,
-	.d_SI_CS_START_LSB = QCA6180_SI_CS_START_LSB,
-	.d_SI_CS_START_MASK = QCA6180_SI_CS_START_MASK,
-	.d_SI_CS_RX_CNT_LSB = QCA6180_SI_CS_RX_CNT_LSB,
-	.d_SI_CS_RX_CNT_MASK = QCA6180_SI_CS_RX_CNT_MASK,
-	.d_SI_CS_TX_CNT_LSB = QCA6180_SI_CS_TX_CNT_LSB,
-	.d_SI_CS_TX_CNT_MASK = QCA6180_SI_CS_TX_CNT_MASK,
-	.d_BOARD_DATA_SZ = QCA6180_BOARD_DATA_SZ,
-	.d_BOARD_EXT_DATA_SZ = QCA6180_BOARD_EXT_DATA_SZ,
-	.d_MBOX_BASE_ADDRESS = QCA6180_MBOX_BASE_ADDRESS,
-	.d_LOCAL_SCRATCH_OFFSET = QCA6180_LOCAL_SCRATCH_OFFSET,
-	.d_CPU_CLOCK_OFFSET = QCA6180_CPU_CLOCK_OFFSET,
-	.d_LPO_CAL_OFFSET = QCA6180_LPO_CAL_OFFSET,
-	.d_GPIO_PIN10_OFFSET = QCA6180_GPIO_PIN10_OFFSET,
-	.d_GPIO_PIN11_OFFSET = QCA6180_GPIO_PIN11_OFFSET,
-	.d_GPIO_PIN12_OFFSET = QCA6180_GPIO_PIN12_OFFSET,
-	.d_GPIO_PIN13_OFFSET = QCA6180_GPIO_PIN13_OFFSET,
-	.d_CLOCK_GPIO_OFFSET = QCA6180_CLOCK_GPIO_OFFSET,
-	.d_CPU_CLOCK_STANDARD_LSB = QCA6180_CPU_CLOCK_STANDARD_LSB,
-	.d_CPU_CLOCK_STANDARD_MASK = QCA6180_CPU_CLOCK_STANDARD_MASK,
-	.d_LPO_CAL_ENABLE_LSB = QCA6180_LPO_CAL_ENABLE_LSB,
-	.d_LPO_CAL_ENABLE_MASK = QCA6180_LPO_CAL_ENABLE_MASK,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,
-	.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =
-	QCA6180_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,
-	.d_ANALOG_INTF_BASE_ADDRESS = QCA6180_ANALOG_INTF_BASE_ADDRESS,
-	.d_WLAN_MAC_BASE_ADDRESS = QCA6180_WLAN_MAC_BASE_ADDRESS,
-	.d_FW_INDICATOR_ADDRESS = QCA6180_FW_INDICATOR_ADDRESS,
-	.d_DRAM_BASE_ADDRESS = QCA6180_DRAM_BASE_ADDRESS,
-	.d_SOC_CORE_BASE_ADDRESS = QCA6180_SOC_CORE_BASE_ADDRESS,
-	.d_CORE_CTRL_ADDRESS = QCA6180_CORE_CTRL_ADDRESS,
-	.d_CE_COUNT = QCA6180_CE_COUNT,
-	.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
-	.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
-	.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
-	.d_PCIE_INTR_ENABLE_ADDRESS = QCA6180_PCIE_INTR_ENABLE_ADDRESS,
-	.d_PCIE_INTR_CLR_ADDRESS = QCA6180_PCIE_INTR_CLR_ADDRESS,
-	.d_PCIE_INTR_FIRMWARE_MASK = QCA6180_PCIE_INTR_FIRMWARE_MASK,
-	.d_PCIE_INTR_CE_MASK_ALL = QCA6180_PCIE_INTR_CE_MASK_ALL,
-	.d_CORE_CTRL_CPU_INTR_MASK = QCA6180_CORE_CTRL_CPU_INTR_MASK,
-	.d_SR_WR_INDEX_ADDRESS = QCA6180_SR_WR_INDEX_ADDRESS,
-	.d_DST_WATERMARK_ADDRESS = QCA6180_DST_WATERMARK_ADDRESS,
-	/* htt_rx.c */
-	.d_RX_MSDU_END_4_FIRST_MSDU_MASK =
-	QCA6180_RX_MSDU_END_4_FIRST_MSDU_MASK,
-	.d_RX_MSDU_END_4_FIRST_MSDU_LSB = QCA6180_RX_MSDU_END_4_FIRST_MSDU_LSB,
-	.d_RX_MPDU_START_0_SEQ_NUM_MASK = QCA6180_RX_MPDU_START_0_SEQ_NUM_MASK,
-	.d_RX_MPDU_START_0_SEQ_NUM_LSB = QCA6180_RX_MPDU_START_0_SEQ_NUM_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_LSB = QCA6180_RX_MPDU_START_2_PN_47_32_LSB,
-	.d_RX_MPDU_START_2_PN_47_32_MASK =
-	QCA6180_RX_MPDU_START_2_PN_47_32_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =
-		QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,
-	.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =
-		QCA6180_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,
-	.d_RX_MSDU_END_4_LAST_MSDU_MASK = QCA6180_RX_MSDU_END_4_LAST_MSDU_MASK,
-	.d_RX_MSDU_END_4_LAST_MSDU_LSB = QCA6180_RX_MSDU_END_4_LAST_MSDU_LSB,
-	.d_RX_ATTENTION_0_MCAST_BCAST_MASK =
-		QCA6180_RX_ATTENTION_0_MCAST_BCAST_MASK,
-	.d_RX_ATTENTION_0_MCAST_BCAST_LSB =
-	QCA6180_RX_ATTENTION_0_MCAST_BCAST_LSB,
-	.d_RX_ATTENTION_0_FRAGMENT_MASK = QCA6180_RX_ATTENTION_0_FRAGMENT_MASK,
-	.d_RX_ATTENTION_0_FRAGMENT_LSB = QCA6180_RX_ATTENTION_0_FRAGMENT_LSB,
-	.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =
-		QCA6180_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =
-		QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,
-	.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =
-		QCA6180_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =
-		QCA6180_RX_MSDU_START_0_MSDU_LENGTH_MASK,
-	.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =
-		QCA6180_RX_MSDU_START_0_MSDU_LENGTH_LSB,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =
-		QCA6180_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =
-		QCA6180_RX_MSDU_START_2_DECAP_FORMAT_MASK,
-	.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =
-		QCA6180_RX_MSDU_START_2_DECAP_FORMAT_LSB,
-	.d_RX_MPDU_START_0_ENCRYPTED_MASK =
-	QCA6180_RX_MPDU_START_0_ENCRYPTED_MASK,
-	.d_RX_MPDU_START_0_ENCRYPTED_LSB =
-	QCA6180_RX_MPDU_START_0_ENCRYPTED_LSB,
-	.d_RX_ATTENTION_0_MORE_DATA_MASK =
-	QCA6180_RX_ATTENTION_0_MORE_DATA_MASK,
-	.d_RX_ATTENTION_0_MSDU_DONE_MASK =
-	QCA6180_RX_ATTENTION_0_MSDU_DONE_MASK,
-	.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
-		QCA6180_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
-
-	/* PLL start */
-	.d_EFUSE_OFFSET = QCA6180_EFUSE_OFFSET,
-	.d_EFUSE_XTAL_SEL_MSB = QCA6180_EFUSE_XTAL_SEL_MSB,
-	.d_EFUSE_XTAL_SEL_LSB = QCA6180_EFUSE_XTAL_SEL_LSB,
-	.d_EFUSE_XTAL_SEL_MASK = QCA6180_EFUSE_XTAL_SEL_MASK,
-	.d_BB_PLL_CONFIG_OFFSET = QCA6180_BB_PLL_CONFIG_OFFSET,
-	.d_BB_PLL_CONFIG_OUTDIV_MSB = QCA6180_BB_PLL_CONFIG_OUTDIV_MSB,
-	.d_BB_PLL_CONFIG_OUTDIV_LSB = QCA6180_BB_PLL_CONFIG_OUTDIV_LSB,
-	.d_BB_PLL_CONFIG_OUTDIV_MASK = QCA6180_BB_PLL_CONFIG_OUTDIV_MASK,
-	.d_BB_PLL_CONFIG_FRAC_MSB = QCA6180_BB_PLL_CONFIG_FRAC_MSB,
-	.d_BB_PLL_CONFIG_FRAC_LSB = QCA6180_BB_PLL_CONFIG_FRAC_LSB,
-	.d_BB_PLL_CONFIG_FRAC_MASK = QCA6180_BB_PLL_CONFIG_FRAC_MASK,
-	.d_WLAN_PLL_SETTLE_TIME_MSB = QCA6180_WLAN_PLL_SETTLE_TIME_MSB,
-	.d_WLAN_PLL_SETTLE_TIME_LSB = QCA6180_WLAN_PLL_SETTLE_TIME_LSB,
-	.d_WLAN_PLL_SETTLE_TIME_MASK = QCA6180_WLAN_PLL_SETTLE_TIME_MASK,
-	.d_WLAN_PLL_SETTLE_OFFSET = QCA6180_WLAN_PLL_SETTLE_OFFSET,
-	.d_WLAN_PLL_SETTLE_SW_MASK = QCA6180_WLAN_PLL_SETTLE_SW_MASK,
-	.d_WLAN_PLL_SETTLE_RSTMASK = QCA6180_WLAN_PLL_SETTLE_RSTMASK,
-	.d_WLAN_PLL_SETTLE_RESET = QCA6180_WLAN_PLL_SETTLE_RESET,
-	.d_WLAN_PLL_CONTROL_NOPWD_MSB = QCA6180_WLAN_PLL_CONTROL_NOPWD_MSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_LSB = QCA6180_WLAN_PLL_CONTROL_NOPWD_LSB,
-	.d_WLAN_PLL_CONTROL_NOPWD_MASK = QCA6180_WLAN_PLL_CONTROL_NOPWD_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_MSB = QCA6180_WLAN_PLL_CONTROL_BYPASS_MSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_LSB = QCA6180_WLAN_PLL_CONTROL_BYPASS_LSB,
-	.d_WLAN_PLL_CONTROL_BYPASS_MASK = QCA6180_WLAN_PLL_CONTROL_BYPASS_MASK,
-	.d_WLAN_PLL_CONTROL_BYPASS_RESET =
-		QCA6180_WLAN_PLL_CONTROL_BYPASS_RESET,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MSB = QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_LSB = QCA6180_WLAN_PLL_CONTROL_CLK_SEL_LSB,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_MASK =
-		QCA6180_WLAN_PLL_CONTROL_CLK_SEL_MASK,
-	.d_WLAN_PLL_CONTROL_CLK_SEL_RESET =
-		QCA6180_WLAN_PLL_CONTROL_CLK_SEL_RESET,
-	.d_WLAN_PLL_CONTROL_REFDIV_MSB = QCA6180_WLAN_PLL_CONTROL_REFDIV_MSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_LSB = QCA6180_WLAN_PLL_CONTROL_REFDIV_LSB,
-	.d_WLAN_PLL_CONTROL_REFDIV_MASK = QCA6180_WLAN_PLL_CONTROL_REFDIV_MASK,
-	.d_WLAN_PLL_CONTROL_REFDIV_RESET =
-		QCA6180_WLAN_PLL_CONTROL_REFDIV_RESET,
-	.d_WLAN_PLL_CONTROL_DIV_MSB = QCA6180_WLAN_PLL_CONTROL_DIV_MSB,
-	.d_WLAN_PLL_CONTROL_DIV_LSB = QCA6180_WLAN_PLL_CONTROL_DIV_LSB,
-	.d_WLAN_PLL_CONTROL_DIV_MASK = QCA6180_WLAN_PLL_CONTROL_DIV_MASK,
-	.d_WLAN_PLL_CONTROL_DIV_RESET = QCA6180_WLAN_PLL_CONTROL_DIV_RESET,
-	.d_WLAN_PLL_CONTROL_OFFSET = QCA6180_WLAN_PLL_CONTROL_OFFSET,
-	.d_WLAN_PLL_CONTROL_SW_MASK = QCA6180_WLAN_PLL_CONTROL_SW_MASK,
-	.d_WLAN_PLL_CONTROL_RSTMASK = QCA6180_WLAN_PLL_CONTROL_RSTMASK,
-	.d_WLAN_PLL_CONTROL_RESET = QCA6180_WLAN_PLL_CONTROL_RESET,
-	.d_SOC_CORE_CLK_CTRL_OFFSET = QCA6180_SOC_CORE_CLK_CTRL_OFFSET,
-	.d_SOC_CORE_CLK_CTRL_DIV_MSB = QCA6180_SOC_CORE_CLK_CTRL_DIV_MSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_LSB = QCA6180_SOC_CORE_CLK_CTRL_DIV_LSB,
-	.d_SOC_CORE_CLK_CTRL_DIV_MASK = QCA6180_SOC_CORE_CLK_CTRL_DIV_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MSB =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_LSB =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_LSB,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_MASK =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_MASK,
-	.d_RTC_SYNC_STATUS_PLL_CHANGING_RESET =
-		QCA6180_RTC_SYNC_STATUS_PLL_CHANGING_RESET,
-	.d_RTC_SYNC_STATUS_OFFSET = QCA6180_RTC_SYNC_STATUS_OFFSET,
-	.d_SOC_CPU_CLOCK_OFFSET = QCA6180_SOC_CPU_CLOCK_OFFSET,
-	.d_SOC_CPU_CLOCK_STANDARD_MSB = QCA6180_SOC_CPU_CLOCK_STANDARD_MSB,
-	.d_SOC_CPU_CLOCK_STANDARD_LSB = QCA6180_SOC_CPU_CLOCK_STANDARD_LSB,
-	.d_SOC_CPU_CLOCK_STANDARD_MASK = QCA6180_SOC_CPU_CLOCK_STANDARD_MASK,
-	/* PLL end */
-	.d_SOC_POWER_REG_OFFSET = QCA6180_SOC_POWER_REG_OFFSET,
-	.d_PCIE_INTR_CAUSE_ADDRESS = QCA6180_PCIE_INTR_CAUSE_ADDRESS,
-	.d_SOC_RESET_CONTROL_ADDRESS = QCA6180_SOC_RESET_CONTROL_ADDRESS,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
-		QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
-	.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =
-		QCA6180_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
-	.d_SOC_RESET_CONTROL_CE_RST_MASK =
-		QCA6180_SOC_RESET_CONTROL_CE_RST_MASK,
-	.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
-		QCA6180_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
-	.d_CPU_INTR_ADDRESS = QCA6180_CPU_INTR_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
-		QCA6180_SOC_LF_TIMER_CONTROL0_ADDRESS,
-	.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
-		QCA6180_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
-	/* chip id start */
-	.d_SOC_CHIP_ID_ADDRESS = QCA6180_SOC_CHIP_ID_ADDRESS,
-	.d_SOC_CHIP_ID_VERSION_MASK = QCA6180_SOC_CHIP_ID_VERSION_MASK,
-	.d_SOC_CHIP_ID_VERSION_LSB = QCA6180_SOC_CHIP_ID_VERSION_LSB,
-	.d_SOC_CHIP_ID_REVISION_MASK = QCA6180_SOC_CHIP_ID_REVISION_MASK,
-	.d_SOC_CHIP_ID_REVISION_LSB = QCA6180_SOC_CHIP_ID_REVISION_LSB,
-	/* chip id end */
-	.d_A_SOC_CORE_SCRATCH_0_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_0_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_1_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_1_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_2_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_2_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_3_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_3_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_4_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_4_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_5_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_5_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_6_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_6_ADDRESS,
-	.d_A_SOC_CORE_SCRATCH_7_ADDRESS = QCA6180_A_SOC_CORE_SCRATCH_7_ADDRESS,
-	.d_A_SOC_CORE_SPARE_0_REGISTER = QCA6180_A_SOC_CORE_SPARE_0_REGISTER,
-	.d_PCIE_INTR_FIRMWARE_ROUTE_MASK =
-		QCA6180_PCIE_INTR_FIRMWARE_ROUTE_MASK,
-	.d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 =
-		QCA6180_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1,
-	.d_A_SOC_CORE_SPARE_1_REGISTER =
-		QCA6180_A_SOC_CORE_SPARE_1_REGISTER,
-	.d_A_SOC_CORE_PCIE_INTR_CLR_GRP1 =
-		QCA6180_A_SOC_CORE_PCIE_INTR_CLR_GRP1,
-	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 =
-		QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_0 =
-		QCA6180_A_SOC_PCIE_PCIE_SCRATCH_0,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_1 =
-		QCA6180_A_SOC_PCIE_PCIE_SCRATCH_1,
-	.d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA =
-		QCA6180_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA,
-	.d_A_SOC_PCIE_PCIE_SCRATCH_2 = QCA6180_A_SOC_PCIE_PCIE_SCRATCH_2,
-	.d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK =
-		QCA6180_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK,
-
-	.d_WLAN_DEBUG_INPUT_SEL_OFFSET = QCA6180_WLAN_DEBUG_INPUT_SEL_OFFSET,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
-	.d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =
-		QCA6180_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
-	.d_WLAN_DEBUG_CONTROL_OFFSET = QCA6180_WLAN_DEBUG_CONTROL_OFFSET,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MSB =
-		QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_LSB =
-		QCA6180_WLAN_DEBUG_CONTROL_ENABLE_LSB,
-	.d_WLAN_DEBUG_CONTROL_ENABLE_MASK =
-		QCA6180_WLAN_DEBUG_CONTROL_ENABLE_MASK,
-	.d_WLAN_DEBUG_OUT_OFFSET = QCA6180_WLAN_DEBUG_OUT_OFFSET,
-	.d_WLAN_DEBUG_OUT_DATA_MSB = QCA6180_WLAN_DEBUG_OUT_DATA_MSB,
-	.d_WLAN_DEBUG_OUT_DATA_LSB = QCA6180_WLAN_DEBUG_OUT_DATA_LSB,
-	.d_WLAN_DEBUG_OUT_DATA_MASK = QCA6180_WLAN_DEBUG_OUT_DATA_MASK,
-	.d_AMBA_DEBUG_BUS_OFFSET = QCA6180_AMBA_DEBUG_BUS_OFFSET,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =
-		QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =
-		QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =
-		QCA6180_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
-	.d_AMBA_DEBUG_BUS_SEL_MSB = QCA6180_AMBA_DEBUG_BUS_SEL_MSB,
-	.d_AMBA_DEBUG_BUS_SEL_LSB = QCA6180_AMBA_DEBUG_BUS_SEL_LSB,
-	.d_AMBA_DEBUG_BUS_SEL_MASK = QCA6180_AMBA_DEBUG_BUS_SEL_MASK,
-};
-
-struct hostdef_s qca6180_hostdef = {
-	.d_INT_STATUS_ENABLE_ERROR_LSB = QCA6180_INT_STATUS_ENABLE_ERROR_LSB,
-	.d_INT_STATUS_ENABLE_ERROR_MASK = QCA6180_INT_STATUS_ENABLE_ERROR_MASK,
-	.d_INT_STATUS_ENABLE_CPU_LSB = QCA6180_INT_STATUS_ENABLE_CPU_LSB,
-	.d_INT_STATUS_ENABLE_CPU_MASK = QCA6180_INT_STATUS_ENABLE_CPU_MASK,
-	.d_INT_STATUS_ENABLE_COUNTER_LSB =
-		QCA6180_INT_STATUS_ENABLE_COUNTER_LSB,
-	.d_INT_STATUS_ENABLE_COUNTER_MASK =
-		QCA6180_INT_STATUS_ENABLE_COUNTER_MASK,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =
-		QCA6180_INT_STATUS_ENABLE_MBOX_DATA_LSB,
-	.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =
-		QCA6180_INT_STATUS_ENABLE_MBOX_DATA_MASK,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =
-		QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =
-		QCA6180_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =
-		QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,
-	.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =
-		QCA6180_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =
-		QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_LSB,
-	.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =
-		QCA6180_COUNTER_INT_STATUS_ENABLE_BIT_MASK,
-	.d_INT_STATUS_ENABLE_ADDRESS = QCA6180_INT_STATUS_ENABLE_ADDRESS,
-	.d_CPU_INT_STATUS_ENABLE_BIT_LSB =
-		QCA6180_CPU_INT_STATUS_ENABLE_BIT_LSB,
-	.d_CPU_INT_STATUS_ENABLE_BIT_MASK =
-		QCA6180_CPU_INT_STATUS_ENABLE_BIT_MASK,
-	.d_HOST_INT_STATUS_ADDRESS = QCA6180_HOST_INT_STATUS_ADDRESS,
-	.d_CPU_INT_STATUS_ADDRESS = QCA6180_CPU_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_ADDRESS = QCA6180_ERROR_INT_STATUS_ADDRESS,
-	.d_ERROR_INT_STATUS_WAKEUP_MASK = QCA6180_ERROR_INT_STATUS_WAKEUP_MASK,
-	.d_ERROR_INT_STATUS_WAKEUP_LSB = QCA6180_ERROR_INT_STATUS_WAKEUP_LSB,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =
-		QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,
-	.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =
-		QCA6180_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =
-		QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_MASK,
-	.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =
-		QCA6180_ERROR_INT_STATUS_TX_OVERFLOW_LSB,
-	.d_COUNT_DEC_ADDRESS = QCA6180_COUNT_DEC_ADDRESS,
-	.d_HOST_INT_STATUS_CPU_MASK = QCA6180_HOST_INT_STATUS_CPU_MASK,
-	.d_HOST_INT_STATUS_CPU_LSB = QCA6180_HOST_INT_STATUS_CPU_LSB,
-	.d_HOST_INT_STATUS_ERROR_MASK = QCA6180_HOST_INT_STATUS_ERROR_MASK,
-	.d_HOST_INT_STATUS_ERROR_LSB = QCA6180_HOST_INT_STATUS_ERROR_LSB,
-	.d_HOST_INT_STATUS_COUNTER_MASK = QCA6180_HOST_INT_STATUS_COUNTER_MASK,
-	.d_HOST_INT_STATUS_COUNTER_LSB = QCA6180_HOST_INT_STATUS_COUNTER_LSB,
-	.d_RX_LOOKAHEAD_VALID_ADDRESS = QCA6180_RX_LOOKAHEAD_VALID_ADDRESS,
-	.d_WINDOW_DATA_ADDRESS = QCA6180_WINDOW_DATA_ADDRESS,
-	.d_WINDOW_READ_ADDR_ADDRESS = QCA6180_WINDOW_READ_ADDR_ADDRESS,
-	.d_WINDOW_WRITE_ADDR_ADDRESS = QCA6180_WINDOW_WRITE_ADDR_ADDRESS,
-	.d_SOC_GLOBAL_RESET_ADDRESS = QCA6180_SOC_GLOBAL_RESET_ADDRESS,
-	.d_RTC_STATE_ADDRESS = QCA6180_RTC_STATE_ADDRESS,
-	.d_RTC_STATE_COLD_RESET_MASK = QCA6180_RTC_STATE_COLD_RESET_MASK,
-	.d_PCIE_LOCAL_BASE_ADDRESS = QCA6180_PCIE_LOCAL_BASE_ADDRESS,
-	.d_PCIE_SOC_WAKE_RESET = QCA6180_PCIE_SOC_WAKE_RESET,
-	.d_PCIE_SOC_WAKE_ADDRESS = QCA6180_PCIE_SOC_WAKE_ADDRESS,
-	.d_PCIE_SOC_WAKE_V_MASK = QCA6180_PCIE_SOC_WAKE_V_MASK,
-	.d_RTC_STATE_V_MASK = QCA6180_RTC_STATE_V_MASK,
-	.d_RTC_STATE_V_LSB = QCA6180_RTC_STATE_V_LSB,
-	.d_FW_IND_EVENT_PENDING = QCA6180_FW_IND_EVENT_PENDING,
-	.d_FW_IND_INITIALIZED = QCA6180_FW_IND_INITIALIZED,
-	.d_FW_IND_HELPER = QCA6180_FW_IND_HELPER,
-	.d_RTC_STATE_V_ON = QCA6180_RTC_STATE_V_ON,
-#if defined(SDIO_3_0)
-	.d_HOST_INT_STATUS_MBOX_DATA_MASK =
-		QCA6180_HOST_INT_STATUS_MBOX_DATA_MASK,
-	.d_HOST_INT_STATUS_MBOX_DATA_LSB =
-		QCA6180_HOST_INT_STATUS_MBOX_DATA_LSB,
-#endif
-	.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
-	.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
-	.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
-	.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,
-	.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
-	.d_HOST_CE_COUNT = 8,
-	.d_ENABLE_MSI = 0,
-	.d_MUX_ID_MASK = 0xf000,
-	.d_TRANSACTION_ID_MASK = 0x0fff,
-	.d_DESC_DATA_FLAG_MASK = 0x1FFFE3E0,
-	.d_A_SOC_PCIE_PCIE_BAR0_START = QCA6180_A_SOC_PCIE_PCIE_BAR0_START,
-};
-
-
-struct ce_reg_def qca6180_ce_targetdef = {
-	/* copy_engine.c  */
-	.d_DST_WR_INDEX_ADDRESS = QCA6180_DST_WR_INDEX_ADDRESS,
-	.d_SRC_WATERMARK_ADDRESS = QCA6180_SRC_WATERMARK_ADDRESS,
-	.d_SRC_WATERMARK_LOW_MASK = QCA6180_SRC_WATERMARK_LOW_MASK,
-	.d_SRC_WATERMARK_HIGH_MASK = QCA6180_SRC_WATERMARK_HIGH_MASK,
-	.d_DST_WATERMARK_LOW_MASK = QCA6180_DST_WATERMARK_LOW_MASK,
-	.d_DST_WATERMARK_HIGH_MASK = QCA6180_DST_WATERMARK_HIGH_MASK,
-	.d_CURRENT_SRRI_ADDRESS = QCA6180_CURRENT_SRRI_ADDRESS,
-	.d_CURRENT_DRRI_ADDRESS = QCA6180_CURRENT_DRRI_ADDRESS,
-	.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
-		QCA6180_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
-		QCA6180_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
-		QCA6180_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
-	.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
-		QCA6180_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
-	.d_HOST_IS_ADDRESS = QCA6180_HOST_IS_ADDRESS,
-	.d_MISC_IS_ADDRESS = QCA6180_MISC_IS_ADDRESS,
-	.d_HOST_IS_COPY_COMPLETE_MASK = QCA6180_HOST_IS_COPY_COMPLETE_MASK,
-	.d_CE_WRAPPER_BASE_ADDRESS = QCA6180_CE_WRAPPER_BASE_ADDRESS,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
-		QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,
-	.d_CE_DDR_ADDRESS_FOR_RRI_LOW = QCA6180_CE_WRAPPER_INDEX_BASE_LOW,
-	.d_CE_DDR_ADDRESS_FOR_RRI_HIGH = QCA6180_CE_WRAPPER_INDEX_BASE_HIGH,
-	.d_HOST_IE_ADDRESS = QCA6180_HOST_IE_ADDRESS,
-	.d_HOST_IE_COPY_COMPLETE_MASK = QCA6180_HOST_IE_COPY_COMPLETE_MASK,
-	.d_SR_BA_ADDRESS = QCA6180_SR_BA_ADDRESS,
-	.d_SR_SIZE_ADDRESS = QCA6180_SR_SIZE_ADDRESS,
-	.d_CE_CTRL1_ADDRESS = QCA6180_CE_CTRL1_ADDRESS,
-	.d_CE_CTRL1_DMAX_LENGTH_MASK = QCA6180_CE_CTRL1_DMAX_LENGTH_MASK,
-	.d_DR_BA_ADDRESS = QCA6180_DR_BA_ADDRESS,
-	.d_DR_SIZE_ADDRESS = QCA6180_DR_SIZE_ADDRESS,
-	.d_CE_CMD_REGISTER = QCA6180_CE_CMD_REGISTER,
-	.d_CE_MSI_ADDRESS = QCA6180_CE_MSI_ADDRESS,
-	.d_CE_MSI_ADDRESS_HIGH = QCA6180_CE_MSI_ADDRESS_HIGH,
-	.d_CE_MSI_DATA = QCA6180_CE_MSI_DATA,
-	.d_CE_MSI_ENABLE_BIT = QCA6180_CE_MSI_ENABLE_BIT,
-	.d_MISC_IE_ADDRESS = QCA6180_MISC_IE_ADDRESS,
-	.d_MISC_IS_AXI_ERR_MASK = QCA6180_MISC_IS_AXI_ERR_MASK,
-	.d_MISC_IS_DST_ADDR_ERR_MASK = QCA6180_MISC_IS_DST_ADDR_ERR_MASK,
-	.d_MISC_IS_SRC_LEN_ERR_MASK = QCA6180_MISC_IS_SRC_LEN_ERR_MASK,
-	.d_MISC_IS_DST_MAX_LEN_VIO_MASK = QCA6180_MISC_IS_DST_MAX_LEN_VIO_MASK,
-	.d_MISC_IS_DST_RING_OVERFLOW_MASK =
-		QCA6180_MISC_IS_DST_RING_OVERFLOW_MASK,
-	.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
-		QCA6180_MISC_IS_SRC_RING_OVERFLOW_MASK,
-	.d_SRC_WATERMARK_LOW_LSB = QCA6180_SRC_WATERMARK_LOW_LSB,
-	.d_SRC_WATERMARK_HIGH_LSB = QCA6180_SRC_WATERMARK_HIGH_LSB,
-	.d_DST_WATERMARK_LOW_LSB = QCA6180_DST_WATERMARK_LOW_LSB,
-	.d_DST_WATERMARK_HIGH_LSB = QCA6180_DST_WATERMARK_HIGH_LSB,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
-		QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
-	.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
-		QCA6180_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
-	.d_CE_CTRL1_DMAX_LENGTH_LSB = QCA6180_CE_CTRL1_DMAX_LENGTH_LSB,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
-		QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
-		QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
-	.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
-		QCA6180_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
-		QCA6180_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-	.d_CE_WRAPPER_DEBUG_OFFSET = QCA6180_CE_WRAPPER_DEBUG_OFFSET,
-	.d_CE_WRAPPER_DEBUG_SEL_MSB = QCA6180_CE_WRAPPER_DEBUG_SEL_MSB,
-	.d_CE_WRAPPER_DEBUG_SEL_LSB = QCA6180_CE_WRAPPER_DEBUG_SEL_LSB,
-	.d_CE_WRAPPER_DEBUG_SEL_MASK = QCA6180_CE_WRAPPER_DEBUG_SEL_MASK,
-	.d_CE_DEBUG_OFFSET = QCA6180_CE_DEBUG_OFFSET,
-	.d_CE_DEBUG_SEL_MSB = QCA6180_CE_DEBUG_SEL_MSB,
-	.d_CE_DEBUG_SEL_LSB = QCA6180_CE_DEBUG_SEL_LSB,
-	.d_CE_DEBUG_SEL_MASK = QCA6180_CE_DEBUG_SEL_MASK,
-	.d_CE0_BASE_ADDRESS = QCA6180_CE0_BASE_ADDRESS,
-	.d_CE1_BASE_ADDRESS = QCA6180_CE1_BASE_ADDRESS,
-};
-
-
-struct host_shadow_regs_s qca6180_host_shadow_regs = {
-	.d_A_LOCAL_SHADOW_REG_VALUE_0  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_0,
-	.d_A_LOCAL_SHADOW_REG_VALUE_1  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_1,
-	.d_A_LOCAL_SHADOW_REG_VALUE_2  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_2,
-	.d_A_LOCAL_SHADOW_REG_VALUE_3  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_3,
-	.d_A_LOCAL_SHADOW_REG_VALUE_4  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_4,
-	.d_A_LOCAL_SHADOW_REG_VALUE_5  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_5,
-	.d_A_LOCAL_SHADOW_REG_VALUE_6  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_6,
-	.d_A_LOCAL_SHADOW_REG_VALUE_7  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_7,
-	.d_A_LOCAL_SHADOW_REG_VALUE_8  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_8,
-	.d_A_LOCAL_SHADOW_REG_VALUE_9  =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_9,
-	.d_A_LOCAL_SHADOW_REG_VALUE_10 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_10,
-	.d_A_LOCAL_SHADOW_REG_VALUE_11 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_11,
-	.d_A_LOCAL_SHADOW_REG_VALUE_12 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_12,
-	.d_A_LOCAL_SHADOW_REG_VALUE_13 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_13,
-	.d_A_LOCAL_SHADOW_REG_VALUE_14 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_14,
-	.d_A_LOCAL_SHADOW_REG_VALUE_15 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_15,
-	.d_A_LOCAL_SHADOW_REG_VALUE_16 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_16,
-	.d_A_LOCAL_SHADOW_REG_VALUE_17 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_17,
-	.d_A_LOCAL_SHADOW_REG_VALUE_18 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_18,
-	.d_A_LOCAL_SHADOW_REG_VALUE_19 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_19,
-	.d_A_LOCAL_SHADOW_REG_VALUE_20 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_20,
-	.d_A_LOCAL_SHADOW_REG_VALUE_21 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_21,
-	.d_A_LOCAL_SHADOW_REG_VALUE_22 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_22,
-	.d_A_LOCAL_SHADOW_REG_VALUE_23 =
-		QCA6180_A_LOCAL_SHADOW_REG_VALUE_23,
-
-};
-
-#endif /* _QCA6180DEF_H_ */

core/hif/src/regtable.c

@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include "bmi_msg.h"
-#include "targaddrs.h"
-#include "cepci.h"
-#include "regtable.h"
-#include "ar9888def.h"
-#include "ar6320def.h"
-#include "ar6320v2def.h"
-#include "qca6180def.h"
-#include "ol_if_athvar.h"
-#include "hif.h"
-#include "adrastea_reg_def.h"
-
-void target_register_tbl_attach(struct ol_softc *scn, u32 target_type)
-{
-	switch (target_type) {
-	case TARGET_TYPE_AR9888:
-		scn->targetdef = &ar9888_targetdef;
-		scn->target_ce_def = &ar9888_ce_targetdef;
-		break;
-	case TARGET_TYPE_AR6320:
-		scn->targetdef = &ar6320_targetdef;
-		scn->target_ce_def = &ar6320_ce_targetdef;
-		break;
-	case TARGET_TYPE_AR6320V2:
-		scn->targetdef = &ar6320v2_targetdef;
-		scn->target_ce_def = &ar6320v2_ce_targetdef;
-		break;
-	case TARGET_TYPE_QCA6180:
-		scn->targetdef = &qca6180_targetdef;
-		scn->target_ce_def = &qca6180_ce_targetdef;
-		break;
-	case TARGET_TYPE_ADRASTEA:
-		scn->targetdef = &adrastea_targetdef;
-		scn->target_ce_def = &adrastea_ce_targetdef;
-		break;
-	default:
-		break;
-	}
-}
-
-void hif_register_tbl_attach(struct ol_softc *scn, u32 hif_type)
-{
-	switch (hif_type) {
-	case HIF_TYPE_AR9888:
-		scn->hostdef = &ar9888_hostdef;
-		break;
-	case HIF_TYPE_AR6320:
-		scn->hostdef = &ar6320_hostdef;
-		break;
-	case HIF_TYPE_AR6320V2:
-		scn->hostdef = &ar6320v2_hostdef;
-		break;
-	case HIF_TYPE_QCA6180:
-		scn->hostdef = &qca6180_hostdef;
-		scn->host_shadow_regs = &qca6180_host_shadow_regs;
-		break;
-	case HIF_TYPE_ADRASTEA:
-		scn->hostdef = &adrastea_hostdef;
-		scn->host_shadow_regs = &adrastea_host_shadow_regs;
-		break;
-	default:
-		break;
-	}
-}

core/hif/src/snoc/hif_io32_snoc.h

@@ -1,236 +0,0 @@
-/*
- * Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-/**
- * DOC: hif_io32_snoc.h
- *
- * snoc specific implementations and configurations
- */
-
-#ifndef __HIF_IO32_SNOC_H__
-#define __HIF_IO32_SNOC_H__
-
-#ifdef HIF_PCI
-#error snoc and pci cannot be supported in parrallel at this time
-#endif
-
-#include "hif.h"
-#include "regtable.h"
-#include "ce_reg.h"
-#include "cdf_atomic.h"
-#include <soc/qcom/icnss.h>
-#include "hif_main.h"
-#include "hif_debug.h"
-
-/**
- * Following features are not supported for snoc bus
- * Force 0 and consider moving corresponding code into
- * pci specific files
- */
-#define CONFIG_ATH_PCIE_MAX_PERF 0
-#define CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 0
-#define CONFIG_ATH_PCIE_ACCESS_LIKELY 0
-#define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 0
-
-#define A_TARGET_ACCESS_LIKELY(scn)
-#define A_TARGET_ACCESS_UNLIKELY(scn)
-#define A_TARGET_ACCESS_BEGIN_RET_PTR(scn)
-#define A_TARGET_ACCESS_END_RET_PTR(scn)
-#define A_TARGET_ACCESS_BEGIN(scn)
-#define A_TARGET_ACCESS_END(scn)
-#define A_TARGET_ACCESS_BEGIN_RET(scn)
-#define A_TARGET_ACCESS_END_RET(scn)
-#define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val)
-#define A_TARGET_ACCESS_END_RET_EXT(scn, val)
-
-#define Q_TARGET_ACCESS_BEGIN(scn) 0
-#define Q_TARGET_ACCESS_END(scn) 0
-
-static inline void hif_pci_cancel_deferred_target_sleep(struct ol_softc *scn)
-{
-	return;
-}
-
-static inline void hif_target_sleep_state_adjust(struct ol_softc *scn,
-						bool sleep_ok, bool wait_for_it)
-{
-	return;
-}
-
-/**
- * soc_wake_reset() - soc_wake_reset
- * @scn: ol_softc
- *
- * Return: void
- */
-static inline void soc_wake_reset(struct ol_softc *scn)
-{
-}
-
-/**
- * hif_write32_mb - SNOC write 32
- * @addr: physical address
- * @value: value
- *
- * Return: N/A
- */
-static inline void hif_write32_mb(void __iomem *addr, uint32_t value)
-{
-	wmb(); /* write memory barrier */
-	writel_relaxed((value), (addr));
-	wmb(); /* write memory barrier */
-}
-
-/**
- * hif_read32_mb - SNOC read 32
- * @addr: physical address
- *
- * Return: N/A
- */
-static inline uint32_t hif_read32_mb(void __iomem *addr)
-{
-	uint32_t tmp;
-	rmb(); /* read memory barrier */
-	tmp = readl_relaxed(addr);
-	rmb(); /* read memory barrier */
-	return tmp;
-}
-
-#define A_TARGET_READ(scn, offset) \
-	hif_read32_mb(scn->mem + (offset))
-#define A_TARGET_WRITE(scn, offset, value) \
-	hif_write32_mb((scn->mem + offset), (value))
-
-#define ADRASTEA_CE_INTR_ENABLES 0x002F00A8
-#define ADRASTEA_CE_INTR_ENABLES_SET "COMING IN REGISTER SET36"
-#define ADRASTEA_CE_INTR_ENABLES_CLEAR "COMING IN REGISTER SET36"
-
-#define ADRASTEA_CE_INTR_STATUS 0x002F00AC
-
-static inline void ce_enable_irq_in_individual_register(struct ol_softc *scn,
-		int ce_id)
-{
-	uint32_t offset;
-	offset = HOST_IE_ADDRESS + CE_BASE_ADDRESS(ce_id);
-	hif_write32_mb(scn->mem + offset, 1);
-	hif_read32_mb(scn->mem + offset);
-}
-
-static inline void ce_disable_irq_in_individual_register(struct ol_softc *scn,
-		int ce_id)
-{
-	uint32_t offset;
-	offset = HOST_IE_ADDRESS + CE_BASE_ADDRESS(ce_id);
-	hif_write32_mb(scn->mem + offset, 0);
-	hif_read32_mb(scn->mem + offset);
-}
-
-static inline void ce_read_irq_group_status(struct ol_softc *scn)
-{
-	uint32_t group_status = 0;
-	group_status = hif_read32_mb(scn->mem +
-			ADRASTEA_CE_INTR_STATUS);
-}
-
-static inline void ce_clear_irq_group_status(struct ol_softc *scn, int mask)
-{
-	uint32_t group_status = 0;
-	group_status = hif_read32_mb(scn->mem +
-			ADRASTEA_CE_INTR_STATUS);
-
-	hif_write32_mb(scn->mem +
-			ADRASTEA_CE_INTR_STATUS, mask);
-
-	group_status = hif_read32_mb(scn->mem +
-			ADRASTEA_CE_INTR_STATUS);
-}
-
-/* this will need to be changed when we move to reg set 36
- * because we will have set & clear registers provided
- */
-static inline void ce_enable_irq_in_group_reg(struct ol_softc *scn,
-		int mask)
-{
-	int new_mask = 0;
-	new_mask = hif_read32_mb(scn->mem +
-			ADRASTEA_CE_INTR_ENABLES);
-
-	new_mask |= mask;
-
-	hif_write32_mb(scn->mem +
-			ADRASTEA_CE_INTR_ENABLES, new_mask);
-	mask = hif_read32_mb(scn->mem +
-			ADRASTEA_CE_INTR_ENABLES);
-}
-
-/* this will need to be changed when we move to reg set 36
- * because we will have set & clear registers provided
- */
-static inline void ce_disable_irq_in_group_reg(struct ol_softc *scn,
-		int mask)
-{
-	int new_mask = 0;
-	new_mask = hif_read32_mb(scn->mem +
-			ADRASTEA_CE_INTR_ENABLES);
-
-	new_mask &= ~mask;
-
-	hif_write32_mb(scn->mem +
-			ADRASTEA_CE_INTR_ENABLES, new_mask);
-	mask = hif_read32_mb(scn->mem +
-			ADRASTEA_CE_INTR_ENABLES);
-}
-
-/**
- * ce_irq_enable() - enable copy engine IRQ
- * @scn: struct ol_softc
- * @ce_id: ce_id
- *
- * Return: N/A
- */
-static inline void ce_irq_enable(struct ol_softc *scn,
-		int ce_id)
-{
-	icnss_enable_irq(ce_id);
-	ce_enable_irq_in_individual_register(scn, ce_id);
-	ce_enable_irq_in_group_reg(scn, 1<<ce_id);
-}
-
-/**
- * ce_irq_disable() - disable copy engine IRQ
- * @scn: struct ol_softc
- * @ce_id: ce_id
- *
- * Return: N/A
- */
-static inline void ce_irq_disable(struct ol_softc *scn, int ce_id)
-{
-	ce_disable_irq_in_group_reg(scn, 1<<ce_id);
-	ce_clear_irq_group_status(scn, 1<<ce_id);
-	ce_disable_irq_in_individual_register(scn, ce_id);
-}
-#endif

core/hif/src/snoc/if_snoc.c

@@ -1,315 +0,0 @@
-/*
- * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-/**
- * DOC: if_snoc.c
- *
- * c file for snoc specif implementations.
- */
-
-#include "hif.h"
-#include "hif_main.h"
-#include "hif_debug.h"
-#include "hif_io32.h"
-#include "ce_main.h"
-#include "ce_tasklet.h"
-
-/**
- * hif_bus_prevent_linkdown(): prevent linkdown
- *
- * Dummy function for busses and platforms that do not support
- * link down.  This may need to be replaced with a wakelock.
- *
- * This is duplicated here because CONFIG_CNSS can be defined
- * even though it is not used for the snoc bus.
- */
-void hif_bus_prevent_linkdown(struct ol_softc *scn, bool flag)
-{
-	HIF_ERROR("wlan: %s pcie power collapse ignored",
-			(flag ? "disable" : "enable"));
-}
-
-/**
- * hif_targ_is_awake(): check if target is awake
- *
- * This function returns true if the target is awake
- *
- * @scn: struct ol_softc
- * @mem: mapped mem base
- *
- * Return: bool
- */
-bool hif_targ_is_awake(struct ol_softc *scn, void *__iomem *mem)
-{
-	return true;
-}
-
-/**
- * hif_reset_soc(): reset soc
- *
- * this function resets soc
- *
- * @hif_ctx: HIF context
- *
- * Return: void
- */
-/* Function to reset SoC */
-void hif_reset_soc(void *hif_ctx)
-{
-}
-
-/**
- * hif_disable_isr(): disable isr
- *
- * This function disables isr and kills tasklets
- *
- * @hif_ctx: struct ol_softc
- *
- * Return: void
- */
-void hif_disable_isr(void *hif_ctx)
-{
-	struct ol_softc *scn = (struct ol_softc *)hif_ctx;
-
-	hif_nointrs(scn);
-	ce_tasklet_kill(scn->hif_hdl);
-	cdf_atomic_set(&scn->active_tasklet_cnt, 0);
-}
-
-/**
- * hif_dump_snoc_registers(): dump CE debug registers
- *
- * This function dumps CE debug registers
- *
- * @scn: struct ol_softc
- *
- * Return: void
- */
-static void hif_dump_snoc_registers(struct ol_softc *scn)
-{
-	return;
-}
-
-/**
- * hif_dump_registers(): dump bus debug registers
- *
- * This function dumps hif bus debug registers
- *
- * @scn: struct ol_softc
- *
- * Return: 0 for success or error code
- */
-int hif_dump_registers(struct ol_softc *scn)
-{
-	int status;
-
-	status = hif_dump_ce_registers(scn);
-	if (status)
-		return status;
-	hif_dump_snoc_registers(scn);
-
-	return 0;
-}
-
-/**
- * hif_bus_suspend() - suspend the bus
- *
- * This function suspends the bus, but snoc doesn't need to suspend.
- * Therefore do nothing.
- *
- * Return: 0 for success and non-zero for failure
- */
-int hif_bus_suspend(void)
-{
-	return 0;
-}
-
-/**
- * hif_bus_resume() - hif resume API
- *
- * This function resumes the bus. but snoc doesn't need to resume.
- * Therefore do nothing.
- *
- * Return: 0 for success and non-zero for failure
- */
-int hif_bus_resume(void)
-{
-	return 0;
-}
-
-/**
- * hif_enable_power_gating(): enable HW power gating
- *
- * Return: n/a
- */
-void hif_enable_power_gating(void *hif_ctx)
-{
-}
-
-/**
- * hif_disable_aspm(): hif_disable_aspm
- *
- * Return: n/a
- */
-void hif_disable_aspm(void)
-{
-}
-
-/**
- * hif_bus_close(): hif_bus_close
- *
- * Return: n/a
- */
-void hif_bus_close(struct ol_softc *scn)
-{
-}
-
-/**
- * hif_bus_open(): hif_bus_open
- * @scn: scn
- * @bus_type: bus type
- *
- * Return: n/a
- */
-CDF_STATUS hif_bus_open(struct ol_softc *scn, enum ath_hal_bus_type bus_type)
-{
-	return CDF_STATUS_SUCCESS;
-}
-
-/**
- * hif_get_target_type(): Get the target type
- *
- * This function is used to query the target type.
- *
- * @ol_sc: ol_softc struct pointer
- * @dev: device pointer
- * @bdev: bus dev pointer
- * @bid: bus id pointer
- * @hif_type: HIF type such as HIF_TYPE_QCA6180
- * @target_type: target type such as TARGET_TYPE_QCA6180
- *
- * Return: 0 for success
- */
-int hif_get_target_type(struct ol_softc *ol_sc, struct device *dev,
-	void *bdev, const hif_bus_id *bid, uint32_t *hif_type,
-	uint32_t *target_type)
-{
-	/* TODO: need to use CNSS's HW version. Hard code for now */
-#ifdef QCA_WIFI_3_0_ADRASTEA
-	*hif_type = HIF_TYPE_ADRASTEA;
-	*target_type = TARGET_TYPE_ADRASTEA;
-#else
-	*hif_type = 0;
-	*target_type = 0;
-#endif
-	return 0;
-}
-
-/**
- * hif_enable_bus(): hif_enable_bus
- * @dev: dev
- * @bdev: bus dev
- * @bid: bus id
- * @type: bus type
- *
- * Return: CDF_STATUS
- */
-CDF_STATUS hif_enable_bus(struct ol_softc *ol_sc,
-			  struct device *dev, void *bdev,
-			  const hif_bus_id *bid,
-			  enum hif_enable_type type)
-{
-	int ret;
-	int hif_type;
-	int target_type;
-	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
-	if (ret) {
-		HIF_ERROR("%s: failed to set dma mask error = %d",
-				__func__, ret);
-		return ret;
-	}
-
-	if (!ol_sc) {
-		HIF_ERROR("%s: hif_ctx is NULL", __func__);
-		return CDF_STATUS_E_NOMEM;
-	}
-
-	ol_sc->aps_osdev.device = dev;
-	ol_sc->aps_osdev.bc.bc_handle = (void *)ol_sc->mem;
-	ol_sc->aps_osdev.bc.bc_bustype = type;
-
-	ret = hif_get_target_type(ol_sc, dev, bdev, bid,
-			&hif_type, &target_type);
-	if (ret < 0) {
-		HIF_ERROR("%s: invalid device id/revision_id", __func__);
-		return CDF_STATUS_E_FAILURE;
-	}
-
-	hif_register_tbl_attach(ol_sc, hif_type);
-	target_register_tbl_attach(ol_sc, target_type);
-
-	HIF_TRACE("%s: X - hif_type = 0x%x, target_type = 0x%x",
-		  __func__, hif_type, target_type);
-
-	ret = hif_init_cdf_ctx(ol_sc);
-	if (ret != 0) {
-		HIF_ERROR("%s: cannot init CDF", __func__);
-		return CDF_STATUS_E_FAILURE;
-	}
-
-	return CDF_STATUS_SUCCESS;
-}
-
-/**
- * hif_disable_bus(): hif_disable_bus
- *
- * This function disables the bus
- *
- * @bdev: bus dev
- *
- * Return: none
- */
-void hif_disable_bus(void *bdev)
-{
-}
-
-/**
- * hif_nointrs(): disable IRQ
- *
- * This function stops interrupt(s)
- *
- * @scn: struct ol_softc
- *
- * Return: none
- */
-void hif_nointrs(struct ol_softc *scn)
-{
-	if (scn->request_irq_done) {
-		ce_unregister_irq(scn->hif_hdl, 0xfff);
-		scn->request_irq_done = false;
-	}
-}

core/htc/dl_list.h

@@ -1,208 +0,0 @@
-/*
- * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-/* ============================================================================== */
-/* Double-link list definitions (adapted from Atheros SDIO stack) */
-/* */
-/* Author(s): ="Atheros" */
-/* ============================================================================== */
-
-#ifndef __DL_LIST_H___
-#define __DL_LIST_H___
-
-#define A_CONTAINING_STRUCT(address, struct_type, field_name) \
-	((struct_type *)((char *)(address) - (char *)(&((struct_type *)0)->field_name)))
-
-/* list functions */
-/* pointers for the list */
-typedef struct _DL_LIST {
-	struct _DL_LIST *pPrev;
-	struct _DL_LIST *pNext;
-} DL_LIST, *PDL_LIST;
-/*
- * DL_LIST_INIT , initialize doubly linked list
- */
-#define DL_LIST_INIT(pList) \
-	{(pList)->pPrev = pList; (pList)->pNext = pList; }
-
-/* faster macro to init list and add a single item */
-#define DL_LIST_INIT_AND_ADD(pList,pItem) \
-	{   (pList)->pPrev = (pItem); \
-	    (pList)->pNext = (pItem); \
-	    (pItem)->pNext = (pList); \
-	    (pItem)->pPrev = (pList); \
-	}
-
-#define DL_LIST_IS_EMPTY(pList) (((pList)->pPrev == (pList)) && ((pList)->pNext == (pList)))
-#define DL_LIST_GET_ITEM_AT_HEAD(pList) (pList)->pNext
-#define DL_LIST_GET_ITEM_AT_TAIL(pList) (pList)->pPrev
-/*
- * ITERATE_OVER_LIST pStart is the list, pTemp is a temp list member
- * NOT: do not use this function if the items in the list are deleted inside the
- * iteration loop
- */
-#define ITERATE_OVER_LIST(pStart, pTemp) \
-	for((pTemp) =(pStart)->pNext; pTemp != (pStart); (pTemp) = (pTemp)->pNext)
-
-static __inline bool dl_list_is_entry_in_list(const DL_LIST *pList,
-					      const DL_LIST *pEntry)
-{
-	const DL_LIST *pTmp;
-
-	if (pList == pEntry)
-		return true;
-
-	ITERATE_OVER_LIST(pList, pTmp) {
-		if (pTmp == pEntry) {
-			return true;
-		}
-	}
-
-	return false;
-}
-
-/* safe iterate macro that allows the item to be removed from the list
- * the iteration continues to the next item in the list
- */
-#define ITERATE_OVER_LIST_ALLOW_REMOVE(pStart,pItem,st,offset)	\
-	{							\
-		PDL_LIST pTemp;					    \
-		pTemp = (pStart)->pNext;			    \
-		while (pTemp != (pStart)) {			    \
-			(pItem) = A_CONTAINING_STRUCT(pTemp,st,offset);	  \
-			pTemp = pTemp->pNext;			       \
-
-#define ITERATE_IS_VALID(pStart)    dl_list_is_entry_in_list(pStart, pTemp)
-#define ITERATE_RESET(pStart)       pTemp=(pStart)->pNext
-
-#define ITERATE_END }}
-
-/*
- * dl_list_insert_tail - insert pAdd to the end of the list
- */
-static __inline PDL_LIST dl_list_insert_tail(PDL_LIST pList, PDL_LIST pAdd)
-{
-	/* insert at tail */
-	pAdd->pPrev = pList->pPrev;
-	pAdd->pNext = pList;
-	if (pList->pPrev) {
-		pList->pPrev->pNext = pAdd;
-	}
-	pList->pPrev = pAdd;
-	return pAdd;
-}
-
-/*
- * dl_list_insert_head - insert pAdd into the head of the list
- */
-static __inline PDL_LIST dl_list_insert_head(PDL_LIST pList, PDL_LIST pAdd)
-{
-	/* insert at head */
-	pAdd->pPrev = pList;
-	pAdd->pNext = pList->pNext;
-	pList->pNext->pPrev = pAdd;
-	pList->pNext = pAdd;
-	return pAdd;
-}
-
-#define DL_ListAdd(pList,pItem) dl_list_insert_head((pList),(pItem))
-/*
- * dl_list_remove - remove pDel from list
- */
-static __inline PDL_LIST dl_list_remove(PDL_LIST pDel)
-{
-	if (pDel->pNext != NULL) {
-		pDel->pNext->pPrev = pDel->pPrev;
-	}
-	if (pDel->pPrev != NULL) {
-		pDel->pPrev->pNext = pDel->pNext;
-	}
-
-	/* point back to itself just to be safe, incase remove is called again */
-	pDel->pNext = pDel;
-	pDel->pPrev = pDel;
-	return pDel;
-}
-
-/*
- * dl_list_remove_item_from_head - get a list item from the head
- */
-static __inline PDL_LIST dl_list_remove_item_from_head(PDL_LIST pList)
-{
-	PDL_LIST pItem = NULL;
-	if (pList->pNext != pList) {
-		pItem = pList->pNext;
-		/* remove the first item from head */
-		dl_list_remove(pItem);
-	}
-	return pItem;
-}
-
-static __inline PDL_LIST dl_list_remove_item_from_tail(PDL_LIST pList)
-{
-	PDL_LIST pItem = NULL;
-	if (pList->pPrev != pList) {
-		pItem = pList->pPrev;
-		/* remove the item from tail */
-		dl_list_remove(pItem);
-	}
-	return pItem;
-}
-
-/* transfer src list items to the tail of the destination list */
-static __inline void dl_list_transfer_items_to_tail(PDL_LIST pDest, PDL_LIST pSrc)
-{
-	/* only concatenate if src is not empty */
-	if (!DL_LIST_IS_EMPTY(pSrc)) {
-		/* cut out circular list in src and re-attach to end of dest */
-		pSrc->pPrev->pNext = pDest;
-		pSrc->pNext->pPrev = pDest->pPrev;
-		pDest->pPrev->pNext = pSrc->pNext;
-		pDest->pPrev = pSrc->pPrev;
-		/* terminate src list, it is now empty */
-		pSrc->pPrev = pSrc;
-		pSrc->pNext = pSrc;
-	}
-}
-
-/* transfer src list items to the head of the destination list */
-static __inline void dl_list_transfer_items_to_head(PDL_LIST pDest, PDL_LIST pSrc)
-{
-	/* only concatenate if src is not empty */
-	if (!DL_LIST_IS_EMPTY(pSrc)) {
-		/* cut out circular list in src and re-attach to start of dest */
-		pSrc->pNext->pPrev = pDest;
-		pDest->pNext->pPrev = pSrc->pPrev;
-		pSrc->pPrev->pNext = pDest->pNext;
-		pDest->pNext = pSrc->pNext;
-		/* terminate src list, it is now empty */
-		pSrc->pPrev = pSrc;
-		pSrc->pNext = pSrc;
-	}
-}
-
-#endif /* __DL_LIST_H___ */

core/htc/htc.c

@@ -1,881 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include "ol_if_athvar.h"
-#include "htc_debug.h"
-#include "htc_internal.h"
-#include <cdf_nbuf.h>           /* cdf_nbuf_t */
-#include <cdf_types.h>          /* cdf_print */
-#include <hif.h>
-#include "epping_main.h"
-#include "hif_io32.h"
-#include "cds_concurrency.h"
-#include <cds_api.h>
-
-#ifdef DEBUG
-static ATH_DEBUG_MASK_DESCRIPTION g_htc_debug_description[] = {
-	{ATH_DEBUG_SEND, "Send"},
-	{ATH_DEBUG_RECV, "Recv"},
-	{ATH_DEBUG_SYNC, "Sync"},
-	{ATH_DEBUG_DUMP, "Dump Data (RX or TX)"},
-	{ATH_DEBUG_SETUP, "Setup"},
-};
-
-ATH_DEBUG_INSTANTIATE_MODULE_VAR(htc,
-				 "htc",
-				 "Host Target Communications",
-				 ATH_DEBUG_MASK_DEFAULTS | ATH_DEBUG_INFO |
-				 ATH_DEBUG_SETUP,
-				 ATH_DEBUG_DESCRIPTION_COUNT
-					 (g_htc_debug_description),
-				 g_htc_debug_description);
-
-#endif
-
-extern unsigned int htc_credit_flow;
-
-static void reset_endpoint_states(HTC_TARGET *target);
-
-static void destroy_htc_tx_ctrl_packet(HTC_PACKET *pPacket)
-{
-	cdf_nbuf_t netbuf;
-	netbuf = (cdf_nbuf_t) GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("free ctrl netbuf :0x%p \n", netbuf));
-	if (netbuf != NULL) {
-		cdf_nbuf_free(netbuf);
-	}
-
-	cdf_mem_free(pPacket);
-}
-
-static HTC_PACKET *build_htc_tx_ctrl_packet(cdf_device_t osdev)
-{
-	HTC_PACKET *pPacket = NULL;
-	cdf_nbuf_t netbuf;
-
-	do {
-		pPacket = (HTC_PACKET *) cdf_mem_malloc(sizeof(HTC_PACKET));
-		if (NULL == pPacket) {
-			break;
-		}
-		A_MEMZERO(pPacket, sizeof(HTC_PACKET));
-		netbuf =
-			cdf_nbuf_alloc(osdev, HTC_CONTROL_BUFFER_SIZE, 20, 4, true);
-		if (NULL == netbuf) {
-			cdf_mem_free(pPacket);
-			pPacket = NULL;
-			cdf_print("%s: nbuf alloc failed\n", __func__);
-			break;
-		}
-		AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
-				("alloc ctrl netbuf :0x%p \n", netbuf));
-		SET_HTC_PACKET_NET_BUF_CONTEXT(pPacket, netbuf);
-	} while (false);
-
-	return pPacket;
-}
-
-void htc_free_control_tx_packet(HTC_TARGET *target, HTC_PACKET *pPacket)
-{
-
-#ifdef TODO_FIXME
-	LOCK_HTC(target);
-	HTC_PACKET_ENQUEUE(&target->ControlBufferTXFreeList, pPacket);
-	UNLOCK_HTC(target);
-	/* TODO_FIXME netbufs cannot be RESET! */
-#else
-	destroy_htc_tx_ctrl_packet(pPacket);
-#endif
-
-}
-
-HTC_PACKET *htc_alloc_control_tx_packet(HTC_TARGET *target)
-{
-#ifdef TODO_FIXME
-	HTC_PACKET *pPacket;
-
-	LOCK_HTC(target);
-	pPacket = htc_packet_dequeue(&target->ControlBufferTXFreeList);
-	UNLOCK_HTC(target);
-
-	return pPacket;
-#else
-	return build_htc_tx_ctrl_packet(target->osdev);
-#endif
-}
-
-/* Set the target failure handling callback */
-void htc_set_target_failure_callback(HTC_HANDLE HTCHandle,
-				     HTC_TARGET_FAILURE Callback)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	target->HTCInitInfo.TargetFailure = Callback;
-}
-
-void htc_dump(HTC_HANDLE HTCHandle, uint8_t CmdId, bool start)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	hif_dump(target->hif_dev, CmdId, start);
-}
-
-/* cleanup the HTC instance */
-static void htc_cleanup(HTC_TARGET *target)
-{
-	HTC_PACKET *pPacket;
-	/* cdf_nbuf_t netbuf; */
-
-	if (target->hif_dev != NULL) {
-		hif_detach_htc(target->hif_dev);
-		target->hif_dev = NULL;
-	}
-
-	while (true) {
-		pPacket = allocate_htc_packet_container(target);
-		if (NULL == pPacket) {
-			break;
-		}
-		cdf_mem_free(pPacket);
-	}
-
-	pPacket = target->pBundleFreeList;
-	while (pPacket) {
-		HTC_PACKET *pPacketTmp = (HTC_PACKET *) pPacket->ListLink.pNext;
-		cdf_mem_free(pPacket);
-		pPacket = pPacketTmp;
-	}
-#ifdef TODO_FIXME
-	while (true) {
-		pPacket = htc_alloc_control_tx_packet(target);
-		if (NULL == pPacket) {
-			break;
-		}
-		netbuf = (cdf_nbuf_t) GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-		if (netbuf != NULL) {
-			cdf_nbuf_free(netbuf);
-		}
-
-		cdf_mem_free(pPacket);
-	}
-#endif
-
-	cdf_spinlock_destroy(&target->HTCLock);
-	cdf_spinlock_destroy(&target->HTCRxLock);
-	cdf_spinlock_destroy(&target->HTCTxLock);
-	cdf_spinlock_destroy(&target->HTCCreditLock);
-
-	/* free our instance */
-	cdf_mem_free(target);
-}
-
-/* registered target arrival callback from the HIF layer */
-HTC_HANDLE htc_create(void *ol_sc, HTC_INIT_INFO *pInfo, cdf_device_t osdev)
-{
-	struct hif_msg_callbacks htcCallbacks;
-	HTC_ENDPOINT *pEndpoint = NULL;
-	HTC_TARGET *target = NULL;
-	int i;
-
-	if (ol_sc == NULL) {
-		HTC_ERROR("%s: ol_sc = NULL", __func__);
-		return NULL;
-	}
-	HTC_TRACE("+htc_create ..  HIF :%p", ol_sc);
-
-	A_REGISTER_MODULE_DEBUG_INFO(htc);
-
-	target = (HTC_TARGET *) cdf_mem_malloc(sizeof(HTC_TARGET));
-	if (target == NULL) {
-		HTC_ERROR("%s: Unable to allocate memory", __func__);
-		return NULL;
-	}
-
-	A_MEMZERO(target, sizeof(HTC_TARGET));
-
-	htc_runtime_pm_init(target);
-	cdf_spinlock_init(&target->HTCLock);
-	cdf_spinlock_init(&target->HTCRxLock);
-	cdf_spinlock_init(&target->HTCTxLock);
-	cdf_spinlock_init(&target->HTCCreditLock);
-
-	do {
-		A_MEMCPY(&target->HTCInitInfo, pInfo, sizeof(HTC_INIT_INFO));
-		target->host_handle = pInfo->pContext;
-		target->osdev = osdev;
-
-		reset_endpoint_states(target);
-
-		INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
-
-		for (i = 0; i < HTC_PACKET_CONTAINER_ALLOCATION; i++) {
-			HTC_PACKET *pPacket =
-				(HTC_PACKET *) cdf_mem_malloc(sizeof(HTC_PACKET));
-			if (pPacket != NULL) {
-				A_MEMZERO(pPacket, sizeof(HTC_PACKET));
-				free_htc_packet_container(target, pPacket);
-			}
-		}
-
-#ifdef TODO_FIXME
-		for (i = 0; i < NUM_CONTROL_TX_BUFFERS; i++) {
-			pPacket = build_htc_tx_ctrl_packet();
-			if (NULL == pPacket) {
-				break;
-			}
-			htc_free_control_tx_packet(target, pPacket);
-		}
-#endif
-
-		/* setup HIF layer callbacks */
-		cdf_mem_zero(&htcCallbacks, sizeof(struct hif_msg_callbacks));
-		htcCallbacks.Context = target;
-		htcCallbacks.rxCompletionHandler = htc_rx_completion_handler;
-		htcCallbacks.txCompletionHandler = htc_tx_completion_handler;
-		htcCallbacks.txResourceAvailHandler = htc_tx_resource_avail_handler;
-		htcCallbacks.fwEventHandler = htc_fw_event_handler;
-		target->hif_dev = ol_sc;
-
-		/* Get HIF default pipe for HTC message exchange */
-		pEndpoint = &target->endpoint[ENDPOINT_0];
-
-		hif_post_init(target->hif_dev, target, &htcCallbacks);
-		hif_get_default_pipe(target->hif_dev, &pEndpoint->UL_PipeID,
-				     &pEndpoint->DL_PipeID);
-
-	} while (false);
-
-	htc_recv_init(target);
-
-	HTC_TRACE("-htc_create: (0x%p)", target);
-
-	return (HTC_HANDLE) target;
-}
-
-void htc_destroy(HTC_HANDLE HTCHandle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
-			("+htc_destroy ..  Destroying :0x%p\n", target));
-	hif_stop(htc_get_hif_device(HTCHandle));
-	if (target)
-		htc_cleanup(target);
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-htc_destroy\n"));
-}
-
-/* get the low level HIF device for the caller , the caller may wish to do low level
- * HIF requests */
-void *htc_get_hif_device(HTC_HANDLE HTCHandle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	return target->hif_dev;
-}
-
-void htc_control_tx_complete(void *Context, HTC_PACKET *pPacket)
-{
-	HTC_TARGET *target = (HTC_TARGET *) Context;
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
-			("+-htc_control_tx_complete 0x%p (l:%d) \n", pPacket,
-			 pPacket->ActualLength));
-	htc_free_control_tx_packet(target, pPacket);
-}
-
-/* TODO, this is just a temporary max packet size */
-#define MAX_MESSAGE_SIZE 1536
-
-/**
- * htc_setup_target_buffer_assignments() - setup target buffer assignments
- * @target: HTC Target Pointer
- *
- * Return: A_STATUS
- */
-A_STATUS htc_setup_target_buffer_assignments(HTC_TARGET *target)
-{
-	HTC_SERVICE_TX_CREDIT_ALLOCATION *pEntry;
-	A_STATUS status;
-	int credits;
-	int creditsPerMaxMsg;
-
-	creditsPerMaxMsg = MAX_MESSAGE_SIZE / target->TargetCreditSize;
-	if (MAX_MESSAGE_SIZE % target->TargetCreditSize) {
-		creditsPerMaxMsg++;
-	}
-
-	/* TODO, this should be configured by the caller! */
-
-	credits = target->TotalTransmitCredits;
-	pEntry = &target->ServiceTxAllocTable[0];
-
-	/*
-	 * Allocate all credists/HTC buffers to WMI.
-	 * no buffers are used/required for data. data always
-	 * remains on host.
-	 */
-	status = A_OK;
-	pEntry++;
-	pEntry->service_id = WMI_CONTROL_SVC;
-	pEntry->CreditAllocation = credits;
-
-	if (WLAN_IS_EPPING_ENABLED(cds_get_conparam())) {
-		/* endpoint ping is a testing tool directly on top of HTC in
-		 * both target and host sides.
-		 * In target side, the endppint ping fw has no wlan stack and the
-		 * FW mboxping app directly sits on HTC and it simply drops
-		 * or loops back TX packets. For rx perf, FW mboxping app
-		 * generates packets and passes packets to HTC to send to host.
-		 * There is no WMI mesage exchanges between host and target
-		 * in endpoint ping case.
-		 * In host side, the endpoint ping driver is a Ethernet driver
-		 * and it directly sits on HTC. Only HIF, HTC, CDF, ADF are
-		 * used by the endpoint ping driver. There is no wifi stack
-		 * at all in host side also. For tx perf use case,
-		 * the user space mboxping app sends the raw packets to endpoint
-		 * ping driver and it directly forwards to HTC for transmission
-		 * to stress the bus. For the rx perf, HTC passes the received
-		 * packets to endpoint ping driver and it is passed to the user
-		 * space through the Ethernet interface.
-		 * For credit allocation, in SDIO bus case, only BE service is
-		 * used for tx/rx perf testing so that all credits are given
-		 * to BE service. In PCIe and USB bus case, endpoint ping uses both
-		 * BE and BK services to stress the bus so that the total credits
-		 * are equally distributed to BE and BK services.
-		 */
-		pEntry->service_id = WMI_DATA_BE_SVC;
-		pEntry->CreditAllocation = (credits >> 1);
-
-		pEntry++;
-		pEntry->service_id = WMI_DATA_BK_SVC;
-		pEntry->CreditAllocation = (credits >> 1);
-	}
-
-	if (A_SUCCESS(status)) {
-		int i;
-		for (i = 0; i < HTC_MAX_SERVICE_ALLOC_ENTRIES; i++) {
-			if (target->ServiceTxAllocTable[i].service_id != 0) {
-				AR_DEBUG_PRINTF(ATH_DEBUG_INIT,
-						("HTC Service Index : %d TX : 0x%2.2X : alloc:%d\n",
-						 i,
-						 target->ServiceTxAllocTable[i].
-						 service_id,
-						 target->ServiceTxAllocTable[i].
-						 CreditAllocation));
-			}
-		}
-	}
-
-	return status;
-}
-
-A_UINT8 htc_get_credit_allocation(HTC_TARGET *target, A_UINT16 service_id)
-{
-	A_UINT8 allocation = 0;
-	int i;
-
-	for (i = 0; i < HTC_MAX_SERVICE_ALLOC_ENTRIES; i++) {
-		if (target->ServiceTxAllocTable[i].service_id == service_id) {
-			allocation =
-				target->ServiceTxAllocTable[i].CreditAllocation;
-		}
-	}
-
-	if (0 == allocation) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_INIT,
-			("HTC Service TX : 0x%2.2X : allocation is zero!\n",
-				 service_id));
-	}
-
-	return allocation;
-}
-
-A_STATUS htc_wait_target(HTC_HANDLE HTCHandle)
-{
-	A_STATUS status = A_OK;
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_READY_EX_MSG *pReadyMsg;
-	HTC_SERVICE_CONNECT_REQ connect;
-	HTC_SERVICE_CONNECT_RESP resp;
-	HTC_READY_MSG *rdy_msg;
-	A_UINT16 htc_rdy_msg_id;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
-			("htc_wait_target - Enter (target:0x%p) \n", HTCHandle));
-	AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("+HWT\n"));
-
-	do {
-
-		status = hif_start(target->hif_dev);
-		if (A_FAILED(status)) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("hif_start failed\n"));
-			break;
-		}
-
-		status = htc_wait_recv_ctrl_message(target);
-
-		if (A_FAILED(status)) {
-			break;
-		}
-
-		if (target->CtrlResponseLength < (sizeof(HTC_READY_EX_MSG))) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					("Invalid HTC Ready Msg Len:%d! \n",
-					 target->CtrlResponseLength));
-			status = A_ECOMM;
-			break;
-		}
-
-		pReadyMsg = (HTC_READY_EX_MSG *) target->CtrlResponseBuffer;
-
-		rdy_msg = &pReadyMsg->Version2_0_Info;
-		htc_rdy_msg_id =
-			HTC_GET_FIELD(rdy_msg, HTC_READY_MSG, MESSAGEID);
-		if (htc_rdy_msg_id != HTC_MSG_READY_ID) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					("Invalid HTC Ready Msg : 0x%X ! \n",
-					 htc_rdy_msg_id));
-			status = A_ECOMM;
-			break;
-		}
-
-		target->TotalTransmitCredits =
-			HTC_GET_FIELD(rdy_msg, HTC_READY_MSG, CREDITCOUNT);
-		target->TargetCreditSize =
-			(int)HTC_GET_FIELD(rdy_msg, HTC_READY_MSG, CREDITSIZE);
-		target->MaxMsgsPerHTCBundle =
-			(A_UINT8) pReadyMsg->MaxMsgsPerHTCBundle;
-		/* for old fw this value is set to 0. But the minimum value should be 1,
-		 * i.e., no bundling */
-		if (target->MaxMsgsPerHTCBundle < 1)
-			target->MaxMsgsPerHTCBundle = 1;
-
-		AR_DEBUG_PRINTF(ATH_DEBUG_INIT,
-				("Target Ready! : transmit resources : %d size:%d, MaxMsgsPerHTCBundle = %d\n",
-				 target->TotalTransmitCredits,
-				 target->TargetCreditSize,
-				 target->MaxMsgsPerHTCBundle));
-
-		if ((0 == target->TotalTransmitCredits)
-		    || (0 == target->TargetCreditSize)) {
-			status = A_ECOMM;
-			break;
-		}
-		/* done processing */
-		target->CtrlResponseProcessing = false;
-
-		htc_setup_target_buffer_assignments(target);
-
-		/* setup our pseudo HTC control endpoint connection */
-		A_MEMZERO(&connect, sizeof(connect));
-		A_MEMZERO(&resp, sizeof(resp));
-		connect.EpCallbacks.pContext = target;
-		connect.EpCallbacks.EpTxComplete = htc_control_tx_complete;
-		connect.EpCallbacks.EpRecv = htc_control_rx_complete;
-		connect.MaxSendQueueDepth = NUM_CONTROL_TX_BUFFERS;
-		connect.service_id = HTC_CTRL_RSVD_SVC;
-
-		/* connect fake service */
-		status = htc_connect_service((HTC_HANDLE) target,
-					     &connect, &resp);
-
-	} while (false);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htc_wait_target - Exit (%d)\n", status));
-	AR_DEBUG_PRINTF(ATH_DEBUG_ANY, ("-HWT\n"));
-	return status;
-}
-
-/* start HTC, this is called after all services are connected */
-static A_STATUS htc_config_target_hif_pipe(HTC_TARGET *target)
-{
-
-	return A_OK;
-}
-
-static void reset_endpoint_states(HTC_TARGET *target)
-{
-	HTC_ENDPOINT *pEndpoint;
-	int i;
-
-	for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
-		pEndpoint = &target->endpoint[i];
-		pEndpoint->service_id = 0;
-		pEndpoint->MaxMsgLength = 0;
-		pEndpoint->MaxTxQueueDepth = 0;
-		pEndpoint->Id = i;
-		INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
-		INIT_HTC_PACKET_QUEUE(&pEndpoint->TxLookupQueue);
-		INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBufferHoldQueue);
-		pEndpoint->target = target;
-		/* pEndpoint->TxCreditFlowEnabled = (A_BOOL)htc_credit_flow; */
-		pEndpoint->TxCreditFlowEnabled = (A_BOOL) 1;
-		cdf_atomic_init(&pEndpoint->TxProcessCount);
-	}
-}
-
-A_STATUS htc_start(HTC_HANDLE HTCHandle)
-{
-	cdf_nbuf_t netbuf;
-	A_STATUS status = A_OK;
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_SETUP_COMPLETE_EX_MSG *pSetupComp;
-	HTC_PACKET *pSendPacket;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htc_start Enter\n"));
-
-	do {
-
-		htc_config_target_hif_pipe(target);
-
-		/* allocate a buffer to send */
-		pSendPacket = htc_alloc_control_tx_packet(target);
-		if (NULL == pSendPacket) {
-			AR_DEBUG_ASSERT(false);
-			cdf_print("%s: allocControlTxPacket failed\n",
-				  __func__);
-			status = A_NO_MEMORY;
-			break;
-		}
-
-		netbuf =
-			(cdf_nbuf_t) GET_HTC_PACKET_NET_BUF_CONTEXT(pSendPacket);
-		/* assemble setup complete message */
-		cdf_nbuf_put_tail(netbuf, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
-		pSetupComp =
-			(HTC_SETUP_COMPLETE_EX_MSG *) cdf_nbuf_data(netbuf);
-		A_MEMZERO(pSetupComp, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
-
-		HTC_SET_FIELD(pSetupComp, HTC_SETUP_COMPLETE_EX_MSG,
-			      MESSAGEID, HTC_MSG_SETUP_COMPLETE_EX_ID);
-
-		if (!htc_credit_flow) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_INIT,
-					("HTC will not use TX credit flow control\n"));
-			pSetupComp->SetupFlags |=
-				HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW;
-		} else {
-			AR_DEBUG_PRINTF(ATH_DEBUG_INIT,
-					("HTC using TX credit flow control\n"));
-		}
-
-#ifdef HIF_SDIO
-#if ENABLE_BUNDLE_RX
-		if (HTC_ENABLE_BUNDLE(target))
-			pSetupComp->SetupFlags |=
-				HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV;
-#endif /* ENABLE_BUNDLE_RX */
-#endif /* HIF_SDIO */
-
-		SET_HTC_PACKET_INFO_TX(pSendPacket,
-				       NULL,
-				       (A_UINT8 *) pSetupComp,
-				       sizeof(HTC_SETUP_COMPLETE_EX_MSG),
-				       ENDPOINT_0, HTC_SERVICE_TX_PACKET_TAG);
-
-		status = htc_send_pkt((HTC_HANDLE) target, pSendPacket);
-		if (A_FAILED(status)) {
-			break;
-		}
-
-	} while (false);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("htc_start Exit\n"));
-	return status;
-}
-
-/*flush all queued buffers for surpriseremove case*/
-void htc_flush_surprise_remove(HTC_HANDLE HTCHandle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	int i;
-	HTC_ENDPOINT *pEndpoint;
-#ifdef RX_SG_SUPPORT
-	cdf_nbuf_t netbuf;
-	cdf_nbuf_queue_t *rx_sg_queue = &target->RxSgQueue;
-#endif
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+htc_flush_surprise_remove \n"));
-
-	/* cleanup endpoints */
-	for (i = 0; i < ENDPOINT_MAX; i++) {
-		pEndpoint = &target->endpoint[i];
-		htc_flush_rx_hold_queue(target, pEndpoint);
-		htc_flush_endpoint_tx(target, pEndpoint, HTC_TX_PACKET_TAG_ALL);
-	}
-
-	hif_flush_surprise_remove(target->hif_dev);
-
-#ifdef RX_SG_SUPPORT
-	LOCK_HTC_RX(target);
-	while ((netbuf = cdf_nbuf_queue_remove(rx_sg_queue)) != NULL) {
-		cdf_nbuf_free(netbuf);
-	}
-	RESET_RX_SG_CONFIG(target);
-	UNLOCK_HTC_RX(target);
-#endif
-
-	reset_endpoint_states(target);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-htc_flush_surprise_remove \n"));
-}
-
-/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
-void htc_stop(HTC_HANDLE HTCHandle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	int i;
-	HTC_ENDPOINT *pEndpoint;
-#ifdef RX_SG_SUPPORT
-	cdf_nbuf_t netbuf;
-	cdf_nbuf_queue_t *rx_sg_queue = &target->RxSgQueue;
-#endif
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+htc_stop \n"));
-
-	/* cleanup endpoints */
-	for (i = 0; i < ENDPOINT_MAX; i++) {
-		pEndpoint = &target->endpoint[i];
-		htc_flush_rx_hold_queue(target, pEndpoint);
-		htc_flush_endpoint_tx(target, pEndpoint, HTC_TX_PACKET_TAG_ALL);
-		if (pEndpoint->ul_is_polled) {
-			cdf_softirq_timer_cancel(&pEndpoint->ul_poll_timer);
-			cdf_softirq_timer_free(&pEndpoint->ul_poll_timer);
-		}
-	}
-
-	/* Note: htc_flush_endpoint_tx for all endpoints should be called before
-	 * hif_stop - otherwise htc_tx_completion_handler called from
-	 * hif_send_buffer_cleanup_on_pipe for residual tx frames in HIF layer,
-	 * might queue the packet again to HIF Layer - which could cause tx
-	 * buffer leak
-	 */
-
-	hif_stop(target->hif_dev);
-
-#ifdef RX_SG_SUPPORT
-	LOCK_HTC_RX(target);
-	while ((netbuf = cdf_nbuf_queue_remove(rx_sg_queue)) != NULL) {
-		cdf_nbuf_free(netbuf);
-	}
-	RESET_RX_SG_CONFIG(target);
-	UNLOCK_HTC_RX(target);
-#endif
-
-	reset_endpoint_states(target);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-htc_stop\n"));
-}
-
-/**
- * htc_runtime_pm_init(): runtime pm related intialization
- *
- * need to initialize a work item.
- */
-void htc_runtime_pm_init(HTC_TARGET *target)
-{
-	cdf_create_work(&target->queue_kicker, htc_kick_queues, target);
-}
-
-/**
- * htc_runtime_suspend(): ensure htc is ready to suspend
- *
- * htc is ready to suspend if there are no pending pactets
- * in the txrx queues.
- *
- * Return: 0 on success or -EBUSY if there are queued packets.
- */
-int htc_runtime_suspend(void)
-{
-	ol_txrx_pdev_handle txrx_pdev = cds_get_context(CDF_MODULE_ID_TXRX);
-
-	if (txrx_pdev == NULL) {
-		HTC_ERROR("%s: txrx context null", __func__);
-		return CDF_STATUS_E_FAULT;
-	}
-
-	if (ol_txrx_get_tx_pending(txrx_pdev))
-		return -EBUSY;
-	else
-		return 0;
-}
-
-/**
- * htc_runtime_resume(): resume htc
- *
- * The htc message queue needs to be kicked off after
- * a runtime resume.  Otherwise messages would get stuck.
- *
- * Return: 0 for success;
- */
-int htc_runtime_resume(void)
-{
-	HTC_HANDLE htc_ctx = cds_get_context(CDF_MODULE_ID_HTC);
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(htc_ctx);
-
-	if (target == NULL)
-		return 0;
-
-	cdf_schedule_work(&target->queue_kicker);
-	return 0;
-}
-
-void htc_dump_credit_states(HTC_HANDLE HTCHandle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint;
-	int i;
-
-	for (i = 0; i < ENDPOINT_MAX; i++) {
-		pEndpoint = &target->endpoint[i];
-		if (0 == pEndpoint->service_id)
-			continue;
-
-		AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
-			("--- EP : %d  service_id: 0x%X    --------------\n",
-				 pEndpoint->Id, pEndpoint->service_id));
-		AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
-				(" TxCredits          : %d\n",
-				 pEndpoint->TxCredits));
-		AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
-				(" TxCreditSize       : %d\n",
-				 pEndpoint->TxCreditSize));
-		AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
-				(" TxCreditsPerMaxMsg : %d\n",
-				 pEndpoint->TxCreditsPerMaxMsg));
-		AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
-				(" TxQueueDepth       : %d\n",
-				 HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)));
-		AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
-				("----------------------------------------------------\n"));
-	}
-}
-
-A_BOOL htc_get_endpoint_statistics(HTC_HANDLE HTCHandle,
-				   HTC_ENDPOINT_ID Endpoint,
-				   HTC_ENDPOINT_STAT_ACTION Action,
-				   HTC_ENDPOINT_STATS *pStats)
-{
-#ifdef HTC_EP_STAT_PROFILING
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	A_BOOL clearStats = false;
-	A_BOOL sample = false;
-
-	switch (Action) {
-	case HTC_EP_STAT_SAMPLE:
-		sample = true;
-		break;
-	case HTC_EP_STAT_SAMPLE_AND_CLEAR:
-		sample = true;
-		clearStats = true;
-		break;
-	case HTC_EP_STAT_CLEAR:
-		clearStats = true;
-		break;
-	default:
-		break;
-	}
-
-	A_ASSERT(Endpoint < ENDPOINT_MAX);
-
-	/* lock out TX and RX while we sample and/or clear */
-	LOCK_HTC_TX(target);
-	LOCK_HTC_RX(target);
-
-	if (sample) {
-		A_ASSERT(pStats != NULL);
-		/* return the stats to the caller */
-		A_MEMCPY(pStats, &target->endpoint[Endpoint].endpoint_stats,
-			 sizeof(HTC_ENDPOINT_STATS));
-	}
-
-	if (clearStats) {
-		/* reset stats */
-		A_MEMZERO(&target->endpoint[Endpoint].endpoint_stats,
-			  sizeof(HTC_ENDPOINT_STATS));
-	}
-
-	UNLOCK_HTC_RX(target);
-	UNLOCK_HTC_TX(target);
-
-	return true;
-#else
-	return false;
-#endif
-}
-
-void *htc_get_targetdef(HTC_HANDLE htc_handle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(htc_handle);
-
-	return hif_get_targetdef(target->hif_dev);
-}
-
-/**
- * htc_set_target_to_sleep() - set target to sleep
- * @context: ol_softc context
- *
- * Return: none
- */
-void htc_set_target_to_sleep(void *context)
-{
-	struct ol_softc *scn = (struct ol_softc *)context;
-
-	hif_set_target_sleep(scn, true, false);
-}
-
-/**
- * htc_cancel_deferred_target_sleep() - cancel deferred target sleep
- * @context: ol_softc context
- *
- * Return: none
- */
-void htc_cancel_deferred_target_sleep(void *context)
-{
-	struct ol_softc *scn = (struct ol_softc *)context;
-	hif_cancel_deferred_target_sleep(scn);
-}
-
-#ifdef IPA_OFFLOAD
-/**
- * htc_ipa_get_ce_resource() - get uc resource on lower layer
- * @htc_handle: htc context
- * @ce_sr_base_paddr: copyengine source ring base physical address
- * @ce_sr_ring_size: copyengine source ring size
- * @ce_reg_paddr: copyengine register physical address
- *
- * Return: None
- */
-void htc_ipa_get_ce_resource(HTC_HANDLE htc_handle,
-			     cdf_dma_addr_t *ce_sr_base_paddr,
-			     uint32_t *ce_sr_ring_size,
-			     cdf_dma_addr_t *ce_reg_paddr)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(htc_handle);
-
-	if (target->hif_dev != NULL) {
-		hif_ipa_get_ce_resource(target->hif_dev,
-					ce_sr_base_paddr,
-					ce_sr_ring_size, ce_reg_paddr);
-	}
-}
-#endif /* IPA_OFFLOAD */

core/htc/htc_api.h

@@ -1,718 +0,0 @@
-/*
- * Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _HTC_API_H_
-#define _HTC_API_H_
-
-#include <athdefs.h>
-#include "osapi_linux.h"
-#include "htc_packet.h"
-#include <htc.h>
-#include <htc_services.h>
-#include <cdf_types.h>          /* cdf_device_t */
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* TODO.. for BMI */
-#define ENDPOINT1 0
-/* TODO -remove me, but we have to fix BMI first */
-#define HTC_MAILBOX_NUM_MAX    4
-
-/* this is the amount of header room required by users of HTC */
-#define HTC_HEADER_LEN         HTC_HDR_LENGTH
-
-typedef void *HTC_HANDLE;
-
-typedef A_UINT16 HTC_SERVICE_ID;
-
-typedef void (*HTC_TARGET_FAILURE)(void *Instance, CDF_STATUS Status);
-
-typedef struct _HTC_INIT_INFO {
-	void *pContext;         /* context for target notifications */
-	void (*TargetFailure)(void *Instance, CDF_STATUS Status);
-	void (*TargetSendSuspendComplete)(void *ctx);
-} HTC_INIT_INFO;
-
-/* Struct for HTC layer packet stats*/
-struct ol_ath_htc_stats {
-	int htc_get_pkt_q_fail_count;
-	int htc_pkt_q_empty_count;
-	int htc_send_q_empty_count;
-};
-
-/* To resume HTT Tx queue during runtime resume */
-typedef void (*HTC_EP_RESUME_TX_QUEUE)(void *);
-
-/* per service connection send completion */
-typedef void (*HTC_EP_SEND_PKT_COMPLETE)(void *, HTC_PACKET *);
-/* per service connection callback when a plurality of packets have been sent
- * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
- * to hold a list of completed send packets.
- * If the handler cannot fully traverse the packet queue before returning, it should
- * transfer the items of the queue into the caller's private queue using:
- *   HTC_PACKET_ENQUEUE() */
-typedef void (*HTC_EP_SEND_PKT_COMP_MULTIPLE)(void *,
-					      HTC_PACKET_QUEUE *);
-/* per service connection pkt received */
-typedef void (*HTC_EP_RECV_PKT)(void *, HTC_PACKET *);
-/* per service connection callback when a plurality of packets are received
- * The HTC_PACKET_QUEUE is a temporary queue object (e.g. freed on return from the callback)
- * to hold a list of recv packets.
- * If the handler cannot fully traverse the packet queue before returning, it should
- * transfer the items of the queue into the caller's private queue using:
- *   HTC_PACKET_ENQUEUE() */
-typedef void (*HTC_EP_RECV_PKT_MULTIPLE)(void *, HTC_PACKET_QUEUE *);
-
-/* Optional per service connection receive buffer re-fill callback,
- * On some OSes (like Linux) packets are allocated from a global pool and indicated up
- * to the network stack.  The driver never gets the packets back from the OS.  For these OSes
- * a refill callback can be used to allocate and re-queue buffers into HTC.
- *
- * On other OSes, the network stack can call into the driver's OS-specifc "return_packet" handler and
- * the driver can re-queue these buffers into HTC. In this regard a refill callback is
- * unnecessary */
-typedef void (*HTC_EP_RECV_REFILL)(void *, HTC_ENDPOINT_ID Endpoint);
-
-/* Optional per service connection receive buffer allocation callback.
- * On some systems packet buffers are an extremely limited resource.  Rather than
- * queue largest-possible-sized buffers to HTC, some systems would rather
- * allocate a specific size as the packet is received.  The trade off is
- * slightly more processing (callback invoked for each RX packet)
- * for the benefit of committing fewer buffer resources into HTC.
- *
- * The callback is provided the length of the pending packet to fetch. This includes the
- * HTC header length plus the length of payload.  The callback can return a pointer to
- * the allocated HTC packet for immediate use.
- *
- * Alternatively a variant of this handler can be used to allocate large receive packets as needed.
- * For example an application can use the refill mechanism for normal packets and the recv-alloc mechanism to
- * handle the case where a large packet buffer is required.  This can significantly reduce the
- * amount of "committed" memory used to receive packets.
- *
- * */
-typedef HTC_PACKET *(*HTC_EP_RECV_ALLOC)(void *,
-					 HTC_ENDPOINT_ID Endpoint,
-					 int Length);
-
-typedef enum _HTC_SEND_FULL_ACTION {
-	HTC_SEND_FULL_KEEP = 0,         /* packet that overflowed should be kept in the queue */
-	HTC_SEND_FULL_DROP = 1,         /* packet that overflowed should be dropped */
-} HTC_SEND_FULL_ACTION;
-
-/* Optional per service connection callback when a send queue is full. This can occur if the
- * host continues queueing up TX packets faster than credits can arrive
- * To prevent the host (on some Oses like Linux) from continuously queueing packets
- * and consuming resources, this callback is provided so that that the host
- * can disable TX in the subsystem (i.e. network stack).
- * This callback is invoked for each packet that "overflows" the HTC queue. The callback can
- * determine whether the new packet that overflowed the queue can be kept (HTC_SEND_FULL_KEEP) or
- * dropped (HTC_SEND_FULL_DROP).  If a packet is dropped, the EpTxComplete handler will be called
- * and the packet's status field will be set to A_NO_RESOURCE.
- * Other OSes require a "per-packet" indication for each completed TX packet, this
- * closed loop mechanism will prevent the network stack from overunning the NIC
- * The packet to keep or drop is passed for inspection to the registered handler the handler
- * must ONLY inspect the packet, it may not free or reclaim the packet. */
-typedef HTC_SEND_FULL_ACTION (*HTC_EP_SEND_QUEUE_FULL)(void *,
-						       HTC_PACKET *
-						       pPacket);
-
-typedef struct _HTC_EP_CALLBACKS {
-	void *pContext;         /* context for each callback */
-	HTC_EP_SEND_PKT_COMPLETE EpTxComplete;          /* tx completion callback for connected endpoint */
-	HTC_EP_RECV_PKT EpRecv;         /* receive callback for connected endpoint */
-	HTC_EP_RECV_REFILL EpRecvRefill;                /* OPTIONAL receive re-fill callback for connected endpoint */
-	HTC_EP_SEND_QUEUE_FULL EpSendFull;              /* OPTIONAL send full callback */
-	HTC_EP_RECV_ALLOC EpRecvAlloc;          /* OPTIONAL recv allocation callback */
-	HTC_EP_RECV_ALLOC EpRecvAllocThresh;            /* OPTIONAL recv allocation callback based on a threshold */
-	HTC_EP_SEND_PKT_COMP_MULTIPLE EpTxCompleteMultiple;             /* OPTIONAL completion handler for multiple complete
-	                                                                   indications (EpTxComplete must be NULL) */
-	HTC_EP_RECV_PKT_MULTIPLE EpRecvPktMultiple;             /* OPTIONAL completion handler for multiple
-	                                                           recv packet indications (EpRecv must be NULL) */
-	HTC_EP_RESUME_TX_QUEUE ep_resume_tx_queue;
-	int RecvAllocThreshold;         /* if EpRecvAllocThresh is non-NULL, HTC will compare the
-	                                   threshold value to the current recv packet length and invoke
-	                                   the EpRecvAllocThresh callback to acquire a packet buffer */
-	int RecvRefillWaterMark;                /* if a EpRecvRefill handler is provided, this value
-	                                           can be used to set a trigger refill callback
-	                                           when the recv queue drops below this value
-	                                           if set to 0, the refill is only called when packets
-	                                           are empty */
-} HTC_EP_CALLBACKS;
-
-/* service connection information */
-typedef struct _HTC_SERVICE_CONNECT_REQ {
-	HTC_SERVICE_ID service_id;               /* service ID to connect to */
-	A_UINT16 ConnectionFlags;               /* connection flags, see htc protocol definition */
-	A_UINT8 *pMetaData;             /* ptr to optional service-specific meta-data */
-	A_UINT8 MetaDataLength;         /* optional meta data length */
-	HTC_EP_CALLBACKS EpCallbacks;           /* endpoint callbacks */
-	int MaxSendQueueDepth;          /* maximum depth of any send queue */
-	A_UINT32 LocalConnectionFlags;          /* HTC flags for the host-side (local) connection */
-	unsigned int MaxSendMsgSize;            /* override max message size in send direction */
-} HTC_SERVICE_CONNECT_REQ;
-
-#define HTC_LOCAL_CONN_FLAGS_ENABLE_SEND_BUNDLE_PADDING (1 << 0)        /* enable send bundle padding for this endpoint */
-
-/* service connection response information */
-typedef struct _HTC_SERVICE_CONNECT_RESP {
-	A_UINT8 *pMetaData;             /* caller supplied buffer to optional meta-data */
-	A_UINT8 BufferLength;           /* length of caller supplied buffer */
-	A_UINT8 ActualLength;           /* actual length of meta data */
-	HTC_ENDPOINT_ID Endpoint;               /* endpoint to communicate over */
-	unsigned int MaxMsgLength;              /* max length of all messages over this endpoint */
-	A_UINT8 ConnectRespCode;                /* connect response code from target */
-} HTC_SERVICE_CONNECT_RESP;
-
-/* endpoint distribution structure */
-typedef struct _HTC_ENDPOINT_CREDIT_DIST {
-	struct _HTC_ENDPOINT_CREDIT_DIST *pNext;
-	struct _HTC_ENDPOINT_CREDIT_DIST *pPrev;
-	HTC_SERVICE_ID service_id;               /* Service ID (set by HTC) */
-	HTC_ENDPOINT_ID Endpoint;               /* endpoint for this distribution struct (set by HTC) */
-	A_UINT32 DistFlags;             /* distribution flags, distribution function can
-	                                   set default activity using SET_EP_ACTIVE() macro */
-	int TxCreditsNorm;              /* credits for normal operation, anything above this
-	                                   indicates the endpoint is over-subscribed, this field
-	                                   is only relevant to the credit distribution function */
-	int TxCreditsMin;               /* floor for credit distribution, this field is
-	                                   only relevant to the credit distribution function */
-	int TxCreditsAssigned;          /* number of credits assigned to this EP, this field
-	                                   is only relevant to the credit dist function */
-	int TxCredits;          /* current credits available, this field is used by
-	                           HTC to determine whether a message can be sent or
-	                           must be queued */
-	int TxCreditsToDist;            /* pending credits to distribute on this endpoint, this
-	                                   is set by HTC when credit reports arrive.
-	                                   The credit distribution functions sets this to zero
-	                                   when it distributes the credits */
-	int TxCreditsSeek;              /* this is the number of credits that the current pending TX
-	                                   packet needs to transmit.  This is set by HTC when
-	                                   and endpoint needs credits in order to transmit */
-	int TxCreditSize;               /* size in bytes of each credit (set by HTC) */
-	int TxCreditsPerMaxMsg;         /* credits required for a maximum sized messages (set by HTC) */
-	void *pHTCReserved;             /* reserved for HTC use */
-	int TxQueueDepth;               /* current depth of TX queue , i.e. messages waiting for credits
-	                                   This field is valid only when HTC_CREDIT_DIST_ACTIVITY_CHANGE
-	                                   or HTC_CREDIT_DIST_SEND_COMPLETE is indicated on an endpoint
-	                                   that has non-zero credits to recover
-	                                 */
-} HTC_ENDPOINT_CREDIT_DIST;
-
-#define HTC_EP_ACTIVE                            ((A_UINT32) (1u << 31))
-
-/* macro to check if an endpoint has gone active, useful for credit
- * distributions */
-#define IS_EP_ACTIVE(epDist)  ((epDist)->DistFlags & HTC_EP_ACTIVE)
-#define SET_EP_ACTIVE(epDist) (epDist)->DistFlags |= HTC_EP_ACTIVE
-
-/* credit distibution code that is passed into the distrbution function,
- * there are mandatory and optional codes that must be handled */
-typedef enum _HTC_CREDIT_DIST_REASON {
-	HTC_CREDIT_DIST_SEND_COMPLETE = 0,              /* credits available as a result of completed
-	                                                   send operations (MANDATORY) resulting in credit reports */
-	HTC_CREDIT_DIST_ACTIVITY_CHANGE = 1,            /* a change in endpoint activity occured (OPTIONAL) */
-	HTC_CREDIT_DIST_SEEK_CREDITS,           /* an endpoint needs to "seek" credits (OPTIONAL) */
-	HTC_DUMP_CREDIT_STATE           /* for debugging, dump any state information that is kept by
-	                                   the distribution function */
-} HTC_CREDIT_DIST_REASON;
-
-typedef void (*HTC_CREDIT_DIST_CALLBACK)(void *Context,
-					 HTC_ENDPOINT_CREDIT_DIST *
-					 pEPList,
-					 HTC_CREDIT_DIST_REASON
-					 Reason);
-
-typedef void (*HTC_CREDIT_INIT_CALLBACK)(void *Context,
-					 HTC_ENDPOINT_CREDIT_DIST *
-					 pEPList, int TotalCredits);
-
-/* endpoint statistics action */
-typedef enum _HTC_ENDPOINT_STAT_ACTION {
-	HTC_EP_STAT_SAMPLE = 0,         /* only read statistics */
-	HTC_EP_STAT_SAMPLE_AND_CLEAR = 1,               /* sample and immediately clear statistics */
-	HTC_EP_STAT_CLEAR               /* clear only */
-} HTC_ENDPOINT_STAT_ACTION;
-
-/* endpoint statistics */
-typedef struct _HTC_ENDPOINT_STATS {
-	A_UINT32 TxPosted;              /* number of TX packets posted to the endpoint */
-	A_UINT32 TxCreditLowIndications;                /* number of times the host set the credit-low flag in a send message on
-	                                                   this endpoint */
-	A_UINT32 TxIssued;              /* running count of total TX packets issued */
-	A_UINT32 TxPacketsBundled;              /* running count of TX packets that were issued in bundles */
-	A_UINT32 TxBundles;             /* running count of TX bundles that were issued */
-	A_UINT32 TxDropped;             /* tx packets that were dropped */
-	A_UINT32 TxCreditRpts;          /* running count of total credit reports received for this endpoint */
-	A_UINT32 TxCreditRptsFromRx;            /* credit reports received from this endpoint's RX packets */
-	A_UINT32 TxCreditRptsFromOther;         /* credit reports received from RX packets of other endpoints */
-	A_UINT32 TxCreditRptsFromEp0;           /* credit reports received from endpoint 0 RX packets */
-	A_UINT32 TxCreditsFromRx;               /* count of credits received via Rx packets on this endpoint */
-	A_UINT32 TxCreditsFromOther;            /* count of credits received via another endpoint */
-	A_UINT32 TxCreditsFromEp0;              /* count of credits received via another endpoint */
-	A_UINT32 TxCreditsConsummed;            /* count of consummed credits */
-	A_UINT32 TxCreditsReturned;             /* count of credits returned */
-	A_UINT32 RxReceived;            /* count of RX packets received */
-	A_UINT32 RxLookAheads;          /* count of lookahead records
-	                                   found in messages received on this endpoint */
-	A_UINT32 RxPacketsBundled;              /* count of recv packets received in a bundle */
-	A_UINT32 RxBundleLookAheads;            /* count of number of bundled lookaheads */
-	A_UINT32 RxBundleIndFromHdr;            /* count of the number of bundle indications from the HTC header */
-	A_UINT32 RxAllocThreshHit;              /* count of the number of times the recv allocation threshhold was hit */
-	A_UINT32 RxAllocThreshBytes;            /* total number of bytes */
-} HTC_ENDPOINT_STATS;
-
-/* ------ Function Prototypes ------ */
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Create an instance of HTC over the underlying HIF device
-   @function name: htc_create
-   @input:  HifDevice - hif device handle,
-           pInfo - initialization information
-   @output:
-   @return: HTC_HANDLE on success, NULL on failure
-   @notes:
-   @example:
-   @see also: htc_destroy
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-HTC_HANDLE htc_create(void *HifDevice,
-		      HTC_INIT_INFO *pInfo, cdf_device_t osdev);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Get the underlying HIF device handle
-   @function name: htc_get_hif_device
-   @input:  HTCHandle - handle passed into the AddInstance callback
-   @output:
-   @return: opaque HIF device handle usable in HIF API calls.
-   @notes:
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void *htc_get_hif_device(HTC_HANDLE HTCHandle);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Set credit distribution parameters
-   @function name: htc_set_credit_distribution
-   @input:  HTCHandle - HTC handle
-           pCreditDistCont - caller supplied context to pass into distribution functions
-           CreditDistFunc - Distribution function callback
-           CreditDistInit - Credit Distribution initialization callback
-           ServicePriorityOrder - Array containing list of service IDs, lowest index is highest
-                                  priority
-           ListLength - number of elements in ServicePriorityOrder
-   @output:
-   @return:
-   @notes:  The user can set a custom credit distribution function to handle special requirements
-           for each endpoint.  A default credit distribution routine can be used by setting
-           CreditInitFunc to NULL.  The default credit distribution is only provided for simple
-           "fair" credit distribution without regard to any prioritization.
-
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_set_credit_distribution(HTC_HANDLE HTCHandle,
-				 void *pCreditDistContext,
-				 HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
-				 HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
-				 HTC_SERVICE_ID ServicePriorityOrder[],
-				 int ListLength);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Wait for the target to indicate the HTC layer is ready
-   @function name: htc_wait_target
-   @input:  HTCHandle - HTC handle
-   @output:
-   @return:
-   @notes:  This API blocks until the target responds with an HTC ready message.
-           The caller should not connect services until the target has indicated it is
-           ready.
-   @example:
-   @see also: htc_connect_service
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_STATUS htc_wait_target(HTC_HANDLE HTCHandle);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Start target service communications
-   @function name: htc_start
-   @input:  HTCHandle - HTC handle
-   @output:
-   @return:
-   @notes: This API indicates to the target that the service connection phase is complete
-          and the target can freely start all connected services.  This API should only be
-          called AFTER all service connections have been made.  TCStart will issue a
-          SETUP_COMPLETE message to the target to indicate that all service connections
-          have been made and the target can start communicating over the endpoints.
-   @example:
-   @see also: htc_connect_service
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_STATUS htc_start(HTC_HANDLE HTCHandle);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Add receive packet to HTC
-   @function name: htc_add_receive_pkt
-   @input:  HTCHandle - HTC handle
-           pPacket - HTC receive packet to add
-   @output:
-   @return: A_OK on success
-   @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
-           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
-           macro.
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_STATUS htc_add_receive_pkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Connect to an HTC service
-   @function name: htc_connect_service
-   @input:  HTCHandle - HTC handle
-           pReq - connection details
-   @output: pResp - connection response
-   @return:
-   @notes:  Service connections must be performed before htc_start.  User provides callback handlers
-           for various endpoint events.
-   @example:
-   @see also: htc_start
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_STATUS htc_connect_service(HTC_HANDLE HTCHandle,
-			     HTC_SERVICE_CONNECT_REQ *pReq,
-			     HTC_SERVICE_CONNECT_RESP *pResp);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: HTC register log dump
-   @function name: htc_dump
-   @input:  HTCHandle - HTC handle
-           CmdId - Log command
-           start - start/print logs
-   @output:
-   @return:
-   @notes: Register logs will be started/printed.
-   be flushed.
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-
-void htc_dump(HTC_HANDLE HTCHandle, uint8_t CmdId, bool start);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Send an HTC packet
-   @function name: htc_send_pkt
-   @input:  HTCHandle - HTC handle
-           pPacket - packet to send
-   @output:
-   @return: A_OK
-   @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
-           This interface is fully asynchronous.  On error, HTC SendPkt will
-           call the registered Endpoint callback to cleanup the packet.
-   @example:
-   @see also: htc_flush_endpoint
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_STATUS htc_send_pkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Send an HTC packet containing a tx descriptor and data
-   @function name: htc_send_data_pkt
-   @input:  HTCHandle - HTC handle
-           pPacket - packet to send
-   @output:
-   @return: A_OK
-   @notes:  Caller must initialize packet using SET_HTC_PACKET_INFO_TX() macro.
-           Caller must provide headroom in an initial fragment added to the
-           network buffer to store a HTC_FRAME_HDR.
-           This interface is fully asynchronous.  On error, htc_send_data_pkt will
-           call the registered Endpoint EpDataTxComplete callback to cleanup
-           the packet.
-   @example:
-   @see also: htc_send_pkt
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-#ifdef ATH_11AC_TXCOMPACT
-A_STATUS htc_send_data_pkt(HTC_HANDLE HTCHandle, cdf_nbuf_t netbuf,
-			   int Epid, int ActualLength);
-#else                           /*ATH_11AC_TXCOMPACT */
-A_STATUS htc_send_data_pkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket,
-			   A_UINT8 more_data);
-#endif /*ATH_11AC_TXCOMPACT */
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Flush HTC when target is removed surprisely service communications
-   @function name: htc_flush_surprise_remove
-   @input:  HTCHandle - HTC handle
-   @output:
-   @return:
-   @notes: All receive and pending TX packets will
-          be flushed.
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_flush_surprise_remove(HTC_HANDLE HTCHandle);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Stop HTC service communications
-   @function name: htc_stop
-   @input:  HTCHandle - HTC handle
-   @output:
-   @return:
-   @notes: HTC communications is halted.  All receive and pending TX packets will
-          be flushed.
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_stop(HTC_HANDLE HTCHandle);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Destory HTC service
-   @function name: htc_destroy
-   @input: HTCHandle
-   @output:
-   @return:
-   @notes:  This cleans up all resources allocated by htc_create().
-   @example:
-   @see also: htc_create
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_destroy(HTC_HANDLE HTCHandle);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Flush pending TX packets
-   @function name: htc_flush_endpoint
-   @input:  HTCHandle - HTC handle
-           Endpoint - Endpoint to flush
-           Tag - flush tag
-   @output:
-   @return:
-   @notes:  The Tag parameter is used to selectively flush packets with matching tags.
-           The value of 0 forces all packets to be flush regardless of tag.
-   @example:
-   @see also: htc_send_pkt
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_flush_endpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint,
-			HTC_TX_TAG Tag);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Dump credit distribution state
-   @function name: htc_dump_credit_states
-   @input:  HTCHandle - HTC handle
-   @output:
-   @return:
-   @notes:  This dumps all credit distribution information to the debugger
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_dump_credit_states(HTC_HANDLE HTCHandle);
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Indicate a traffic activity change on an endpoint
-   @function name: htc_indicate_activity_change
-   @input:  HTCHandle - HTC handle
-           Endpoint - endpoint in which activity has changed
-           Active - true if active, false if it has become inactive
-   @output:
-   @return:
-   @notes:  This triggers the registered credit distribution function to
-           re-adjust credits for active/inactive endpoints.
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_indicate_activity_change(HTC_HANDLE HTCHandle,
-				  HTC_ENDPOINT_ID Endpoint, A_BOOL Active);
-
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Get endpoint statistics
-   @function name: htc_get_endpoint_statistics
-   @input:  HTCHandle - HTC handle
-           Endpoint - Endpoint identifier
-           Action - action to take with statistics
-   @output:
-           pStats - statistics that were sampled (can be NULL if Action is HTC_EP_STAT_CLEAR)
-
-   @return: true if statistics profiling is enabled, otherwise false.
-
-   @notes:  Statistics is a compile-time option and this function may return false
-           if HTC is not compiled with profiling.
-
-           The caller can specify the statistic "action" to take when sampling
-           the statistics.  This includes:
-
-           HTC_EP_STAT_SAMPLE: The pStats structure is filled with the current values.
-           HTC_EP_STAT_SAMPLE_AND_CLEAR: The structure is filled and the current statistics
-                             are cleared.
-           HTC_EP_STAT_CLEA : the statistics are cleared, the called can pass a NULL value for
-                   pStats
-
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_BOOL htc_get_endpoint_statistics(HTC_HANDLE HTCHandle,
-				   HTC_ENDPOINT_ID Endpoint,
-				   HTC_ENDPOINT_STAT_ACTION Action,
-				   HTC_ENDPOINT_STATS *pStats);
-
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Unblock HTC message reception
-   @function name: htc_unblock_recv
-   @input:  HTCHandle - HTC handle
-   @output:
-   @return:
-   @notes:
-           HTC will block the receiver if the EpRecvAlloc callback fails to provide a packet.
-           The caller can use this API to indicate to HTC when resources (buffers) are available
-           such that the  receiver can be unblocked and HTC may re-attempt fetching the pending message.
-
-           This API is not required if the user uses the EpRecvRefill callback or uses the HTCAddReceivePacket()
-           API to recycle or provide receive packets to HTC.
-
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_unblock_recv(HTC_HANDLE HTCHandle);
-
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: send a series of HTC packets
-   @function name: htc_send_pkts_multiple
-   @input:  HTCHandle - HTC handle
-           pPktQueue - local queue holding packets to send
-   @output:
-   @return: A_OK
-   @notes:  Caller must initialize each packet using SET_HTC_PACKET_INFO_TX() macro.
-           The queue must only contain packets directed at the same endpoint.
-           Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the TX packets in FIFO order.
-           This API will remove the packets from the pkt queue and place them into the HTC Tx Queue
-           and bundle messages where possible.
-           The caller may allocate the pkt queue on the stack to hold the packets.
-           This interface is fully asynchronous.  On error, htc_send_pkts will
-           call the registered Endpoint callback to cleanup the packet.
-   @example:
-   @see also: htc_flush_endpoint
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_STATUS htc_send_pkts_multiple(HTC_HANDLE HTCHandle,
-				HTC_PACKET_QUEUE *pPktQueue);
-
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Add multiple receive packets to HTC
-   @function name: htc_add_receive_pkt_multiple
-   @input:  HTCHandle - HTC handle
-           pPktQueue - HTC receive packet queue holding packets to add
-   @output:
-   @return: A_OK on success
-   @notes:  user must supply HTC packets for capturing incomming HTC frames.  The caller
-           must initialize each HTC packet using the SET_HTC_PACKET_INFO_RX_REFILL()
-           macro. The queue must only contain recv packets for the same endpoint.
-           Caller supplies a pointer to an HTC_PACKET_QUEUE structure holding the recv packet.
-           This API will remove the packets from the pkt queue and place them into internal
-           recv packet list.
-           The caller may allocate the pkt queue on the stack to hold the packets.
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_STATUS htc_add_receive_pkt_multiple(HTC_HANDLE HTCHandle,
-				      HTC_PACKET_QUEUE *pPktQueue);
-
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Check if an endpoint is marked active
-   @function name: htc_is_endpoint_active
-   @input:  HTCHandle - HTC handle
-           Endpoint - endpoint to check for active state
-   @output:
-   @return: returns true if Endpoint is Active
-   @notes:
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-A_BOOL htc_is_endpoint_active(HTC_HANDLE HTCHandle,
-			      HTC_ENDPOINT_ID Endpoint);
-
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Get the number of recv buffers currently queued into an HTC endpoint
-   @function name: htc_get_num_recv_buffers
-   @input:  HTCHandle - HTC handle
-           Endpoint - endpoint to check
-   @output:
-   @return: returns number of buffers in queue
-   @notes:
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-int htc_get_num_recv_buffers(HTC_HANDLE HTCHandle,
-			     HTC_ENDPOINT_ID Endpoint);
-
-/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-   @desc: Set the target failure handling callback in HTC layer
-   @function name: htc_set_target_failure_callback
-   @input:  HTCHandle - HTC handle
-           Callback - target failure handling callback
-   @output:
-   @return:
-   @notes:
-   @example:
-   @see also:
- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
-void htc_set_target_failure_callback(HTC_HANDLE HTCHandle,
-				     HTC_TARGET_FAILURE Callback);
-
-/* internally used functions for testing... */
-void htc_enable_recv(HTC_HANDLE HTCHandle);
-void htc_disable_recv(HTC_HANDLE HTCHandle);
-A_STATUS HTCWaitForPendingRecv(HTC_HANDLE HTCHandle,
-			       A_UINT32 TimeoutInMs,
-			       A_BOOL *pbIsRecvPending);
-
-/* function to fetch stats from htc layer*/
-struct ol_ath_htc_stats *ieee80211_ioctl_get_htc_stats(HTC_HANDLE
-						       HTCHandle);
-
-#ifdef  HIF_USB
-#define HTCReturnReceivePkt(target,p,osbuf)		      \
-	A_NETBUF_FREE(osbuf);					  \
-	if(p->Status == A_CLONE) {				  \
-		cdf_mem_free(p);					    \
-	}
-#else
-#define HTCReturnReceivePkt(target,p,osbuf)     htc_add_receive_pkt(target,p)
-#endif
-
-#ifdef WLAN_FEATURE_FASTPATH
-#define HTC_TX_DESC_FILL(_htc_tx_desc, _download_len, _ep_id, _seq_no)	\
-do {									\
-		HTC_WRITE32((_htc_tx_desc),				\
-			SM((_download_len), HTC_FRAME_HDR_PAYLOADLEN) |	\
-			SM((_ep_id), HTC_FRAME_HDR_ENDPOINTID));	\
-									\
-		HTC_WRITE32((A_UINT32 *)(_htc_tx_desc) + 1,		\
-				SM((_seq_no), HTC_FRAME_HDR_CONTROLBYTES1));\
-} while (0)
-#endif /* WLAN_FEATURE_FASTPATH */
-
-#ifdef __cplusplus
-}
-#endif
-void htc_get_control_endpoint_tx_host_credits(HTC_HANDLE HTCHandle, int *credit);
-void htc_dump_counter_info(HTC_HANDLE HTCHandle);
-void *htc_get_targetdef(HTC_HANDLE htc_handle);
-void htc_set_target_to_sleep(void *context);
-void htc_cancel_deferred_target_sleep(void *context);
-int htc_runtime_suspend(void);
-int htc_runtime_resume(void);
-
-/* Disable ASPM : Disable PCIe low power */
-void htc_disable_aspm(void);
-
-#ifdef IPA_OFFLOAD
-void htc_ipa_get_ce_resource(HTC_HANDLE htc_handle,
-			     cdf_dma_addr_t *ce_sr_base_paddr,
-			     uint32_t *ce_sr_ring_size,
-			     cdf_dma_addr_t *ce_reg_paddr);
-#else
-#define htc_ipa_get_ce_resource(htc_handle,                \
-			ce_sr_base_paddr,                  \
-			ce_sr_ring_size,                   \
-			ce_reg_paddr)                      /* NO-OP */
-#endif /* IPA_OFFLOAD */
-#endif /* _HTC_API_H_ */

core/htc/htc_debug.h

@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef HTC_DEBUG_H_
-#define HTC_DEBUG_H_
-
-#define ATH_MODULE_NAME htc
-#include "a_debug.h"
-#include "cdf_trace.h"
-
-/* ------- Debug related stuff ------- */
-
-#define  ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0)
-#define  ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1)
-#define  ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2)
-#define  ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3)
-#define  ATH_DEBUG_SETUP  ATH_DEBUG_MAKE_MODULE_MASK(4)
-#define HTC_ERROR(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HTC, CDF_TRACE_LEVEL_ERROR, ## args)
-#define HTC_WARN(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HTC, CDF_TRACE_LEVEL_WARN, ## args)
-#define HTC_INFO(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HTC, CDF_TRACE_LEVEL_INFO, ## args)
-#define HTC_TRACE(args ...) \
-	CDF_TRACE(CDF_MODULE_ID_HTC, CDF_TRACE_LEVEL_DEBUG, ## args)
-#endif /*HTC_DEBUG_H_ */

core/htc/htc_internal.h

@@ -1,317 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef _HTC_INTERNAL_H_
-#define _HTC_INTERNAL_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#include <athdefs.h>
-#include "a_types.h"
-#include "osapi_linux.h"
-#include <cdf_nbuf.h>
-#include <cdf_types.h>
-#include <cdf_lock.h>
-#include <cdf_softirq_timer.h>
-#include <cdf_atomic.h>
-#include "hif.h"
-#include <htc.h>
-#include "htc_api.h"
-#include "htc_packet.h"
-
-/* HTC operational parameters */
-#define HTC_TARGET_RESPONSE_TIMEOUT         2000        /* in ms */
-#define HTC_TARGET_DEBUG_INTR_MASK          0x01
-#define HTC_TARGET_CREDIT_INTR_MASK         0xF0
-#define HTC_MIN_MSG_PER_BUNDLE              2
-#if defined(HIF_USB)
-#define HTC_MAX_MSG_PER_BUNDLE              9
-#else
-#define HTC_MAX_MSG_PER_BUNDLE              16
-#endif
-/*
- * HTC_MAX_TX_BUNDLE_SEND_LIMIT -
- * This value is in units of tx frame fragments.
- * It needs to be at least as large as the maximum number of tx frames in a
- * HTC download bundle times the average number of fragments in each such frame
- * (In certain operating systems, such as Linux, we expect to only have
- * a single fragment per frame anyway.)
- */
-#define HTC_MAX_TX_BUNDLE_SEND_LIMIT        255
-
-#define HTC_PACKET_CONTAINER_ALLOCATION     32
-#define NUM_CONTROL_TX_BUFFERS              2
-#define HTC_CONTROL_BUFFER_SIZE             (HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH)
-#define HTC_CONTROL_BUFFER_ALIGN            32
-#define HTC_TARGET_RESPONSE_POLL_MS         10
-#if !defined(A_SIMOS_DEVHOST)
-#define HTC_TARGET_MAX_RESPONSE_POLL        200 /* actual HW */
-#else
-#define HTC_TARGET_MAX_RESPONSE_POLL        600 /* host + target simulation */
-#endif
-
-#define HTC_SERVICE_TX_PACKET_TAG  HTC_TX_PACKET_TAG_INTERNAL
-
-#define HTC_CREDIT_HISTORY_MAX              1024
-
-typedef enum {
-	HTC_REQUEST_CREDIT,
-	HTC_PROCESS_CREDIT_REPORT,
-	HTC_SUSPEND_ACK,
-	HTC_SUSPEND_NACK,
-} htc_credit_exchange_type;
-
-typedef struct {
-	htc_credit_exchange_type type;
-	uint64_t time;
-	uint32_t tx_credit;
-	uint32_t htc_tx_queue_depth;
-} HTC_CREDIT_HISTORY;
-
-typedef struct _HTC_ENDPOINT {
-	HTC_ENDPOINT_ID Id;
-
-	/* service ID this endpoint is bound to
-	 * non-zero value means this endpoint is in use
-	 */
-	HTC_SERVICE_ID service_id;
-
-	HTC_EP_CALLBACKS EpCallBacks;           /* callbacks associated with this endpoint */
-	HTC_PACKET_QUEUE TxQueue;               /* HTC frame buffer TX queue */
-	int MaxTxQueueDepth;            /* max depth of the TX queue before we need to
-	                                   call driver's full handler */
-	int MaxMsgLength;               /* max length of endpoint message */
-	uint8_t UL_PipeID;
-	uint8_t DL_PipeID;
-	int ul_is_polled;               /* Need to call HIF to get tx completion callbacks? */
-	cdf_softirq_timer_t ul_poll_timer;
-	int ul_poll_timer_active;
-	int ul_outstanding_cnt;
-	int dl_is_polled;               /* Need to call HIF to fetch rx?  (Not currently supported.) */
-#if 0                           /* not currently supported */
-	cdf_softirq_timer_t dl_poll_timer;
-#endif
-
-	HTC_PACKET_QUEUE TxLookupQueue;         /* lookup queue to match netbufs to htc packets */
-	HTC_PACKET_QUEUE RxBufferHoldQueue;             /* temporary hold queue for back compatibility */
-	A_UINT8 SeqNo;          /* TX seq no (helpful) for debugging */
-	cdf_atomic_t TxProcessCount;            /* serialization */
-	struct _HTC_TARGET *target;
-	int TxCredits;          /* TX credits available on this endpoint */
-	int TxCreditSize;               /* size in bytes of each credit (set by HTC) */
-	int TxCreditsPerMaxMsg;         /* credits required per max message (precalculated) */
-#ifdef HTC_EP_STAT_PROFILING
-	HTC_ENDPOINT_STATS endpoint_stats;     /* endpoint statistics */
-#endif
-	A_BOOL TxCreditFlowEnabled;
-} HTC_ENDPOINT;
-
-#ifdef HTC_EP_STAT_PROFILING
-#define INC_HTC_EP_STAT(p, stat, count) ((p)->endpoint_stats.stat += (count))
-#else
-#define INC_HTC_EP_STAT(p, stat, count)
-#endif
-
-typedef struct {
-	A_UINT16 service_id;
-	A_UINT8 CreditAllocation;
-} HTC_SERVICE_TX_CREDIT_ALLOCATION;
-
-#define HTC_MAX_SERVICE_ALLOC_ENTRIES 8
-
-/* Error codes for HTC layer packet stats*/
-enum ol_ath_htc_pkt_ecodes {
-	GET_HTC_PKT_Q_FAIL = 0,         /* error- get packet at head of HTC_PACKET_Q */
-	HTC_PKT_Q_EMPTY,
-	HTC_SEND_Q_EMPTY
-};
-/* our HTC target state */
-typedef struct _HTC_TARGET {
-	struct ol_softc *hif_dev;
-	HTC_ENDPOINT endpoint[ENDPOINT_MAX];
-	cdf_spinlock_t HTCLock;
-	cdf_spinlock_t HTCRxLock;
-	cdf_spinlock_t HTCTxLock;
-	cdf_spinlock_t HTCCreditLock;
-	A_UINT32 HTCStateFlags;
-	void *host_handle;
-	HTC_INIT_INFO HTCInitInfo;
-	HTC_PACKET *pHTCPacketStructPool;               /* pool of HTC packets */
-	HTC_PACKET_QUEUE ControlBufferTXFreeList;
-	A_UINT8 CtrlResponseBuffer[HTC_MAX_CONTROL_MESSAGE_LENGTH];
-	int CtrlResponseLength;
-	cdf_event_t ctrl_response_valid;
-	A_BOOL CtrlResponseProcessing;
-	int TotalTransmitCredits;
-	HTC_SERVICE_TX_CREDIT_ALLOCATION
-		ServiceTxAllocTable[HTC_MAX_SERVICE_ALLOC_ENTRIES];
-	int TargetCreditSize;
-#ifdef RX_SG_SUPPORT
-	cdf_nbuf_queue_t RxSgQueue;
-	A_BOOL IsRxSgInprogress;
-	A_UINT32 CurRxSgTotalLen;               /* current total length */
-	A_UINT32 ExpRxSgTotalLen;               /* expected total length */
-#endif
-	cdf_device_t osdev;
-	struct ol_ath_htc_stats htc_pkt_stats;
-	HTC_PACKET *pBundleFreeList;
-	A_UINT32 ce_send_cnt;
-	A_UINT32 TX_comp_cnt;
-	A_UINT8 MaxMsgsPerHTCBundle;
-	cdf_work_t queue_kicker;
-} HTC_TARGET;
-
-#define HTC_ENABLE_BUNDLE(target) (target->MaxMsgsPerHTCBundle > 1)
-#ifdef RX_SG_SUPPORT
-#define RESET_RX_SG_CONFIG(_target) \
-	_target->ExpRxSgTotalLen = 0; \
-	_target->CurRxSgTotalLen = 0; \
-	_target->IsRxSgInprogress = false;
-#endif
-
-#define HTC_STATE_STOPPING      (1 << 0)
-#define HTC_STOPPING(t)         ((t)->HTCStateFlags & HTC_STATE_STOPPING)
-#define LOCK_HTC(t)             cdf_spin_lock_bh(&(t)->HTCLock);
-#define UNLOCK_HTC(t)           cdf_spin_unlock_bh(&(t)->HTCLock);
-#define LOCK_HTC_RX(t)          cdf_spin_lock_bh(&(t)->HTCRxLock);
-#define UNLOCK_HTC_RX(t)        cdf_spin_unlock_bh(&(t)->HTCRxLock);
-#define LOCK_HTC_TX(t)          cdf_spin_lock_bh(&(t)->HTCTxLock);
-#define UNLOCK_HTC_TX(t)        cdf_spin_unlock_bh(&(t)->HTCTxLock);
-#define LOCK_HTC_CREDIT(t)      cdf_spin_lock_bh(&(t)->HTCCreditLock);
-#define UNLOCK_HTC_CREDIT(t)    cdf_spin_unlock_bh(&(t)->HTCCreditLock);
-
-#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
-
-#define IS_TX_CREDIT_FLOW_ENABLED(ep)  ((ep)->TxCreditFlowEnabled)
-
-#define HTC_POLL_CLEANUP_PERIOD_MS 10   /* milliseconds */
-
-/* Macro to Increment the  HTC_PACKET_ERRORS for Tx.*/
-#define OL_ATH_HTC_PKT_ERROR_COUNT_INCR(_target,_ecode)	\
-	do { \
-		if(_ecode==GET_HTC_PKT_Q_FAIL) (_target->htc_pkt_stats.htc_get_pkt_q_fail_count)+=1; \
-		if(_ecode==HTC_PKT_Q_EMPTY) (_target->htc_pkt_stats.htc_pkt_q_empty_count)+=1; \
-		if(_ecode==HTC_SEND_Q_EMPTY) (_target->htc_pkt_stats.htc_send_q_empty_count)+=1; \
-	} while(0);
-/* internal HTC functions */
-
-CDF_STATUS htc_rx_completion_handler(void *Context, cdf_nbuf_t netbuf,
-				   uint8_t pipeID);
-CDF_STATUS htc_tx_completion_handler(void *Context, cdf_nbuf_t netbuf,
-				   unsigned int transferID, uint32_t toeplitz_hash_result);
-
-HTC_PACKET *allocate_htc_bundle_packet(HTC_TARGET *target);
-void free_htc_bundle_packet(HTC_TARGET *target, HTC_PACKET *pPacket);
-
-HTC_PACKET *allocate_htc_packet_container(HTC_TARGET *target);
-void free_htc_packet_container(HTC_TARGET *target, HTC_PACKET *pPacket);
-void htc_flush_rx_hold_queue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint);
-void htc_flush_endpoint_tx(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint,
-			   HTC_TX_TAG Tag);
-void htc_recv_init(HTC_TARGET *target);
-A_STATUS htc_wait_recv_ctrl_message(HTC_TARGET *target);
-void htc_free_control_tx_packet(HTC_TARGET *target, HTC_PACKET *pPacket);
-HTC_PACKET *htc_alloc_control_tx_packet(HTC_TARGET *target);
-A_UINT8 htc_get_credit_allocation(HTC_TARGET *target, A_UINT16 service_id);
-void htc_tx_resource_avail_handler(void *context, A_UINT8 pipeID);
-void htc_control_rx_complete(void *Context, HTC_PACKET *pPacket);
-void htc_process_credit_rpt(HTC_TARGET *target,
-			    HTC_CREDIT_REPORT *pRpt,
-			    int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
-void htc_fw_event_handler(void *context, CDF_STATUS status);
-void htc_send_complete_check_cleanup(void *context);
-void htc_runtime_pm_init(HTC_TARGET *target);
-void htc_kick_queues(void *context);
-
-void htc_credit_record(htc_credit_exchange_type type, uint32_t tx_credit,
-		       uint32_t htc_tx_queue_depth);
-
-static inline void htc_send_complete_poll_timer_stop(HTC_ENDPOINT *
-						     pEndpoint) {
-	LOCK_HTC_TX(pEndpoint->target);
-	if (pEndpoint->ul_poll_timer_active) {
-		/* cdf_softirq_timer_cancel(&pEndpoint->ul_poll_timer); */
-		pEndpoint->ul_poll_timer_active = 0;
-	}
-	UNLOCK_HTC_TX(pEndpoint->target);
-}
-
-static inline void htc_send_complete_poll_timer_start(HTC_ENDPOINT *
-						      pEndpoint) {
-	LOCK_HTC_TX(pEndpoint->target);
-	if (pEndpoint->ul_outstanding_cnt
-	    && !pEndpoint->ul_poll_timer_active) {
-		/*
-		   cdf_softirq_timer_start(
-		   &pEndpoint->ul_poll_timer, HTC_POLL_CLEANUP_PERIOD_MS);
-		 */
-		pEndpoint->ul_poll_timer_active = 1;
-	}
-	UNLOCK_HTC_TX(pEndpoint->target);
-}
-
-static inline void
-htc_send_complete_check(HTC_ENDPOINT *pEndpoint, int force) {
-	/*
-	 * Stop the polling-cleanup timer that will result in a later call to
-	 * this function.  It may get started again below, if there are still
-	 * outsending sends.
-	 */
-	htc_send_complete_poll_timer_stop(pEndpoint);
-	/*
-	 * Check whether HIF has any prior sends that have finished,
-	 * have not had the post-processing done.
-	 */
-	hif_send_complete_check(pEndpoint->target->hif_dev,
-				pEndpoint->UL_PipeID, force);
-	/*
-	 * If there are still outstanding sends after polling, start a timer
-	 * to check again a little later.
-	 */
-	htc_send_complete_poll_timer_start(pEndpoint);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#ifndef DEBUG_BUNDLE
-#define DEBUG_BUNDLE 0
-#endif
-
-#ifdef HIF_SDIO
-#ifndef ENABLE_BUNDLE_TX
-#define ENABLE_BUNDLE_TX 1
-#endif
-
-#ifndef ENABLE_BUNDLE_RX
-#define ENABLE_BUNDLE_RX 1
-#endif
-#endif /* HIF_SDIO */
-#endif /* !_HTC_HOST_INTERNAL_H_ */

core/htc/htc_packet.h

@@ -1,280 +0,0 @@
-/*
- * Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#ifndef HTC_PACKET_H_
-#define HTC_PACKET_H_
-
-#include <osdep.h>
-#include <a_types.h>            /* A_UINT16, etc. */
-#include "dl_list.h"
-
-/* ------ Endpoint IDS ------ */
-typedef enum {
-	ENDPOINT_UNUSED = -1,
-	ENDPOINT_0 = 0,
-	ENDPOINT_1 = 1,
-	ENDPOINT_2 = 2,
-	ENDPOINT_3,
-	ENDPOINT_4,
-	ENDPOINT_5,
-	ENDPOINT_6,
-	ENDPOINT_7,
-	ENDPOINT_8,
-	ENDPOINT_MAX,
-} HTC_ENDPOINT_ID;
-
-struct _HTC_PACKET;
-
-typedef void (*HTC_PACKET_COMPLETION)(void *, struct _HTC_PACKET *);
-
-typedef A_UINT16 HTC_TX_TAG;
-
-typedef struct _HTC_TX_PACKET_INFO {
-	HTC_TX_TAG Tag;         /* tag used to selective flush packets */
-	int CreditsUsed;        /* number of credits used for this TX packet (HTC internal) */
-	A_UINT8 SendFlags;      /* send flags (HTC internal) */
-	int SeqNo;              /* internal seq no for debugging (HTC internal) */
-	A_UINT32 Flags;         /* internal use */
-} HTC_TX_PACKET_INFO;
-
-/**
- * HTC_TX_PACKET_TAG_XXX - #defines for tagging packets for special handling
- * HTC_TX_PACKET_TAG_ALL: zero is reserved and used to flush ALL packets
- * HTC_TX_PACKET_TAG_INTERNAL: internal tags start here
- * HTC_TX_PACKET_TAG_USER_DEFINED: user-defined tags start here
- * HTC_TX_PACKET_TAG_BUNDLED: indicate this is a bundled tx packet
- * HTC_TX_PACKET_TAG_AUTO_PM: indicate a power management wmi command
- */
-#define HTC_TX_PACKET_TAG_ALL          0
-#define HTC_TX_PACKET_TAG_INTERNAL     1
-#define HTC_TX_PACKET_TAG_USER_DEFINED (HTC_TX_PACKET_TAG_INTERNAL + 9)
-#define HTC_TX_PACKET_TAG_BUNDLED      (HTC_TX_PACKET_TAG_USER_DEFINED + 1)
-#define HTC_TX_PACKET_TAG_AUTO_PM      (HTC_TX_PACKET_TAG_USER_DEFINED + 2)
-
-/* Tag packet for runtime put after sending */
-#define HTC_TX_PACKET_TAG_RUNTIME_PUT  (HTC_TX_PACKET_TAG_USER_DEFINED + 3)
-
-
-#define HTC_TX_PACKET_FLAG_FIXUP_NETBUF (1 << 0)
-
-typedef struct _HTC_RX_PACKET_INFO {
-	A_UINT32 ExpectedHdr;   /* HTC internal use */
-	A_UINT32 HTCRxFlags;    /* HTC internal use */
-	A_UINT32 IndicationFlags;       /* indication flags set on each RX packet indication */
-} HTC_RX_PACKET_INFO;
-
-#define HTC_RX_FLAGS_INDICATE_MORE_PKTS  (1 << 0)       /* more packets on this endpoint are being fetched */
-
-/* wrapper around endpoint-specific packets */
-typedef struct _HTC_PACKET {
-	DL_LIST ListLink;       /* double link */
-	void *pPktContext;      /* caller's per packet specific context */
-
-	A_UINT8 *pBufferStart;  /* the true buffer start , the caller can
-	                           store the real buffer start here.  In
-	                           receive callbacks, the HTC layer sets pBuffer
-	                           to the start of the payload past the header. This
-	                           field allows the caller to reset pBuffer when it
-	                           recycles receive packets back to HTC */
-	/*
-	 * Pointer to the start of the buffer. In the transmit
-	 * direction this points to the start of the payload. In the
-	 * receive direction, however, the buffer when queued up
-	 * points to the start of the HTC header but when returned
-	 * to the caller points to the start of the payload
-	 */
-	A_UINT8 *pBuffer;       /* payload start (RX/TX) */
-	A_UINT32 BufferLength;  /* length of buffer */
-	A_UINT32 ActualLength;  /* actual length of payload */
-	HTC_ENDPOINT_ID Endpoint;       /* endpoint that this packet was sent/recv'd from */
-	A_STATUS Status;        /* completion status */
-	union {
-		HTC_TX_PACKET_INFO AsTx;        /* Tx Packet specific info */
-		HTC_RX_PACKET_INFO AsRx;        /* Rx Packet specific info */
-	} PktInfo;
-
-	/* the following fields are for internal HTC use */
-	A_UINT32 netbufOrigHeadRoom;
-	HTC_PACKET_COMPLETION Completion;       /* completion */
-	void *pContext;         /* HTC private completion context */
-	void *pNetBufContext;   /* optimization for network-oriented data, the HTC packet
-	                           can pass the network buffer corresponding to the HTC packet
-	                           lower layers may optimized the transfer knowing this is
-	                           a network buffer */
-} HTC_PACKET;
-
-#define COMPLETE_HTC_PACKET(p,status)	     \
-	{					     \
-		(p)->Status = (status);			 \
-		(p)->Completion((p)->pContext,(p));	 \
-	}
-
-#define INIT_HTC_PACKET_INFO(p,b,len)		  \
-	{						  \
-		(p)->pBufferStart = (b);		      \
-		(p)->BufferLength = (len);		      \
-	}
-
-/* macro to set an initial RX packet for refilling HTC */
-#define SET_HTC_PACKET_INFO_RX_REFILL(p,c,b,len,ep) \
-	{						  \
-		(p)->pPktContext = (c);			      \
-		(p)->pBuffer = (b);			      \
-		(p)->pBufferStart = (b);		      \
-		(p)->BufferLength = (len);		      \
-		(p)->Endpoint = (ep);			      \
-	}
-
-/* fast macro to recycle an RX packet that will be re-queued to HTC */
-#define HTC_PACKET_RESET_RX(p)		    \
-	{ (p)->pBuffer = (p)->pBufferStart; (p)->ActualLength = 0; }
-
-/* macro to set packet parameters for TX */
-#define SET_HTC_PACKET_INFO_TX(p,c,b,len,ep,tag)  \
-	{						  \
-		(p)->pPktContext = (c);			      \
-		(p)->pBuffer = (b);			      \
-		(p)->ActualLength = (len);		      \
-		(p)->Endpoint = (ep);			      \
-		(p)->PktInfo.AsTx.Tag = (tag);		      \
-		(p)->PktInfo.AsTx.Flags = 0;		      \
-		(p)->PktInfo.AsTx.SendFlags = 0;	      \
-	}
-
-#define SET_HTC_PACKET_NET_BUF_CONTEXT(p,nb) \
-	(p)->pNetBufContext = (nb)
-
-#define GET_HTC_PACKET_NET_BUF_CONTEXT(p)  (p)->pNetBufContext
-
-/* HTC Packet Queueing Macros */
-typedef struct _HTC_PACKET_QUEUE {
-	DL_LIST QueueHead;
-	int Depth;
-} HTC_PACKET_QUEUE;
-
-/* initialize queue */
-#define INIT_HTC_PACKET_QUEUE(pQ)   \
-	{				    \
-		DL_LIST_INIT(& (pQ)->QueueHead); \
-		(pQ)->Depth = 0;		\
-	}
-
-/* enqueue HTC packet to the tail of the queue */
-#define HTC_PACKET_ENQUEUE(pQ,p)			\
-	{   dl_list_insert_tail(& (pQ)->QueueHead,& (p)->ListLink); \
-	    (pQ)->Depth ++;					 \
-	}
-
-/* enqueue HTC packet to the tail of the queue */
-#define HTC_PACKET_ENQUEUE_TO_HEAD(pQ,p)		\
-	{   dl_list_insert_head(& (pQ)->QueueHead,& (p)->ListLink); \
-	    (pQ)->Depth ++;					 \
-	}
-/* test if a queue is empty */
-#define HTC_QUEUE_EMPTY(pQ)       ((pQ)->Depth == 0)
-/* get packet at head without removing it */
-static INLINE HTC_PACKET *htc_get_pkt_at_head(HTC_PACKET_QUEUE *queue)
-{
-	if (queue->Depth == 0) {
-		return NULL;
-	}
-	return
-		A_CONTAINING_STRUCT((DL_LIST_GET_ITEM_AT_HEAD(&queue->QueueHead)),
-				    HTC_PACKET, ListLink);
-}
-
-/* remove a packet from a queue, where-ever it is in the queue */
-#define HTC_PACKET_REMOVE(pQ,p)	    \
-	{				    \
-		dl_list_remove(& (p)->ListLink);  \
-		(pQ)->Depth --;			 \
-	}
-
-/* dequeue an HTC packet from the head of the queue */
-static INLINE HTC_PACKET *htc_packet_dequeue(HTC_PACKET_QUEUE *queue)
-{
-	DL_LIST *pItem = dl_list_remove_item_from_head(&queue->QueueHead);
-	if (pItem != NULL) {
-		queue->Depth--;
-		return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
-	}
-	return NULL;
-}
-
-/* dequeue an HTC packet from the tail of the queue */
-static INLINE HTC_PACKET *htc_packet_dequeue_tail(HTC_PACKET_QUEUE *queue)
-{
-	DL_LIST *pItem = dl_list_remove_item_from_tail(&queue->QueueHead);
-	if (pItem != NULL) {
-		queue->Depth--;
-		return A_CONTAINING_STRUCT(pItem, HTC_PACKET, ListLink);
-	}
-	return NULL;
-}
-
-#define HTC_PACKET_QUEUE_DEPTH(pQ) (pQ)->Depth
-
-#define HTC_GET_ENDPOINT_FROM_PKT(p) (p)->Endpoint
-#define HTC_GET_TAG_FROM_PKT(p)      (p)->PktInfo.AsTx.Tag
-
-/* transfer the packets from one queue to the tail of another queue */
-#define HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(pQDest,pQSrc)	\
-	{									    \
-		dl_list_transfer_items_to_tail(&(pQDest)->QueueHead,&(pQSrc)->QueueHead);   \
-		(pQDest)->Depth += (pQSrc)->Depth;					\
-		(pQSrc)->Depth = 0;							\
-	}
-
-/*
- * Transfer the packets from one queue to the head of another queue.
- * This xfer_to_head(q1,q2) is basically equivalent to xfer_to_tail(q2,q1),
- * but it updates the queue descriptor object for the initial queue to refer
- * to the concatenated queue.
- */
-#define HTC_PACKET_QUEUE_TRANSFER_TO_HEAD(pQDest, pQSrc)  \
-	{									    \
-		dl_list_transfer_items_to_head(&(pQDest)->QueueHead,&(pQSrc)->QueueHead);   \
-		(pQDest)->Depth += (pQSrc)->Depth;					\
-		(pQSrc)->Depth = 0;							\
-	}
-
-/* fast version to init and add a single packet to a queue */
-#define INIT_HTC_PACKET_QUEUE_AND_ADD(pQ,pP) \
-	{					     \
-		DL_LIST_INIT_AND_ADD(&(pQ)->QueueHead,&(pP)->ListLink)	\
-		(pQ)->Depth = 1;					\
-	}
-
-#define HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pQ, pPTemp) \
-	ITERATE_OVER_LIST_ALLOW_REMOVE(&(pQ)->QueueHead,(pPTemp), HTC_PACKET, ListLink)
-
-#define HTC_PACKET_QUEUE_ITERATE_IS_VALID(pQ)   ITERATE_IS_VALID(&(pQ)->QueueHead)
-#define HTC_PACKET_QUEUE_ITERATE_RESET(pQ) ITERATE_RESET(&(pQ)->QueueHead)
-
-#define HTC_PACKET_QUEUE_ITERATE_END ITERATE_END
-
-#endif /*HTC_PACKET_H_ */

core/htc/htc_recv.c

@@ -1,749 +0,0 @@
-/*
- * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include "htc_debug.h"
-#include "htc_internal.h"
-#include "cds_api.h"
-#include <cdf_nbuf.h>           /* cdf_nbuf_t */
-#include "epping_main.h"
-
-/* HTC Control message receive timeout msec */
-#define HTC_CONTROL_RX_TIMEOUT     3000
-
-#ifdef DEBUG
-void debug_dump_bytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
-{
-	A_CHAR stream[60];
-	A_CHAR byteOffsetStr[10];
-	A_UINT32 i;
-	A_UINT16 offset, count, byteOffset;
-
-	A_PRINTF("<---------Dumping %d Bytes : %s ------>\n", length,
-		 pDescription);
-
-	count = 0;
-	offset = 0;
-	byteOffset = 0;
-	for (i = 0; i < length; i++) {
-		A_SNPRINTF(stream + offset, (sizeof(stream) - offset),
-			   "%02X ", buffer[i]);
-		count++;
-		offset += 3;
-
-		if (count == 16) {
-			count = 0;
-			offset = 0;
-			A_SNPRINTF(byteOffsetStr, sizeof(byteOffset), "%4.4X",
-				   byteOffset);
-			A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
-			A_MEMZERO(stream, 60);
-			byteOffset += 16;
-		}
-	}
-
-	if (offset != 0) {
-		A_SNPRINTF(byteOffsetStr, sizeof(byteOffset), "%4.4X",
-			   byteOffset);
-		A_PRINTF("[%s]: %s\n", byteOffsetStr, stream);
-	}
-
-	A_PRINTF("<------------------------------------------------->\n");
-}
-#else
-void debug_dump_bytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription)
-{
-}
-#endif
-
-static A_STATUS htc_process_trailer(HTC_TARGET *target,
-				    A_UINT8 *pBuffer,
-				    int Length, HTC_ENDPOINT_ID FromEndpoint);
-
-static void do_recv_completion(HTC_ENDPOINT *pEndpoint,
-			       HTC_PACKET_QUEUE *pQueueToIndicate)
-{
-
-	do {
-
-		if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
-			/* nothing to indicate */
-			break;
-		}
-
-		if (pEndpoint->EpCallBacks.EpRecvPktMultiple != NULL) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
-					(" HTC calling ep %d, recv multiple callback (%d pkts) \n",
-					 pEndpoint->Id,
-					 HTC_PACKET_QUEUE_DEPTH
-						 (pQueueToIndicate)));
-			/* a recv multiple handler is being used, pass the queue to the handler */
-			pEndpoint->EpCallBacks.EpRecvPktMultiple(pEndpoint->
-								 EpCallBacks.
-								 pContext,
-								 pQueueToIndicate);
-			INIT_HTC_PACKET_QUEUE(pQueueToIndicate);
-		} else {
-			HTC_PACKET *pPacket;
-			/* using legacy EpRecv */
-			while (!HTC_QUEUE_EMPTY(pQueueToIndicate)) {
-				pPacket = htc_packet_dequeue(pQueueToIndicate);
-				if (pEndpoint->EpCallBacks.EpRecv == NULL) {
-					AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-							("HTC ep %d has NULL recv callback on packet %p\n",
-							 pEndpoint->Id,
-							 pPacket));
-					continue;
-				}
-				AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
-						("HTC calling ep %d recv callback on packet %p\n",
-						 pEndpoint->Id, pPacket));
-				pEndpoint->EpCallBacks.EpRecv(pEndpoint->
-							      EpCallBacks.
-							      pContext,
-							      pPacket);
-			}
-		}
-
-	} while (false);
-
-}
-
-static void recv_packet_completion(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint,
-				   HTC_PACKET *pPacket)
-{
-	HTC_PACKET_QUEUE container;
-	INIT_HTC_PACKET_QUEUE_AND_ADD(&container, pPacket);
-	/* do completion */
-	do_recv_completion(pEndpoint, &container);
-}
-
-void htc_control_rx_complete(void *Context, HTC_PACKET *pPacket)
-{
-	/* TODO, can't really receive HTC control messages yet.... */
-	AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-			("Invalid call to  htc_control_rx_complete\n"));
-}
-
-void htc_unblock_recv(HTC_HANDLE HTCHandle)
-{
-	/* TODO  find the Need in new model */
-}
-
-void htc_enable_recv(HTC_HANDLE HTCHandle)
-{
-
-	/* TODO  find the Need in new model */
-}
-
-void htc_disable_recv(HTC_HANDLE HTCHandle)
-{
-
-	/* TODO  find the Need in new model */
-}
-
-int htc_get_num_recv_buffers(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint = &target->endpoint[Endpoint];
-	return HTC_PACKET_QUEUE_DEPTH(&pEndpoint->RxBufferHoldQueue);
-}
-
-HTC_PACKET *allocate_htc_packet_container(HTC_TARGET *target)
-{
-	HTC_PACKET *pPacket;
-
-	LOCK_HTC_RX(target);
-
-	if (NULL == target->pHTCPacketStructPool) {
-		UNLOCK_HTC_RX(target);
-		return NULL;
-	}
-
-	pPacket = target->pHTCPacketStructPool;
-	target->pHTCPacketStructPool = (HTC_PACKET *) pPacket->ListLink.pNext;
-
-	UNLOCK_HTC_RX(target);
-
-	pPacket->ListLink.pNext = NULL;
-	return pPacket;
-}
-
-void free_htc_packet_container(HTC_TARGET *target, HTC_PACKET *pPacket)
-{
-	LOCK_HTC_RX(target);
-
-	if (NULL == target->pHTCPacketStructPool) {
-		target->pHTCPacketStructPool = pPacket;
-		pPacket->ListLink.pNext = NULL;
-	} else {
-		pPacket->ListLink.pNext =
-			(DL_LIST *) target->pHTCPacketStructPool;
-		target->pHTCPacketStructPool = pPacket;
-	}
-
-	UNLOCK_HTC_RX(target);
-}
-
-#ifdef RX_SG_SUPPORT
-cdf_nbuf_t rx_sg_to_single_netbuf(HTC_TARGET *target)
-{
-	cdf_nbuf_t skb;
-	uint8_t *anbdata;
-	uint8_t *anbdata_new;
-	uint32_t anblen;
-	cdf_nbuf_t new_skb = NULL;
-	uint32_t sg_queue_len;
-	cdf_nbuf_queue_t *rx_sg_queue = &target->RxSgQueue;
-
-	sg_queue_len = cdf_nbuf_queue_len(rx_sg_queue);
-
-	if (sg_queue_len <= 1) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-				("rx_sg_to_single_netbuf: invalid sg queue len %u\n"));
-		goto _failed;
-	}
-
-	new_skb = cdf_nbuf_alloc(target->ExpRxSgTotalLen, 0, 4, false);
-	if (new_skb == NULL) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-				("rx_sg_to_single_netbuf: can't allocate %u size netbuf\n",
-				 target->ExpRxSgTotalLen));
-		goto _failed;
-	}
-
-	cdf_nbuf_peek_header(new_skb, &anbdata_new, &anblen);
-
-	skb = cdf_nbuf_queue_remove(rx_sg_queue);
-	do {
-		cdf_nbuf_peek_header(skb, &anbdata, &anblen);
-		cdf_mem_copy(anbdata_new, anbdata, cdf_nbuf_len(skb));
-		cdf_nbuf_put_tail(new_skb, cdf_nbuf_len(skb));
-		anbdata_new += cdf_nbuf_len(skb);
-		cdf_nbuf_free(skb);
-		skb = cdf_nbuf_queue_remove(rx_sg_queue);
-	} while (skb != NULL);
-
-	RESET_RX_SG_CONFIG(target);
-	return new_skb;
-
-_failed:
-
-	while ((skb = cdf_nbuf_queue_remove(rx_sg_queue)) != NULL) {
-		cdf_nbuf_free(skb);
-	}
-
-	RESET_RX_SG_CONFIG(target);
-	return NULL;
-}
-#endif
-
-CDF_STATUS htc_rx_completion_handler(void *Context, cdf_nbuf_t netbuf,
-				   uint8_t pipeID)
-{
-	CDF_STATUS status = CDF_STATUS_SUCCESS;
-	HTC_FRAME_HDR *HtcHdr;
-	HTC_TARGET *target = (HTC_TARGET *) Context;
-	uint8_t *netdata;
-	uint32_t netlen;
-	HTC_ENDPOINT *pEndpoint;
-	HTC_PACKET *pPacket;
-	A_UINT16 payloadLen;
-	uint32_t trailerlen = 0;
-	A_UINT8 htc_ep_id;
-
-#ifdef RX_SG_SUPPORT
-	LOCK_HTC_RX(target);
-	if (target->IsRxSgInprogress) {
-		target->CurRxSgTotalLen += cdf_nbuf_len(netbuf);
-		cdf_nbuf_queue_add(&target->RxSgQueue, netbuf);
-		if (target->CurRxSgTotalLen == target->ExpRxSgTotalLen) {
-			netbuf = rx_sg_to_single_netbuf(target);
-			if (netbuf == NULL) {
-				UNLOCK_HTC_RX(target);
-				goto _out;
-			}
-		} else {
-			netbuf = NULL;
-			UNLOCK_HTC_RX(target);
-			goto _out;
-		}
-	}
-	UNLOCK_HTC_RX(target);
-#endif
-
-	netdata = cdf_nbuf_data(netbuf);
-	netlen = cdf_nbuf_len(netbuf);
-
-	HtcHdr = (HTC_FRAME_HDR *) netdata;
-
-	do {
-
-		htc_ep_id = HTC_GET_FIELD(HtcHdr, HTC_FRAME_HDR, ENDPOINTID);
-
-		if (htc_ep_id >= ENDPOINT_MAX) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					("HTC Rx: invalid EndpointID=%d\n",
-					 htc_ep_id));
-			debug_dump_bytes((A_UINT8 *) HtcHdr,
-					 sizeof(HTC_FRAME_HDR), "BAD HTC Header");
-			status = CDF_STATUS_E_FAILURE;
-			CDF_BUG(0);
-			break;
-		}
-
-		pEndpoint = &target->endpoint[htc_ep_id];
-
-		/*
-		 * If this endpoint that received a message from the target has
-		 * a to-target HIF pipe whose send completions are polled rather
-		 * than interrupt-driven, this is a good point to ask HIF to check
-		 * whether it has any completed sends to handle.
-		 */
-		if (pEndpoint->ul_is_polled) {
-			htc_send_complete_check(pEndpoint, 1);
-		}
-
-		payloadLen = HTC_GET_FIELD(HtcHdr, HTC_FRAME_HDR, PAYLOADLEN);
-
-		if (netlen < (payloadLen + HTC_HDR_LENGTH)) {
-#ifdef RX_SG_SUPPORT
-			LOCK_HTC_RX(target);
-			target->IsRxSgInprogress = true;
-			cdf_nbuf_queue_init(&target->RxSgQueue);
-			cdf_nbuf_queue_add(&target->RxSgQueue, netbuf);
-			target->ExpRxSgTotalLen = (payloadLen + HTC_HDR_LENGTH);
-			target->CurRxSgTotalLen += netlen;
-			UNLOCK_HTC_RX(target);
-			netbuf = NULL;
-			break;
-#else
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					("HTC Rx: insufficient length, got:%d expected =%zu\n",
-					 netlen, payloadLen + HTC_HDR_LENGTH));
-			debug_dump_bytes((A_UINT8 *) HtcHdr,
-					 sizeof(HTC_FRAME_HDR),
-					 "BAD RX packet length");
-			status = CDF_STATUS_E_FAILURE;
-			CDF_BUG(0);
-			break;
-#endif
-		}
-#ifdef HTC_EP_STAT_PROFILING
-		LOCK_HTC_RX(target);
-		INC_HTC_EP_STAT(pEndpoint, RxReceived, 1);
-		UNLOCK_HTC_RX(target);
-#endif
-
-		/* if (IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) { */
-		{
-			A_UINT8 temp;
-			A_STATUS temp_status;
-			/* get flags to check for trailer */
-			temp = HTC_GET_FIELD(HtcHdr, HTC_FRAME_HDR, FLAGS);
-			if (temp & HTC_FLAGS_RECV_TRAILER) {
-				/* extract the trailer length */
-				temp =
-					HTC_GET_FIELD(HtcHdr, HTC_FRAME_HDR,
-						      CONTROLBYTES0);
-				if ((temp < sizeof(HTC_RECORD_HDR))
-				    || (temp > payloadLen)) {
-					AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-						("htc_rx_completion_handler, invalid header (payloadlength should be :%d, CB[0] is:%d)\n",
-						payloadLen, temp));
-					status = CDF_STATUS_E_INVAL;
-					break;
-				}
-
-				trailerlen = temp;
-				/* process trailer data that follows HDR + application payload */
-				temp_status = htc_process_trailer(target,
-							     ((A_UINT8 *) HtcHdr +
-							      HTC_HDR_LENGTH +
-							      payloadLen - temp),
-							     temp, htc_ep_id);
-				if (A_FAILED(temp_status)) {
-					status = CDF_STATUS_E_FAILURE;
-					break;
-				}
-
-			}
-		}
-
-		if (((int)payloadLen - (int)trailerlen) <= 0) {
-			/* zero length packet with trailer data, just drop these */
-			break;
-		}
-
-		if (htc_ep_id == ENDPOINT_0) {
-			A_UINT16 message_id;
-			HTC_UNKNOWN_MSG *htc_msg;
-			int wow_nack = 0;
-
-			/* remove HTC header */
-			cdf_nbuf_pull_head(netbuf, HTC_HDR_LENGTH);
-			netdata = cdf_nbuf_data(netbuf);
-			netlen = cdf_nbuf_len(netbuf);
-
-			htc_msg = (HTC_UNKNOWN_MSG *) netdata;
-			message_id =
-				HTC_GET_FIELD(htc_msg, HTC_UNKNOWN_MSG, MESSAGEID);
-
-			switch (message_id) {
-			default:
-				/* handle HTC control message */
-				if (target->CtrlResponseProcessing) {
-					/* this is a fatal error, target should not be sending unsolicited messages
-					 * on the endpoint 0 */
-					AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-							("HTC Rx Ctrl still processing\n"));
-					status = CDF_STATUS_E_FAILURE;
-					CDF_BUG(false);
-					break;
-				}
-
-				LOCK_HTC_RX(target);
-				target->CtrlResponseLength =
-					min((int)netlen,
-					    HTC_MAX_CONTROL_MESSAGE_LENGTH);
-				A_MEMCPY(target->CtrlResponseBuffer, netdata,
-					 target->CtrlResponseLength);
-
-				/* Requester will clear this flag */
-				target->CtrlResponseProcessing = true;
-				UNLOCK_HTC_RX(target);
-
-				cdf_event_set(&target->ctrl_response_valid);
-				break;
-			case HTC_MSG_SEND_SUSPEND_COMPLETE:
-				wow_nack = 0;
-				LOCK_HTC_CREDIT(target);
-				htc_credit_record(HTC_SUSPEND_ACK,
-					pEndpoint->TxCredits,
-					HTC_PACKET_QUEUE_DEPTH(
-						&pEndpoint->TxQueue));
-				UNLOCK_HTC_CREDIT(target);
-				target->HTCInitInfo.
-				TargetSendSuspendComplete((void *)
-							  &wow_nack);
-				break;
-			case HTC_MSG_NACK_SUSPEND:
-				wow_nack = 1;
-				LOCK_HTC_CREDIT(target);
-				htc_credit_record(HTC_SUSPEND_ACK,
-					pEndpoint->TxCredits,
-					HTC_PACKET_QUEUE_DEPTH(
-						&pEndpoint->TxQueue));
-				UNLOCK_HTC_CREDIT(target);
-
-				target->HTCInitInfo.
-				TargetSendSuspendComplete((void *)
-							  &wow_nack);
-				break;
-			}
-
-			cdf_nbuf_free(netbuf);
-			netbuf = NULL;
-			break;
-		}
-
-		/* the current message based HIF architecture allocates net bufs for recv packets
-		 * since this layer bridges that HIF to upper layers , which expects HTC packets,
-		 * we form the packets here
-		 * TODO_FIXME */
-		pPacket = allocate_htc_packet_container(target);
-		if (NULL == pPacket) {
-			status = CDF_STATUS_E_RESOURCES;
-			break;
-		}
-		pPacket->Status = CDF_STATUS_SUCCESS;
-		pPacket->Endpoint = htc_ep_id;
-		pPacket->pPktContext = netbuf;
-		pPacket->pBuffer = cdf_nbuf_data(netbuf) + HTC_HDR_LENGTH;
-		pPacket->ActualLength = netlen - HTC_HEADER_LEN - trailerlen;
-
-		cdf_nbuf_pull_head(netbuf, HTC_HEADER_LEN);
-		cdf_nbuf_set_pktlen(netbuf, pPacket->ActualLength);
-
-		recv_packet_completion(target, pEndpoint, pPacket);
-		/* recover the packet container */
-		free_htc_packet_container(target, pPacket);
-		netbuf = NULL;
-
-	} while (false);
-
-#ifdef RX_SG_SUPPORT
-_out:
-#endif
-
-	if (netbuf != NULL) {
-		cdf_nbuf_free(netbuf);
-	}
-
-	return status;
-
-}
-
-A_STATUS htc_add_receive_pkt_multiple(HTC_HANDLE HTCHandle,
-				      HTC_PACKET_QUEUE *pPktQueue)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint;
-	HTC_PACKET *pFirstPacket;
-	A_STATUS status = A_OK;
-	HTC_PACKET *pPacket;
-
-	pFirstPacket = htc_get_pkt_at_head(pPktQueue);
-
-	if (NULL == pFirstPacket) {
-		A_ASSERT(false);
-		return A_EINVAL;
-	}
-
-	AR_DEBUG_ASSERT(pFirstPacket->Endpoint < ENDPOINT_MAX);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
-			("+- htc_add_receive_pkt_multiple : endPointId: %d, cnt:%d, length: %d\n",
-			 pFirstPacket->Endpoint,
-			 HTC_PACKET_QUEUE_DEPTH(pPktQueue),
-			 pFirstPacket->BufferLength));
-
-	pEndpoint = &target->endpoint[pFirstPacket->Endpoint];
-
-	LOCK_HTC_RX(target);
-
-	do {
-
-		if (HTC_STOPPING(target)) {
-			status = A_ERROR;
-			break;
-		}
-
-		/* store receive packets */
-		HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->RxBufferHoldQueue,
-						  pPktQueue);
-
-	} while (false);
-
-	UNLOCK_HTC_RX(target);
-
-	if (A_FAILED(status)) {
-		/* walk through queue and mark each one canceled */
-		HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue, pPacket) {
-			pPacket->Status = A_ECANCELED;
-		}
-		HTC_PACKET_QUEUE_ITERATE_END;
-
-		do_recv_completion(pEndpoint, pPktQueue);
-	}
-
-	return status;
-}
-
-A_STATUS htc_add_receive_pkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
-{
-	HTC_PACKET_QUEUE queue;
-	INIT_HTC_PACKET_QUEUE_AND_ADD(&queue, pPacket);
-	return htc_add_receive_pkt_multiple(HTCHandle, &queue);
-}
-
-void htc_flush_rx_hold_queue(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint)
-{
-	HTC_PACKET *pPacket;
-	HTC_PACKET_QUEUE container;
-
-	LOCK_HTC_RX(target);
-
-	while (1) {
-		pPacket = htc_packet_dequeue(&pEndpoint->RxBufferHoldQueue);
-		if (NULL == pPacket) {
-			break;
-		}
-		UNLOCK_HTC_RX(target);
-		pPacket->Status = A_ECANCELED;
-		pPacket->ActualLength = 0;
-		AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
-				("  Flushing RX packet:%p, length:%d, ep:%d \n",
-				 pPacket, pPacket->BufferLength,
-				 pPacket->Endpoint));
-		INIT_HTC_PACKET_QUEUE_AND_ADD(&container, pPacket);
-		/* give the packet back */
-		do_recv_completion(pEndpoint, &container);
-		LOCK_HTC_RX(target);
-	}
-
-	UNLOCK_HTC_RX(target);
-}
-
-void htc_recv_init(HTC_TARGET *target)
-{
-	/* Initialize ctrl_response_valid to block */
-	cdf_event_init(&target->ctrl_response_valid);
-}
-
-/* polling routine to wait for a control packet to be received */
-A_STATUS htc_wait_recv_ctrl_message(HTC_TARGET *target)
-{
-/*    int count = HTC_TARGET_MAX_RESPONSE_POLL; */
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCWaitCtrlMessageRecv\n"));
-
-	/* Wait for BMI request/response transaction to complete */
-	if (cdf_wait_single_event(&target->ctrl_response_valid,
-		cdf_system_msecs_to_ticks(HTC_CONTROL_RX_TIMEOUT))) {
-		CDF_BUG(0);
-		return A_ERROR;
-	}
-
-	LOCK_HTC_RX(target);
-	/* caller will clear this flag */
-	target->CtrlResponseProcessing = true;
-
-	UNLOCK_HTC_RX(target);
-
-#if 0
-	while (count > 0) {
-
-		LOCK_HTC_RX(target);
-
-		if (target->CtrlResponseValid) {
-			target->CtrlResponseValid = false;
-			/* caller will clear this flag */
-			target->CtrlResponseProcessing = true;
-			UNLOCK_HTC_RX(target);
-			break;
-		}
-
-		UNLOCK_HTC_RX(target);
-
-		count--;
-		A_MSLEEP(HTC_TARGET_RESPONSE_POLL_MS);
-	}
-
-	if (count <= 0) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-				("-HTCWaitCtrlMessageRecv: Timeout!\n"));
-		return A_ECOMM;
-	}
-#endif
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCWaitCtrlMessageRecv success\n"));
-	return A_OK;
-}
-
-static A_STATUS htc_process_trailer(HTC_TARGET *target,
-				    A_UINT8 *pBuffer,
-				    int Length, HTC_ENDPOINT_ID FromEndpoint)
-{
-	HTC_RECORD_HDR *pRecord;
-	A_UINT8 htc_rec_id;
-	A_UINT8 htc_rec_len;
-	A_UINT8 *pRecordBuf;
-	A_UINT8 *pOrigBuffer;
-	int origLength;
-	A_STATUS status;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
-			("+htc_process_trailer (length:%d) \n", Length));
-
-	if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
-		AR_DEBUG_PRINTBUF(pBuffer, Length, "Recv Trailer");
-	}
-
-	pOrigBuffer = pBuffer;
-	origLength = Length;
-	status = A_OK;
-
-	while (Length > 0) {
-
-		if (Length < sizeof(HTC_RECORD_HDR)) {
-			status = A_EPROTO;
-			break;
-		}
-		/* these are byte aligned structs */
-		pRecord = (HTC_RECORD_HDR *) pBuffer;
-		Length -= sizeof(HTC_RECORD_HDR);
-		pBuffer += sizeof(HTC_RECORD_HDR);
-
-		htc_rec_len = HTC_GET_FIELD(pRecord, HTC_RECORD_HDR, LENGTH);
-		htc_rec_id = HTC_GET_FIELD(pRecord, HTC_RECORD_HDR, RECORDID);
-
-		if (htc_rec_len > Length) {
-			/* no room left in buffer for record */
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					(" invalid record length: %d (id:%d) buffer has: %d bytes left \n",
-					 htc_rec_len, htc_rec_id, Length));
-			status = A_EPROTO;
-			break;
-		}
-		/* start of record follows the header */
-		pRecordBuf = pBuffer;
-
-		switch (htc_rec_id) {
-		case HTC_RECORD_CREDITS:
-			AR_DEBUG_ASSERT(htc_rec_len >=
-					sizeof(HTC_CREDIT_REPORT));
-			htc_process_credit_rpt(target,
-					       (HTC_CREDIT_REPORT *) pRecordBuf,
-					       htc_rec_len /
-					       (sizeof(HTC_CREDIT_REPORT)),
-					       FromEndpoint);
-			break;
-
-#ifdef HIF_SDIO
-		case HTC_RECORD_LOOKAHEAD:
-			/* Process in HIF layer */
-			break;
-
-		case HTC_RECORD_LOOKAHEAD_BUNDLE:
-			/* Process in HIF layer */
-			break;
-#endif /* HIF_SDIO */
-
-		default:
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					(" HTC unhandled record: id:%d length:%d \n",
-					 htc_rec_id, htc_rec_len));
-			break;
-		}
-
-		if (A_FAILED(status)) {
-			break;
-		}
-
-		/* advance buffer past this record for next time around */
-		pBuffer += htc_rec_len;
-		Length -= htc_rec_len;
-	}
-
-	if (A_FAILED(status)) {
-		debug_dump_bytes(pOrigBuffer, origLength, "BAD Recv Trailer");
-	}
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_RECV, ("-htc_process_trailer \n"));
-	return status;
-
-}

core/htc/htc_send.c

@@ -1,2002 +0,0 @@
-/*
- * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include "htc_debug.h"
-#include "htc_internal.h"
-#include <cdf_nbuf.h>           /* cdf_nbuf_t */
-#include <cdf_memory.h>         /* cdf_mem_malloc */
-#include "epping_main.h"
-
-/* #define USB_HIF_SINGLE_PIPE_DATA_SCHED */
-/* #ifdef USB_HIF_SINGLE_PIPE_DATA_SCHED */
-#define DATA_EP_SIZE 4
-/* #endif */
-#define HTC_DATA_RESOURCE_THRS 256
-#define HTC_DATA_MINDESC_PERPACKET 2
-
-typedef enum _HTC_SEND_QUEUE_RESULT {
-	HTC_SEND_QUEUE_OK = 0,  /* packet was queued */
-	HTC_SEND_QUEUE_DROP = 1,        /* this packet should be dropped */
-} HTC_SEND_QUEUE_RESULT;
-
-#ifndef DEBUG_CREDIT
-#define DEBUG_CREDIT 0
-#endif
-
-#if DEBUG_CREDIT
-/* bit mask to enable debug certain endpoint */
-static unsigned ep_debug_mask =
-	(1 << ENDPOINT_0) | (1 << ENDPOINT_1) | (1 << ENDPOINT_2);
-#endif
-
-/* HTC Control Path Credit History */
-A_UINT32 g_htc_credit_history_idx = 0;
-HTC_CREDIT_HISTORY htc_credit_history_buffer[HTC_CREDIT_HISTORY_MAX];
-
-/**
- * htc_credit_record() - records tx que state & credit transactions
- * @type:		type of echange can be HTC_REQUEST_CREDIT
- *			or HTC_PROCESS_CREDIT_REPORT
- * @tx_credits:		current number of tx_credits
- * @htc_tx_queue_depth:	current hct tx queue depth
- *
- * This function records the credits and pending commands whenever a command is
- * sent or credits are returned.  Call this after the credits have been updated
- * according to the transaction.  Call this before dequeing commands.
- *
- * Consider making this function accept an HTC_ENDPOINT and find the current
- * credits and queue depth itself.
- *
- * Consider moving the LOCK_HTC_CREDIT(target); logic into this function as well.
- */
-void htc_credit_record(htc_credit_exchange_type type, uint32_t tx_credit,
-		       uint32_t htc_tx_queue_depth) {
-	if (HTC_CREDIT_HISTORY_MAX <= g_htc_credit_history_idx)
-		g_htc_credit_history_idx = 0;
-
-	htc_credit_history_buffer[g_htc_credit_history_idx].type = type;
-	htc_credit_history_buffer[g_htc_credit_history_idx].time =
-		cdf_get_log_timestamp();
-	htc_credit_history_buffer[g_htc_credit_history_idx].tx_credit =
-		tx_credit;
-	htc_credit_history_buffer[g_htc_credit_history_idx].htc_tx_queue_depth =
-		htc_tx_queue_depth;
-	g_htc_credit_history_idx++;
-
-#ifdef QCA_WIFI_3_0_EMU
-	if (type == HTC_REQUEST_CREDIT)
-		printk("\nrequest_credits-> current_credit %d, pending commands %d\n",
-			tx_credit, htc_tx_queue_depth);
-
-	else if (type == HTC_PROCESS_CREDIT_REPORT)
-		printk("\ncredit_report<- current_credit %d, pending commands %d\n",
-			tx_credit, htc_tx_queue_depth);
-#endif
-}
-
-void htc_dump_counter_info(HTC_HANDLE HTCHandle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-			("\n%s: ce_send_cnt = %d, TX_comp_cnt = %d\n",
-			 __func__, target->ce_send_cnt, target->TX_comp_cnt));
-}
-
-void htc_get_control_endpoint_tx_host_credits(HTC_HANDLE HTCHandle, int *credits)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint;
-	int i;
-
-	if (!credits || !target) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: invalid args", __func__));
-		return;
-	}
-
-	*credits = 0;
-	LOCK_HTC_TX(target);
-	for (i = 0; i < ENDPOINT_MAX; i++) {
-		pEndpoint = &target->endpoint[i];
-		if (pEndpoint->service_id == WMI_CONTROL_SVC) {
-			*credits = pEndpoint->TxCredits;
-			break;
-		}
-	}
-	UNLOCK_HTC_TX(target);
-}
-
-static INLINE void restore_tx_packet(HTC_TARGET *target, HTC_PACKET *pPacket)
-{
-	if (pPacket->PktInfo.AsTx.Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) {
-		cdf_nbuf_t netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-		cdf_nbuf_unmap(target->osdev, netbuf, CDF_DMA_TO_DEVICE);
-		cdf_nbuf_pull_head(netbuf, sizeof(HTC_FRAME_HDR));
-		pPacket->PktInfo.AsTx.Flags &= ~HTC_TX_PACKET_FLAG_FIXUP_NETBUF;
-	}
-
-}
-
-static void do_send_completion(HTC_ENDPOINT *pEndpoint,
-			       HTC_PACKET_QUEUE *pQueueToIndicate)
-{
-	do {
-
-		if (HTC_QUEUE_EMPTY(pQueueToIndicate)) {
-			/* nothing to indicate */
-			break;
-		}
-
-		if (pEndpoint->EpCallBacks.EpTxCompleteMultiple != NULL) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-					(" HTC calling ep %d, send complete multiple callback (%d pkts) \n",
-					 pEndpoint->Id,
-					 HTC_PACKET_QUEUE_DEPTH
-						 (pQueueToIndicate)));
-			/* a multiple send complete handler is being used, pass the queue to the handler */
-			pEndpoint->EpCallBacks.EpTxCompleteMultiple(pEndpoint->
-								    EpCallBacks.
-								    pContext,
-								    pQueueToIndicate);
-			/* all packets are now owned by the callback, reset queue to be safe */
-			INIT_HTC_PACKET_QUEUE(pQueueToIndicate);
-		} else {
-			HTC_PACKET *pPacket;
-			/* using legacy EpTxComplete */
-			do {
-				pPacket = htc_packet_dequeue(pQueueToIndicate);
-				AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-						(" HTC calling ep %d send complete callback on packet %p \n",
-						 pEndpoint->Id, pPacket));
-				pEndpoint->EpCallBacks.EpTxComplete(pEndpoint->
-								    EpCallBacks.
-								    pContext,
-								    pPacket);
-			} while (!HTC_QUEUE_EMPTY(pQueueToIndicate));
-		}
-
-	} while (false);
-
-}
-
-static void send_packet_completion(HTC_TARGET *target, HTC_PACKET *pPacket)
-{
-	HTC_ENDPOINT *pEndpoint = &target->endpoint[pPacket->Endpoint];
-	HTC_PACKET_QUEUE container;
-
-	restore_tx_packet(target, pPacket);
-	INIT_HTC_PACKET_QUEUE_AND_ADD(&container, pPacket);
-
-	/* do completion */
-	do_send_completion(pEndpoint, &container);
-}
-
-void htc_send_complete_check_cleanup(void *context)
-{
-	HTC_ENDPOINT *pEndpoint = (HTC_ENDPOINT *) context;
-	htc_send_complete_check(pEndpoint, 1);
-}
-
-HTC_PACKET *allocate_htc_bundle_packet(HTC_TARGET *target)
-{
-	HTC_PACKET *pPacket;
-	HTC_PACKET_QUEUE *pQueueSave;
-	cdf_nbuf_t netbuf;
-	LOCK_HTC_TX(target);
-	if (NULL == target->pBundleFreeList) {
-		UNLOCK_HTC_TX(target);
-		netbuf = cdf_nbuf_alloc(NULL,
-					target->MaxMsgsPerHTCBundle *
-					target->TargetCreditSize, 0, 4, false);
-		AR_DEBUG_ASSERT(netbuf);
-		if (!netbuf) {
-			return NULL;
-		}
-		pPacket = cdf_mem_malloc(sizeof(HTC_PACKET));
-		AR_DEBUG_ASSERT(pPacket);
-		if (!pPacket) {
-			cdf_nbuf_free(netbuf);
-			return NULL;
-		}
-		pQueueSave = cdf_mem_malloc(sizeof(HTC_PACKET_QUEUE));
-		AR_DEBUG_ASSERT(pQueueSave);
-		if (!pQueueSave) {
-			cdf_nbuf_free(netbuf);
-			cdf_mem_free(pPacket);
-			return NULL;
-		}
-		INIT_HTC_PACKET_QUEUE(pQueueSave);
-		pPacket->pContext = pQueueSave;
-		SET_HTC_PACKET_NET_BUF_CONTEXT(pPacket, netbuf);
-		pPacket->pBuffer = cdf_nbuf_data(netbuf);
-		pPacket->BufferLength = cdf_nbuf_len(netbuf);
-
-		/* store the original head room so that we can restore this when we "free" the packet */
-		/* free packet puts the packet back on the free list */
-		pPacket->netbufOrigHeadRoom = cdf_nbuf_headroom(netbuf);
-		return pPacket;
-	}
-	/* already done malloc - restore from free list */
-	pPacket = target->pBundleFreeList;
-	AR_DEBUG_ASSERT(pPacket);
-	if (!pPacket) {
-		UNLOCK_HTC_TX(target);
-		return NULL;
-	}
-	target->pBundleFreeList = (HTC_PACKET *) pPacket->ListLink.pNext;
-	UNLOCK_HTC_TX(target);
-	pPacket->ListLink.pNext = NULL;
-
-	return pPacket;
-}
-
-void free_htc_bundle_packet(HTC_TARGET *target, HTC_PACKET *pPacket)
-{
-	A_UINT32 curentHeadRoom;
-	cdf_nbuf_t netbuf;
-	HTC_PACKET_QUEUE *pQueueSave;
-
-	netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-	AR_DEBUG_ASSERT(netbuf);
-	if (!netbuf) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("\n%s: Invalid netbuf in HTC "
-						"Packet\n", __func__));
-		return;
-	}
-	/* HIF adds data to the headroom section of the nbuf, restore the original */
-	/* size. If this is not done, headroom keeps shrinking with every HIF send */
-	/* and eventually HIF ends up doing another malloc big enough to store the */
-	/* data + its header */
-
-	curentHeadRoom = cdf_nbuf_headroom(netbuf);
-	cdf_nbuf_pull_head(netbuf,
-			   pPacket->netbufOrigHeadRoom - curentHeadRoom);
-	cdf_nbuf_trim_tail(netbuf, cdf_nbuf_len(netbuf));
-
-	/* restore the pBuffer pointer. HIF changes this */
-	pPacket->pBuffer = cdf_nbuf_data(netbuf);
-	pPacket->BufferLength = cdf_nbuf_len(netbuf);
-
-	/* restore queue */
-	pQueueSave = (HTC_PACKET_QUEUE *) pPacket->pContext;
-	AR_DEBUG_ASSERT(pQueueSave);
-
-	INIT_HTC_PACKET_QUEUE(pQueueSave);
-
-	LOCK_HTC_TX(target);
-	if (target->pBundleFreeList == NULL) {
-		target->pBundleFreeList = pPacket;
-		pPacket->ListLink.pNext = NULL;
-	} else {
-		pPacket->ListLink.pNext = (DL_LIST *) target->pBundleFreeList;
-		target->pBundleFreeList = pPacket;
-	}
-	UNLOCK_HTC_TX(target);
-}
-
-#if defined(HIF_USB) || defined(HIF_SDIO)
-#ifdef ENABLE_BUNDLE_TX
-static A_STATUS htc_send_bundled_netbuf(HTC_TARGET *target,
-					HTC_ENDPOINT *pEndpoint,
-					unsigned char *pBundleBuffer,
-					HTC_PACKET *pPacketTx)
-{
-	cdf_size_t data_len;
-	A_STATUS status;
-	cdf_nbuf_t bundleBuf;
-	uint32_t data_attr = 0;
-
-	bundleBuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacketTx);
-	data_len = pBundleBuffer - cdf_nbuf_data(bundleBuf);
-	cdf_nbuf_put_tail(bundleBuf, data_len);
-	SET_HTC_PACKET_INFO_TX(pPacketTx,
-			       target,
-			       pBundleBuffer,
-			       data_len,
-			       pEndpoint->Id, HTC_TX_PACKET_TAG_BUNDLED);
-	LOCK_HTC_TX(target);
-	HTC_PACKET_ENQUEUE(&pEndpoint->TxLookupQueue, pPacketTx);
-	UNLOCK_HTC_TX(target);
-#if DEBUG_BUNDLE
-	cdf_print(" Send bundle EP%d buffer size:0x%x, total:0x%x, count:%d.\n",
-		  pEndpoint->Id,
-		  pEndpoint->TxCreditSize,
-		  data_len, data_len / pEndpoint->TxCreditSize);
-#endif
-	status = hif_send_head(target->hif_dev,
-			       pEndpoint->UL_PipeID,
-			       pEndpoint->Id, data_len, bundleBuf, data_attr);
-	if (status != A_OK) {
-		cdf_print("%s:hif_send_head failed(len=%d).\n", __FUNCTION__,
-			  data_len);
-	}
-	return status;
-}
-
-static void htc_issue_packets_bundle(HTC_TARGET *target,
-				     HTC_ENDPOINT *pEndpoint,
-				     HTC_PACKET_QUEUE *pPktQueue)
-{
-	int i, frag_count, nbytes;
-	cdf_nbuf_t netbuf, bundleBuf;
-	unsigned char *pBundleBuffer = NULL;
-	HTC_PACKET *pPacket = NULL, *pPacketTx = NULL;
-	HTC_FRAME_HDR *pHtcHdr;
-	int creditPad, creditRemainder, transferLength, bundlesSpaceRemaining =
-		0;
-	HTC_PACKET_QUEUE *pQueueSave = NULL;
-
-	bundlesSpaceRemaining =
-		target->MaxMsgsPerHTCBundle * pEndpoint->TxCreditSize;
-	pPacketTx = allocate_htc_bundle_packet(target);
-	if (!pPacketTx) {
-		/* good time to panic */
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-				("allocate_htc_bundle_packet failed \n"));
-		AR_DEBUG_ASSERT(false);
-		return;
-	}
-	bundleBuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacketTx);
-	pBundleBuffer = cdf_nbuf_data(bundleBuf);
-	pQueueSave = (HTC_PACKET_QUEUE *) pPacketTx->pContext;
-	while (1) {
-		pPacket = htc_packet_dequeue(pPktQueue);
-		if (pPacket == NULL) {
-			break;
-		}
-		creditPad = 0;
-		transferLength = pPacket->ActualLength + HTC_HDR_LENGTH;
-		creditRemainder = transferLength % pEndpoint->TxCreditSize;
-		if (creditRemainder != 0) {
-			if (transferLength < pEndpoint->TxCreditSize) {
-				creditPad =
-					pEndpoint->TxCreditSize - transferLength;
-			} else {
-				creditPad = creditRemainder;
-			}
-			transferLength += creditPad;
-		}
-
-		if (bundlesSpaceRemaining < transferLength) {
-			/* send out previous buffer */
-			htc_send_bundled_netbuf(target, pEndpoint, pBundleBuffer,
-						pPacketTx);
-			if (HTC_PACKET_QUEUE_DEPTH(pPktQueue) <
-			    HTC_MIN_MSG_PER_BUNDLE) {
-				return;
-			}
-			bundlesSpaceRemaining =
-				target->MaxMsgsPerHTCBundle *
-				pEndpoint->TxCreditSize;
-			pPacketTx = allocate_htc_bundle_packet(target);
-			if (!pPacketTx) {
-				/* good time to panic */
-				AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-						("allocate_htc_bundle_packet failed \n"));
-				AR_DEBUG_ASSERT(false);
-				return;
-			}
-			bundleBuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacketTx);
-			pBundleBuffer = cdf_nbuf_data(bundleBuf);
-			pQueueSave = (HTC_PACKET_QUEUE *) pPacketTx->pContext;
-		}
-
-		bundlesSpaceRemaining -= transferLength;
-		netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-		pHtcHdr = (HTC_FRAME_HDR *) cdf_nbuf_get_frag_vaddr(netbuf, 0);
-		HTC_WRITE32(pHtcHdr,
-			    SM(pPacket->ActualLength,
-			       HTC_FRAME_HDR_PAYLOADLEN) | SM(pPacket->PktInfo.
-							      AsTx.
-							      SendFlags |
-							      HTC_FLAGS_SEND_BUNDLE,
-							      HTC_FRAME_HDR_FLAGS)
-			    | SM(pPacket->Endpoint, HTC_FRAME_HDR_ENDPOINTID));
-		HTC_WRITE32((A_UINT32 *) pHtcHdr + 1,
-			    SM(pPacket->PktInfo.AsTx.SeqNo,
-			       HTC_FRAME_HDR_CONTROLBYTES1) | SM(creditPad,
-								 HTC_FRAME_HDR_RESERVED));
-		pHtcHdr->reserved = creditPad;
-		frag_count = cdf_nbuf_get_num_frags(netbuf);
-		nbytes = pPacket->ActualLength + HTC_HDR_LENGTH;
-		for (i = 0; i < frag_count && nbytes > 0; i++) {
-			int frag_len = cdf_nbuf_get_frag_len(netbuf, i);
-			unsigned char *frag_addr =
-				cdf_nbuf_get_frag_vaddr(netbuf, i);
-			if (frag_len > nbytes) {
-				frag_len = nbytes;
-			}
-			A_MEMCPY(pBundleBuffer, frag_addr, frag_len);
-			nbytes -= frag_len;
-			pBundleBuffer += frag_len;
-		}
-		HTC_PACKET_ENQUEUE(pQueueSave, pPacket);
-		pBundleBuffer += creditPad;
-	}
-	if (pBundleBuffer != cdf_nbuf_data(bundleBuf)) {
-		/* send out remaining buffer */
-		htc_send_bundled_netbuf(target, pEndpoint, pBundleBuffer,
-					pPacketTx);
-	} else {
-		free_htc_bundle_packet(target, pPacketTx);
-	}
-}
-#endif /* ENABLE_BUNDLE_TX */
-#endif
-
-static A_STATUS htc_issue_packets(HTC_TARGET *target,
-				  HTC_ENDPOINT *pEndpoint,
-				  HTC_PACKET_QUEUE *pPktQueue)
-{
-	A_STATUS status = A_OK;
-	cdf_nbuf_t netbuf;
-	HTC_PACKET *pPacket = NULL;
-	uint16_t payloadLen;
-	HTC_FRAME_HDR *pHtcHdr;
-	uint32_t data_attr = 0;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("+htc_issue_packets: Queue: %p, Pkts %d \n", pPktQueue,
-			 HTC_PACKET_QUEUE_DEPTH(pPktQueue)));
-	while (true) {
-#if defined(HIF_USB) || defined(HIF_SDIO)
-#ifdef ENABLE_BUNDLE_TX
-		if (IS_TX_CREDIT_FLOW_ENABLED(pEndpoint) &&
-		    HTC_ENABLE_BUNDLE(target) &&
-		    HTC_PACKET_QUEUE_DEPTH(pPktQueue) >=
-		    HTC_MIN_MSG_PER_BUNDLE) {
-			htc_issue_packets_bundle(target, pEndpoint, pPktQueue);
-		}
-#endif
-#endif
-		/* if not bundling or there was a packet that could not be placed in a bundle,
-		 * and send it by normal way
-		 */
-		pPacket = htc_packet_dequeue(pPktQueue);
-		if (NULL == pPacket) {
-			/* local queue is fully drained */
-			break;
-		}
-
-		netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-		AR_DEBUG_ASSERT(netbuf);
-		/* Non-credit enabled endpoints have been mapped and setup by now,
-		 * so no need to revisit the HTC headers
-		 */
-		if (IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) {
-
-			payloadLen = pPacket->ActualLength;
-			/* setup HTC frame header */
-
-			pHtcHdr =
-				(HTC_FRAME_HDR *) cdf_nbuf_get_frag_vaddr(netbuf,
-									  0);
-			AR_DEBUG_ASSERT(pHtcHdr);
-
-			HTC_WRITE32(pHtcHdr,
-				    SM(payloadLen,
-				       HTC_FRAME_HDR_PAYLOADLEN) | SM(pPacket->
-								      PktInfo.
-								      AsTx.
-								      SendFlags,
-								      HTC_FRAME_HDR_FLAGS)
-				    | SM(pPacket->Endpoint,
-					 HTC_FRAME_HDR_ENDPOINTID));
-			HTC_WRITE32(((A_UINT32 *) pHtcHdr) + 1,
-				    SM(pPacket->PktInfo.AsTx.SeqNo,
-				       HTC_FRAME_HDR_CONTROLBYTES1));
-
-			/*
-			 * Now that the HTC frame header has been added, the netbuf can be
-			 * mapped.  This only applies to non-data frames, since data frames
-			 * were already mapped as they entered into the driver.
-			 * Check the "FIXUP_NETBUF" flag to see whether this is a data netbuf
-			 * that is already mapped, or a non-data netbuf that needs to be
-			 * mapped.
-			 */
-			if (pPacket->PktInfo.AsTx.
-			    Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) {
-				cdf_nbuf_map(target->osdev,
-					     GET_HTC_PACKET_NET_BUF_CONTEXT
-						     (pPacket), CDF_DMA_TO_DEVICE);
-			}
-		}
-		LOCK_HTC_TX(target);
-		/* store in look up queue to match completions */
-		HTC_PACKET_ENQUEUE(&pEndpoint->TxLookupQueue, pPacket);
-		INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
-		pEndpoint->ul_outstanding_cnt++;
-		UNLOCK_HTC_TX(target);
-
-		hif_send_complete_check(target->hif_dev, pEndpoint->UL_PipeID, false);
-		status = hif_send_head(target->hif_dev,
-				       pEndpoint->UL_PipeID, pEndpoint->Id,
-				       HTC_HDR_LENGTH + pPacket->ActualLength,
-				       netbuf, data_attr);
-#if DEBUG_BUNDLE
-		cdf_print(" Send single EP%d buffer size:0x%x, total:0x%x.\n",
-			  pEndpoint->Id,
-			  pEndpoint->TxCreditSize,
-			  HTC_HDR_LENGTH + pPacket->ActualLength);
-#endif
-
-		target->ce_send_cnt++;
-
-		if (cdf_unlikely(A_FAILED(status))) {
-			if (status != A_NO_RESOURCE) {
-				/* TODO : if more than 1 endpoint maps to the same PipeID it is possible
-				 * to run out of resources in the HIF layer. Don't emit the error */
-				AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-						("hif_send Failed status:%d \n",
-						 status));
-			}
-			LOCK_HTC_TX(target);
-			target->ce_send_cnt--;
-			pEndpoint->ul_outstanding_cnt--;
-			HTC_PACKET_REMOVE(&pEndpoint->TxLookupQueue, pPacket);
-			/* reclaim credits */
-#if defined(HIF_USB)
-			if (pEndpoint->Id >= ENDPOINT_2
-			    && pEndpoint->Id <= ENDPOINT_5)
-				target->avail_tx_credits +=
-					pPacket->PktInfo.AsTx.CreditsUsed;
-			else
-				pEndpoint->TxCredits +=
-					pPacket->PktInfo.AsTx.CreditsUsed;
-#else
-			pEndpoint->TxCredits +=
-				pPacket->PktInfo.AsTx.CreditsUsed;
-#endif
-			/* put it back into the callers queue */
-			HTC_PACKET_ENQUEUE_TO_HEAD(pPktQueue, pPacket);
-			UNLOCK_HTC_TX(target);
-			break;
-		}
-
-		/*
-		 * For HTT messages without a response from fw,
-		 *   do the runtime put here.
-		 * otherwise runtime put will be done when the fw response comes
-		 */
-		if (pPacket->PktInfo.AsTx.Tag == HTC_TX_PACKET_TAG_RUNTIME_PUT)
-			hif_pm_runtime_put(target->hif_dev);
-	}
-	if (cdf_unlikely(A_FAILED(status))) {
-#if defined(HIF_USB)
-		if (pEndpoint->Id >= ENDPOINT_2 && pEndpoint->Id <= ENDPOINT_5)
-			target->avail_tx_credits +=
-				pPacket->PktInfo.AsTx.CreditsUsed;
-		else
-			pEndpoint->TxCredits +=
-				pPacket->PktInfo.AsTx.CreditsUsed;
-#endif
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-			("htc_issue_packets, failed pkt:0x%p status:%d",
-			 pPacket, status));
-	}
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-htc_issue_packets \n"));
-
-	return status;
-}
-
-#ifdef FEATURE_RUNTIME_PM
-/**
- * extract_htc_pm_packtes(): move pm packets from endpoint into queue
- * @endpoint: which enpoint to extract packets from
- * @queue: a queue to store extracted packets in.
- *
- * remove pm packets from the endpoint's tx queue.
- * queue them into a queue
- */
-static void extract_htc_pm_packets(HTC_ENDPOINT *endpoint,
-				HTC_PACKET_QUEUE *queue)
-{
-	HTC_PACKET *packet;
-
-	/* only WMI endpoint has power management packets */
-	if (endpoint->service_id != WMI_CONTROL_SVC)
-		return;
-
-	ITERATE_OVER_LIST_ALLOW_REMOVE(&endpoint->TxQueue.QueueHead, packet,
-			HTC_PACKET, ListLink) {
-		if (packet->PktInfo.AsTx.Tag == HTC_TX_PACKET_TAG_AUTO_PM) {
-			HTC_PACKET_REMOVE(&endpoint->TxQueue, packet);
-			HTC_PACKET_ENQUEUE(queue, packet);
-		}
-	} ITERATE_END
-}
-
-/**
- * queue_htc_pm_packets(): queue pm packets with priority
- * @endpoint: enpoint to queue packets to
- * @queue: queue of pm packets to enque
- *
- * suspend resume packets get special treatment & priority.
- * need to queue them at the front of the queue.
- */
-static void queue_htc_pm_packets(HTC_ENDPOINT *endpoint,
-				 HTC_PACKET_QUEUE *queue)
-{
-	if (endpoint->service_id != WMI_CONTROL_SVC)
-		return;
-
-	HTC_PACKET_QUEUE_TRANSFER_TO_HEAD(&endpoint->TxQueue, queue);
-}
-#else
-static void extract_htc_pm_packets(HTC_ENDPOINT *endpoint,
-		HTC_PACKET_QUEUE *queue)
-{}
-
-static void queue_htc_pm_packets(HTC_ENDPOINT *endpoint,
-		HTC_PACKET_QUEUE *queue)
-{}
-#endif
-
-
-/* get HTC send packets from the TX queue on an endpoint, based on available credits */
-void get_htc_send_packets_credit_based(HTC_TARGET *target,
-				       HTC_ENDPOINT *pEndpoint,
-				       HTC_PACKET_QUEUE *pQueue)
-{
-	int creditsRequired;
-	int remainder;
-	A_UINT8 sendFlags;
-	HTC_PACKET *pPacket;
-	unsigned int transferLength;
-	HTC_PACKET_QUEUE *tx_queue;
-	HTC_PACKET_QUEUE pm_queue;
-	bool do_pm_get = false;
-
-	/****** NOTE : the TX lock is held when this function is called *****************/
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+get_htc_send_packets_credit_based\n"));
-
-	INIT_HTC_PACKET_QUEUE(&pm_queue);
-	extract_htc_pm_packets(pEndpoint, &pm_queue);
-	if (HTC_QUEUE_EMPTY(&pm_queue)) {
-		tx_queue = &pEndpoint->TxQueue;
-		do_pm_get = true;
-	} else {
-		tx_queue = &pm_queue;
-	}
-
-	/* loop until we can grab as many packets out of the queue as we can */
-	while (true) {
-		if (do_pm_get && hif_pm_runtime_get(target->hif_dev)) {
-			/* bus suspended, runtime resume issued */
-			CDF_ASSERT(HTC_PACKET_QUEUE_DEPTH(pQueue) == 0);
-			break;
-		}
-
-		sendFlags = 0;
-		/* get packet at head, but don't remove it */
-		pPacket = htc_get_pkt_at_head(tx_queue);
-		if (pPacket == NULL) {
-			if (do_pm_get)
-				hif_pm_runtime_put(target->hif_dev);
-			break;
-		}
-
-		AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-				(" Got head packet:%p , Queue Depth: %d\n",
-				 pPacket,
-				 HTC_PACKET_QUEUE_DEPTH(tx_queue)));
-
-		transferLength = pPacket->ActualLength + HTC_HDR_LENGTH;
-
-		if (transferLength <= pEndpoint->TxCreditSize) {
-			creditsRequired = 1;
-		} else {
-			/* figure out how many credits this message requires */
-			creditsRequired =
-				transferLength / pEndpoint->TxCreditSize;
-			remainder = transferLength % pEndpoint->TxCreditSize;
-
-			if (remainder) {
-				creditsRequired++;
-			}
-		}
-
-		AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-				(" Credits Required:%d   Got:%d\n",
-				 creditsRequired, pEndpoint->TxCredits));
-
-		if (pEndpoint->Id == ENDPOINT_0) {
-			/* endpoint 0 is special, it always has a credit and does not require credit based
-			 * flow control */
-			creditsRequired = 0;
-#if defined(HIF_USB)
-		} else if (pEndpoint->Id >= ENDPOINT_2
-			   && pEndpoint->Id <= ENDPOINT_5) {
-			if (target->avail_tx_credits < creditsRequired)
-				break;
-
-			target->avail_tx_credits -= creditsRequired;
-
-			if (target->avail_tx_credits < 9) {
-				/* tell the target we need credits ASAP! */
-				sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
-				INC_HTC_EP_STAT(pEndpoint,
-						TxCreditLowIndications, 1);
-				AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-						(" Host Needs Credits  \n"));
-			}
-#endif
-		} else {
-
-			if (pEndpoint->TxCredits < creditsRequired) {
-#if DEBUG_CREDIT
-				AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-						(" EP%d, No Credit now. %d < %d\n",
-						 pEndpoint->Id,
-						 pEndpoint->TxCredits,
-						 creditsRequired));
-#endif
-				if (do_pm_get)
-					hif_pm_runtime_put(target->hif_dev);
-				break;
-			}
-
-			pEndpoint->TxCredits -= creditsRequired;
-			INC_HTC_EP_STAT(pEndpoint, TxCreditsConsummed,
-					creditsRequired);
-
-			/* check if we need credits back from the target */
-			if (pEndpoint->TxCredits <=
-			    pEndpoint->TxCreditsPerMaxMsg) {
-				/* tell the target we need credits ASAP! */
-				sendFlags |= HTC_FLAGS_NEED_CREDIT_UPDATE;
-
-				if (pEndpoint->service_id == WMI_CONTROL_SVC) {
-					LOCK_HTC_CREDIT(target);
-					htc_credit_record(HTC_REQUEST_CREDIT,
-							  pEndpoint->TxCredits,
-							  HTC_PACKET_QUEUE_DEPTH
-								  (tx_queue));
-					UNLOCK_HTC_CREDIT(target);
-				}
-
-				INC_HTC_EP_STAT(pEndpoint,
-						TxCreditLowIndications, 1);
-#if DEBUG_CREDIT
-				AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-						(" EP%d Needs Credits\n",
-						 pEndpoint->Id));
-#endif
-			}
-		}
-
-		/* now we can fully dequeue */
-		pPacket = htc_packet_dequeue(tx_queue);
-		if (pPacket) {
-			/* save the number of credits this packet consumed */
-			pPacket->PktInfo.AsTx.CreditsUsed = creditsRequired;
-			/* save send flags */
-			pPacket->PktInfo.AsTx.SendFlags = sendFlags;
-
-			/* queue this packet into the caller's queue */
-			HTC_PACKET_ENQUEUE(pQueue, pPacket);
-		}
-	}
-
-	if (!HTC_QUEUE_EMPTY(&pm_queue))
-		queue_htc_pm_packets(pEndpoint, &pm_queue);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("-get_htc_send_packets_credit_based\n"));
-
-}
-
-void get_htc_send_packets(HTC_TARGET *target,
-			  HTC_ENDPOINT *pEndpoint,
-			  HTC_PACKET_QUEUE *pQueue, int Resources)
-{
-
-	HTC_PACKET *pPacket;
-	HTC_PACKET_QUEUE *tx_queue;
-	HTC_PACKET_QUEUE pm_queue;
-	bool do_pm_get;
-
-	/****** NOTE : the TX lock is held when this function is called *****************/
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("+get_htc_send_packets %d resources\n", Resources));
-
-	INIT_HTC_PACKET_QUEUE(&pm_queue);
-	extract_htc_pm_packets(pEndpoint, &pm_queue);
-	if (HTC_QUEUE_EMPTY(&pm_queue)) {
-		tx_queue = &pEndpoint->TxQueue;
-		do_pm_get = true;
-	} else {
-		tx_queue = &pm_queue;
-	}
-
-	/* loop until we can grab as many packets out of the queue as we can */
-	while (Resources > 0) {
-		int num_frags;
-
-		if (do_pm_get && hif_pm_runtime_get(target->hif_dev)) {
-			/* bus suspended, runtime resume issued */
-			CDF_ASSERT(HTC_PACKET_QUEUE_DEPTH(pQueue) == 0);
-			break;
-		}
-
-		pPacket = htc_packet_dequeue(tx_queue);
-		if (pPacket == NULL) {
-			if (do_pm_get)
-				hif_pm_runtime_put(target->hif_dev);
-			break;
-		}
-		AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-				(" Got packet:%p , New Queue Depth: %d\n",
-				 pPacket,
-				 HTC_PACKET_QUEUE_DEPTH(tx_queue)));
-		/* For non-credit path the sequence number is already embedded
-		 * in the constructed HTC header
-		 */
-#if 0
-		pPacket->PktInfo.AsTx.SeqNo = pEndpoint->SeqNo;
-		pEndpoint->SeqNo++;
-#endif
-		pPacket->PktInfo.AsTx.SendFlags = 0;
-		pPacket->PktInfo.AsTx.CreditsUsed = 0;
-		/* queue this packet into the caller's queue */
-		HTC_PACKET_ENQUEUE(pQueue, pPacket);
-
-		/*
-		 * FIX THIS:
-		 * For now, avoid calling cdf_nbuf_get_num_frags before calling
-		 * cdf_nbuf_map, because the MacOS version of cdf_nbuf_t doesn't
-		 * support cdf_nbuf_get_num_frags until after cdf_nbuf_map has
-		 * been done.
-		 * Assume that the non-data netbufs, i.e. the WMI message netbufs,
-		 * consist of a single fragment.
-		 */
-		num_frags =
-			(pPacket->PktInfo.AsTx.
-			 Flags & HTC_TX_PACKET_FLAG_FIXUP_NETBUF) ? 1
-		        /* WMI messages are in a single-fragment network buffer */ :
-			cdf_nbuf_get_num_frags(GET_HTC_PACKET_NET_BUF_CONTEXT
-						       (pPacket));
-		Resources -= num_frags;
-	}
-
-	if (!HTC_QUEUE_EMPTY(&pm_queue))
-		queue_htc_pm_packets(pEndpoint, &pm_queue);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-get_htc_send_packets\n"));
-
-}
-
-static HTC_SEND_QUEUE_RESULT htc_try_send(HTC_TARGET *target,
-					  HTC_ENDPOINT *pEndpoint,
-					  HTC_PACKET_QUEUE *pCallersSendQueue)
-{
-	HTC_PACKET_QUEUE sendQueue;     /* temp queue to hold packets at various stages */
-	HTC_PACKET *pPacket;
-	int tx_resources;
-	int overflow;
-	HTC_SEND_QUEUE_RESULT result = HTC_SEND_QUEUE_OK;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("+htc_try_send (Queue:%p Depth:%d)\n",
-					 pCallersSendQueue,
-					 (pCallersSendQueue ==
-					  NULL) ? 0 :
-					 HTC_PACKET_QUEUE_DEPTH
-						 (pCallersSendQueue)));
-
-	/* init the local send queue */
-	INIT_HTC_PACKET_QUEUE(&sendQueue);
-
-	do {
-
-		if (NULL == pCallersSendQueue) {
-			/* caller didn't provide a queue, just wants us to check queues and send */
-			break;
-		}
-
-		if (HTC_QUEUE_EMPTY(pCallersSendQueue)) {
-			/* empty queue */
-			OL_ATH_HTC_PKT_ERROR_COUNT_INCR(target,
-							HTC_PKT_Q_EMPTY);
-			result = HTC_SEND_QUEUE_DROP;
-			break;
-		}
-
-		if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) >=
-		    pEndpoint->MaxTxQueueDepth) {
-			/* we've already overflowed */
-			overflow = HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue);
-		} else {
-			/* figure out how much we will overflow by */
-			overflow = HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
-			overflow += HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue);
-			/* figure out how much we will overflow the TX queue by */
-			overflow -= pEndpoint->MaxTxQueueDepth;
-		}
-
-		/* if overflow is negative or zero, we are okay */
-		if (overflow > 0) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-					(" Endpoint %d, TX queue will overflow :%d , Tx Depth:%d, Max:%d \n",
-					 pEndpoint->Id, overflow,
-					 HTC_PACKET_QUEUE_DEPTH(&pEndpoint->
-								TxQueue),
-					 pEndpoint->MaxTxQueueDepth));
-		}
-		if ((overflow <= 0)
-		    || (pEndpoint->EpCallBacks.EpSendFull == NULL)) {
-			/* all packets will fit or caller did not provide send full indication handler
-			 * --  just move all of them to the local sendQueue object */
-			HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&sendQueue,
-							  pCallersSendQueue);
-		} else {
-			int i;
-			int goodPkts =
-				HTC_PACKET_QUEUE_DEPTH(pCallersSendQueue) -
-				overflow;
-
-			A_ASSERT(goodPkts >= 0);
-			/* we have overflowed, and a callback is provided */
-			/* dequeue all non-overflow packets into the sendqueue */
-			for (i = 0; i < goodPkts; i++) {
-				/* pop off caller's queue */
-				pPacket = htc_packet_dequeue(pCallersSendQueue);
-				A_ASSERT(pPacket != NULL);
-				/* insert into local queue */
-				HTC_PACKET_ENQUEUE(&sendQueue, pPacket);
-			}
-
-			/* the caller's queue has all the packets that won't fit */
-			/* walk through the caller's queue and indicate each one to the send full handler */
-			ITERATE_OVER_LIST_ALLOW_REMOVE(&pCallersSendQueue->
-						       QueueHead, pPacket,
-						       HTC_PACKET, ListLink) {
-
-				AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-						(" Indicating overflowed TX packet: %p \n",
-						 pPacket));
-				/*
-				 * Remove headroom reserved for HTC_FRAME_HDR before giving
-				 * the packet back to the user via the EpSendFull callback.
-				 */
-				restore_tx_packet(target, pPacket);
-
-				if (pEndpoint->EpCallBacks.
-				    EpSendFull(pEndpoint->EpCallBacks.pContext,
-					       pPacket) == HTC_SEND_FULL_DROP) {
-					/* callback wants the packet dropped */
-					INC_HTC_EP_STAT(pEndpoint, TxDropped,
-							1);
-					/* leave this one in the caller's queue for cleanup */
-				} else {
-					/* callback wants to keep this packet, remove from caller's queue */
-					HTC_PACKET_REMOVE(pCallersSendQueue,
-							  pPacket);
-					/* put it in the send queue */
-					/* add HTC_FRAME_HDR space reservation again */
-					cdf_nbuf_push_head
-						(GET_HTC_PACKET_NET_BUF_CONTEXT
-							(pPacket), sizeof(HTC_FRAME_HDR));
-
-					HTC_PACKET_ENQUEUE(&sendQueue, pPacket);
-				}
-
-			}
-			ITERATE_END;
-
-			if (HTC_QUEUE_EMPTY(&sendQueue)) {
-				/* no packets made it in, caller will cleanup */
-				OL_ATH_HTC_PKT_ERROR_COUNT_INCR(target,
-								HTC_SEND_Q_EMPTY);
-				result = HTC_SEND_QUEUE_DROP;
-				break;
-			}
-		}
-
-	} while (false);
-
-	if (result != HTC_SEND_QUEUE_OK) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-htc_try_send:  \n"));
-		return result;
-	}
-
-	if (!IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) {
-		tx_resources =
-			hif_get_free_queue_number(target->hif_dev,
-						  pEndpoint->UL_PipeID);
-	} else {
-		tx_resources = 0;
-	}
-
-	LOCK_HTC_TX(target);
-
-	if (!HTC_QUEUE_EMPTY(&sendQueue)) {
-		/* transfer packets to tail */
-		HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&pEndpoint->TxQueue,
-						  &sendQueue);
-		A_ASSERT(HTC_QUEUE_EMPTY(&sendQueue));
-		INIT_HTC_PACKET_QUEUE(&sendQueue);
-	}
-
-	/* increment tx processing count on entry */
-	cdf_atomic_inc(&pEndpoint->TxProcessCount);
-	if (cdf_atomic_read(&pEndpoint->TxProcessCount) > 1) {
-		/* another thread or task is draining the TX queues on this endpoint
-		 * that thread will reset the tx processing count when the queue is drained */
-		cdf_atomic_dec(&pEndpoint->TxProcessCount);
-		UNLOCK_HTC_TX(target);
-		AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-htc_try_send (busy) \n"));
-		return HTC_SEND_QUEUE_OK;
-	}
-
-	/***** beyond this point only 1 thread may enter ******/
-
-	/* now drain the endpoint TX queue for transmission as long as we have enough
-	 * transmit resources */
-	while (true) {
-
-		if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue) == 0) {
-			break;
-		}
-
-		if (IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) {
-#if DEBUG_CREDIT
-			int cred = pEndpoint->TxCredits;
-#endif
-			/* credit based mechanism provides flow control based on target transmit resource availability, we
-			 * assume that the HIF layer will always have bus resources greater than target transmit resources */
-			get_htc_send_packets_credit_based(target, pEndpoint,
-							  &sendQueue);
-#if DEBUG_CREDIT
-			if (ep_debug_mask & (1 << pEndpoint->Id)) {
-				if (cred - pEndpoint->TxCredits > 0) {
-					AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-							(" <HTC> Decrease EP%d %d - %d = %d credits.\n",
-							 pEndpoint->Id, cred,
-							 cred -
-							 pEndpoint->TxCredits,
-							 pEndpoint->TxCredits));
-				}
-			}
-#endif
-		} else {
-			/* get all the packets for this endpoint that we can for this pass */
-			get_htc_send_packets(target, pEndpoint, &sendQueue,
-					     tx_resources);
-		}
-
-		if (HTC_PACKET_QUEUE_DEPTH(&sendQueue) == 0) {
-			/* didn't get any packets due to a lack of resources or TX queue was drained */
-			break;
-		}
-
-		UNLOCK_HTC_TX(target);
-
-		/* send what we can */
-		result = htc_issue_packets(target, pEndpoint, &sendQueue);
-		if (result) {
-			int i;
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-				("htc_issue_packets, failed status:%d put it back to head of callersSendQueue",
-				 result));
-
-			for (i = HTC_PACKET_QUEUE_DEPTH(&sendQueue); i > 0; i--)
-				hif_pm_runtime_put(target->hif_dev);
-
-			HTC_PACKET_QUEUE_TRANSFER_TO_HEAD(&pEndpoint->TxQueue,
-							  &sendQueue);
-			LOCK_HTC_TX(target);
-			break;
-		}
-
-		if (!IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) {
-			tx_resources =
-				hif_get_free_queue_number(target->hif_dev,
-							  pEndpoint->UL_PipeID);
-		}
-
-		LOCK_HTC_TX(target);
-
-	}
-
-	UNLOCK_HTC_TX(target);
-	/* done with this endpoint, we can clear the count */
-	cdf_atomic_init(&pEndpoint->TxProcessCount);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-htc_try_send:  \n"));
-
-	return HTC_SEND_QUEUE_OK;
-}
-
-#ifdef USB_HIF_SINGLE_PIPE_DATA_SCHED
-static A_UINT16 htc_send_pkts_sched_check(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID id)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint;
-	HTC_ENDPOINT_ID eid;
-	HTC_PACKET_QUEUE *pTxQueue;
-	A_UINT16 resources;
-	A_UINT16 acQueueStatus[DATA_EP_SIZE] = { 0, 0, 0, 0 };
-
-	if (id < ENDPOINT_2 || id > ENDPOINT_5) {
-		return 1;
-	}
-
-	for (eid = ENDPOINT_2; eid <= ENDPOINT_5; eid++) {
-		pEndpoint = &target->endpoint[eid];
-		pTxQueue = &pEndpoint->TxQueue;
-
-		if (HTC_QUEUE_EMPTY(pTxQueue)) {
-			acQueueStatus[eid - 2] = 1;
-		}
-	}
-
-	switch (id) {
-	case ENDPOINT_2:        /* BE */
-		return (acQueueStatus[0] && acQueueStatus[2]
-			&& acQueueStatus[3]);
-	case ENDPOINT_3:        /* BK */
-		return (acQueueStatus[0] && acQueueStatus[1] && acQueueStatus[2]
-			&& acQueueStatus[3]);
-	case ENDPOINT_4:        /* VI */
-		return (acQueueStatus[2] && acQueueStatus[3]);
-	case ENDPOINT_5:        /* VO */
-		return (acQueueStatus[3]);
-	default:
-		return 0;
-	}
-
-}
-
-static A_STATUS htc_send_pkts_sched_queue(HTC_TARGET *target,
-					  HTC_PACKET_QUEUE *pPktQueue,
-					  HTC_ENDPOINT_ID eid)
-{
-	HTC_ENDPOINT *pEndpoint;
-	HTC_PACKET_QUEUE *pTxQueue;
-	HTC_PACKET *pPacket;
-	int goodPkts;
-
-	pEndpoint = &target->endpoint[eid];
-	pTxQueue = &pEndpoint->TxQueue;
-
-	LOCK_HTC_TX(target);
-
-	goodPkts =
-		pEndpoint->MaxTxQueueDepth -
-		HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue);
-
-	if (goodPkts > 0) {
-		while (!HTC_QUEUE_EMPTY(pPktQueue)) {
-			pPacket = htc_packet_dequeue(pPktQueue);
-			HTC_PACKET_ENQUEUE(pTxQueue, pPacket);
-			goodPkts--;
-
-			if (goodPkts <= 0) {
-				break;
-			}
-		}
-	}
-
-	if (HTC_PACKET_QUEUE_DEPTH(pPktQueue)) {
-		ITERATE_OVER_LIST_ALLOW_REMOVE(&pPktQueue->QueueHead, pPacket,
-					       HTC_PACKET, ListLink) {
-
-			if (pEndpoint->EpCallBacks.
-			    EpSendFull(pEndpoint->EpCallBacks.pContext,
-				       pPacket) == HTC_SEND_FULL_DROP) {
-				INC_HTC_EP_STAT(pEndpoint, TxDropped, 1);
-			} else {
-				HTC_PACKET_REMOVE(pPktQueue, pPacket);
-				HTC_PACKET_ENQUEUE(pTxQueue, pPacket);
-			}
-		}
-		ITERATE_END;
-	}
-
-	UNLOCK_HTC_TX(target);
-
-	return A_OK;
-}
-
-#endif
-
-A_STATUS htc_send_pkts_multiple(HTC_HANDLE HTCHandle, HTC_PACKET_QUEUE *pPktQueue)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint;
-	HTC_PACKET *pPacket;
-	cdf_nbuf_t netbuf;
-	HTC_FRAME_HDR *pHtcHdr;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("+htc_send_pkts_multiple: Queue: %p, Pkts %d \n",
-			 pPktQueue, HTC_PACKET_QUEUE_DEPTH(pPktQueue)));
-
-	/* get packet at head to figure out which endpoint these packets will go into */
-	pPacket = htc_get_pkt_at_head(pPktQueue);
-	if (NULL == pPacket) {
-		OL_ATH_HTC_PKT_ERROR_COUNT_INCR(target, GET_HTC_PKT_Q_FAIL);
-		AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-htc_send_pkts_multiple \n"));
-		return A_EINVAL;
-	}
-
-	AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
-	pEndpoint = &target->endpoint[pPacket->Endpoint];
-
-	if (!pEndpoint->service_id) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("%s service_id is invalid\n",
-								__func__));
-		return A_EINVAL;
-	}
-
-#ifdef HTC_EP_STAT_PROFILING
-	LOCK_HTC_TX(target);
-	INC_HTC_EP_STAT(pEndpoint, TxPosted, HTC_PACKET_QUEUE_DEPTH(pPktQueue));
-	UNLOCK_HTC_TX(target);
-#endif
-
-	/* provide room in each packet's netbuf for the HTC frame header */
-	HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue, pPacket) {
-		netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-		AR_DEBUG_ASSERT(netbuf);
-
-		cdf_nbuf_push_head(netbuf, sizeof(HTC_FRAME_HDR));
-		/* setup HTC frame header */
-		pHtcHdr = (HTC_FRAME_HDR *) cdf_nbuf_get_frag_vaddr(netbuf, 0);
-		AR_DEBUG_ASSERT(pHtcHdr);
-		HTC_WRITE32(pHtcHdr,
-			    SM(pPacket->ActualLength,
-			       HTC_FRAME_HDR_PAYLOADLEN) | SM(pPacket->Endpoint,
-							      HTC_FRAME_HDR_ENDPOINTID));
-
-		LOCK_HTC_TX(target);
-
-		pPacket->PktInfo.AsTx.SeqNo = pEndpoint->SeqNo;
-		pEndpoint->SeqNo++;
-
-		HTC_WRITE32(((A_UINT32 *) pHtcHdr) + 1,
-			    SM(pPacket->PktInfo.AsTx.SeqNo,
-			       HTC_FRAME_HDR_CONTROLBYTES1));
-
-		UNLOCK_HTC_TX(target);
-		/*
-		 * Now that the HTC frame header has been added, the netbuf can be
-		 * mapped.  This only applies to non-data frames, since data frames
-		 * were already mapped as they entered into the driver.
-		 */
-		cdf_nbuf_map(target->osdev,
-			     GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket),
-			     CDF_DMA_TO_DEVICE);
-
-		pPacket->PktInfo.AsTx.Flags |= HTC_TX_PACKET_FLAG_FIXUP_NETBUF;
-	}
-	HTC_PACKET_QUEUE_ITERATE_END;
-
-#ifdef USB_HIF_SINGLE_PIPE_DATA_SCHED
-	if (!htc_send_pkts_sched_check(HTCHandle, pEndpoint->Id)) {
-		htc_send_pkts_sched_queue(HTCHandle, pPktQueue, pEndpoint->Id);
-	} else {
-		htc_try_send(target, pEndpoint, pPktQueue);
-	}
-#else
-	htc_try_send(target, pEndpoint, pPktQueue);
-#endif
-
-	/* do completion on any packets that couldn't get in */
-	if (!HTC_QUEUE_EMPTY(pPktQueue)) {
-
-		HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pPktQueue, pPacket) {
-			/* remove the headroom reserved for HTC_FRAME_HDR */
-			restore_tx_packet(target, pPacket);
-
-			if (HTC_STOPPING(target)) {
-				pPacket->Status = A_ECANCELED;
-			} else {
-				pPacket->Status = A_NO_RESOURCE;
-			}
-		}
-		HTC_PACKET_QUEUE_ITERATE_END;
-
-		do_send_completion(pEndpoint, pPktQueue);
-	}
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-htc_send_pkts_multiple \n"));
-
-	return A_OK;
-}
-
-/* HTC API - htc_send_pkt */
-A_STATUS htc_send_pkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket)
-{
-	HTC_PACKET_QUEUE queue;
-
-	if (HTCHandle == NULL || pPacket == NULL) {
-		return A_ERROR;
-	}
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("+-htc_send_pkt: Enter endPointId: %d, buffer: %p, length: %d \n",
-			 pPacket->Endpoint, pPacket->pBuffer,
-			 pPacket->ActualLength));
-	INIT_HTC_PACKET_QUEUE_AND_ADD(&queue, pPacket);
-	return htc_send_pkts_multiple(HTCHandle, &queue);
-}
-
-#ifdef ATH_11AC_TXCOMPACT
-
-A_STATUS htc_send_data_pkt(HTC_HANDLE HTCHandle, cdf_nbuf_t netbuf, int Epid,
-			   int ActualLength)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint;
-	HTC_FRAME_HDR *pHtcHdr;
-	A_STATUS status = A_OK;
-	int tx_resources;
-	uint32_t data_attr = 0;
-
-	pEndpoint = &target->endpoint[Epid];
-
-	tx_resources =
-		hif_get_free_queue_number(target->hif_dev, pEndpoint->UL_PipeID);
-
-	if (tx_resources < HTC_DATA_RESOURCE_THRS) {
-		if (pEndpoint->ul_is_polled) {
-			hif_send_complete_check(pEndpoint->target->hif_dev,
-						pEndpoint->UL_PipeID, 1);
-			tx_resources =
-				hif_get_free_queue_number(target->hif_dev,
-							  pEndpoint->UL_PipeID);
-		}
-		if (tx_resources < HTC_DATA_MINDESC_PERPACKET) {
-			return A_ERROR;
-		}
-	}
-
-	if (hif_pm_runtime_get(target->hif_dev))
-		return A_ERROR;
-
-	pHtcHdr = (HTC_FRAME_HDR *) cdf_nbuf_get_frag_vaddr(netbuf, 0);
-	AR_DEBUG_ASSERT(pHtcHdr);
-
-	data_attr = cdf_nbuf_data_attr_get(netbuf);
-
-	HTC_WRITE32(pHtcHdr, SM(ActualLength, HTC_FRAME_HDR_PAYLOADLEN) |
-		    SM(Epid, HTC_FRAME_HDR_ENDPOINTID));
-	/*
-	 * If the HIF pipe for the data endpoint is polled rather than
-	 * interrupt-driven, this is a good point to check whether any
-	 * data previously sent through the HIF pipe have finished being
-	 * sent.
-	 * Since this may result in callbacks to htc_tx_completion_handler,
-	 * which can take the HTC tx lock, make the hif_send_complete_check
-	 * call before acquiring the HTC tx lock.
-	 * Call hif_send_complete_check directly, rather than calling
-	 * htc_send_complete_check, and call the PollTimerStart separately
-	 * after calling hif_send_head, so the timer will be started to
-	 * check for completion of the new outstanding download (in the
-	 * unexpected event that other polling calls don't catch it).
-	 */
-
-	LOCK_HTC_TX(target);
-
-	HTC_WRITE32(((A_UINT32 *) pHtcHdr) + 1,
-		    SM(pEndpoint->SeqNo, HTC_FRAME_HDR_CONTROLBYTES1));
-
-	pEndpoint->SeqNo++;
-
-	NBUF_UPDATE_TX_PKT_COUNT(netbuf, NBUF_TX_PKT_HTC);
-	DPTRACE(cdf_dp_trace(netbuf, CDF_DP_TRACE_HTC_PACKET_PTR_RECORD,
-				(uint8_t *)(cdf_nbuf_data(netbuf)),
-				sizeof(cdf_nbuf_data(netbuf))));
-	status = hif_send_head(target->hif_dev,
-			       pEndpoint->UL_PipeID,
-			       pEndpoint->Id, ActualLength, netbuf, data_attr);
-
-	UNLOCK_HTC_TX(target);
-	return status;
-}
-#else                           /*ATH_11AC_TXCOMPACT */
-
-A_STATUS htc_send_data_pkt(HTC_HANDLE HTCHandle, HTC_PACKET *pPacket,
-			   A_UINT8 more_data)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint;
-	HTC_FRAME_HDR *pHtcHdr;
-	HTC_PACKET_QUEUE sendQueue;
-	cdf_nbuf_t netbuf = NULL;
-	int tx_resources;
-	A_STATUS status = A_OK;
-	uint32_t data_attr = 0;
-
-	if (pPacket) {
-		AR_DEBUG_ASSERT(pPacket->Endpoint < ENDPOINT_MAX);
-		pEndpoint = &target->endpoint[pPacket->Endpoint];
-
-		/* add HTC_FRAME_HDR in the initial fragment */
-		netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-		pHtcHdr = (HTC_FRAME_HDR *) cdf_nbuf_get_frag_vaddr(netbuf, 0);
-		AR_DEBUG_ASSERT(pHtcHdr);
-
-		HTC_WRITE32(pHtcHdr,
-			    SM(pPacket->ActualLength,
-			       HTC_FRAME_HDR_PAYLOADLEN) | SM(pPacket->PktInfo.
-							      AsTx.SendFlags,
-							      HTC_FRAME_HDR_FLAGS)
-			    | SM(pPacket->Endpoint, HTC_FRAME_HDR_ENDPOINTID));
-		/*
-		 * If the HIF pipe for the data endpoint is polled rather than
-		 * interrupt-driven, this is a good point to check whether any
-		 * data previously sent through the HIF pipe have finished being
-		 * sent.
-		 * Since this may result in callbacks to htc_tx_completion_handler,
-		 * which can take the HTC tx lock, make the hif_send_complete_check
-		 * call before acquiring the HTC tx lock.
-		 * Call hif_send_complete_check directly, rather than calling
-		 * htc_send_complete_check, and call the PollTimerStart separately
-		 * after calling hif_send_head, so the timer will be started to
-		 * check for completion of the new outstanding download (in the
-		 * unexpected event that other polling calls don't catch it).
-		 */
-		if (pEndpoint->ul_is_polled) {
-			htc_send_complete_poll_timer_stop(pEndpoint);
-			hif_send_complete_check(pEndpoint->target->hif_dev,
-						pEndpoint->UL_PipeID, 0);
-		}
-
-		LOCK_HTC_TX(target);
-
-		pPacket->PktInfo.AsTx.SeqNo = pEndpoint->SeqNo;
-		pEndpoint->SeqNo++;
-
-		HTC_WRITE32(((A_UINT32 *) pHtcHdr) + 1,
-			    SM(pPacket->PktInfo.AsTx.SeqNo,
-			       HTC_FRAME_HDR_CONTROLBYTES1));
-
-		/* append new packet to pEndpoint->TxQueue */
-		HTC_PACKET_ENQUEUE(&pEndpoint->TxQueue, pPacket);
-#ifdef ENABLE_BUNDLE_TX
-		if (HTC_ENABLE_BUNDLE(target) && (more_data)) {
-			UNLOCK_HTC_TX(target);
-			return A_OK;
-		}
-#endif
-	} else {
-		LOCK_HTC_TX(target);
-		pEndpoint = &target->endpoint[1];
-	}
-
-	/* increment tx processing count on entry */
-	cdf_atomic_inc(&pEndpoint->TxProcessCount);
-	if (cdf_atomic_read(&pEndpoint->TxProcessCount) > 1) {
-		/*
-		 * Another thread or task is draining the TX queues on this endpoint.
-		 * That thread will reset the tx processing count when the queue is
-		 * drained.
-		 */
-		cdf_atomic_dec(&pEndpoint->TxProcessCount);
-		UNLOCK_HTC_TX(target);
-		return A_OK;
-	}
-
-	/***** beyond this point only 1 thread may enter ******/
-
-	INIT_HTC_PACKET_QUEUE(&sendQueue);
-	if (IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) {
-#if DEBUG_CREDIT
-		int cred = pEndpoint->TxCredits;
-#endif
-		get_htc_send_packets_credit_based(target, pEndpoint, &sendQueue);
-#if DEBUG_CREDIT
-		if (ep_debug_mask & (1 << pEndpoint->Id)) {
-			if (cred - pEndpoint->TxCredits > 0) {
-				AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-						(" <HTC> Decrease EP%d %d - %d = %d credits.\n",
-						 pEndpoint->Id, cred,
-						 cred - pEndpoint->TxCredits,
-						 pEndpoint->TxCredits));
-			}
-		}
-#endif
-		UNLOCK_HTC_TX(target);
-	}
-#ifdef ENABLE_BUNDLE_TX
-	else if (HTC_ENABLE_BUNDLE(target)) {
-		/* Dequeue max packets from endpoint tx queue */
-		get_htc_send_packets(target, pEndpoint, &sendQueue,
-				     HTC_MAX_TX_BUNDLE_SEND_LIMIT);
-		UNLOCK_HTC_TX(target);
-	}
-#endif
-	else {
-		/*
-		 * Now drain the endpoint TX queue for transmission as long as we have
-		 * enough transmit resources
-		 */
-		tx_resources =
-			hif_get_free_queue_number(target->hif_dev,
-						  pEndpoint->UL_PipeID);
-		get_htc_send_packets(target, pEndpoint, &sendQueue, tx_resources);
-		UNLOCK_HTC_TX(target);
-	}
-	NBUF_UPDATE_TX_PKT_COUNT(netbuf, NBUF_TX_PKT_HTC);
-	DPTRACE(cdf_dp_trace(netbuf, CDF_DP_TRACE_HTC_PACKET_PTR_RECORD,
-				(uint8_t *)(cdf_nbuf_data(netbuf)),
-				sizeof(cdf_nbuf_data(netbuf))));
-
-	/* send what we can */
-	while (true) {
-#if defined(HIF_USB) || defined(HIF_SDIO)
-#ifdef ENABLE_BUNDLE_TX
-		if (HTC_ENABLE_BUNDLE(target) &&
-		    HTC_PACKET_QUEUE_DEPTH(&sendQueue) >=
-		    HTC_MIN_MSG_PER_BUNDLE) {
-			htc_issue_packets_bundle(target, pEndpoint, &sendQueue);
-		}
-#endif
-#endif
-		pPacket = htc_packet_dequeue(&sendQueue);
-		if (pPacket == NULL) {
-			break;
-		}
-		netbuf = GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket);
-
-		LOCK_HTC_TX(target);
-		/* store in look up queue to match completions */
-		HTC_PACKET_ENQUEUE(&pEndpoint->TxLookupQueue, pPacket);
-		INC_HTC_EP_STAT(pEndpoint, TxIssued, 1);
-		pEndpoint->ul_outstanding_cnt++;
-		UNLOCK_HTC_TX(target);
-
-		status = hif_send_head(target->hif_dev,
-				       pEndpoint->UL_PipeID,
-				       pEndpoint->Id,
-				       HTC_HDR_LENGTH + pPacket->ActualLength,
-				       netbuf, data_attr);
-#if DEBUG_BUNDLE
-		cdf_print(" Send single EP%d buffer size:0x%x, total:0x%x.\n",
-			  pEndpoint->Id,
-			  pEndpoint->TxCreditSize,
-			  HTC_HDR_LENGTH + pPacket->ActualLength);
-#endif
-
-		if (cdf_unlikely(A_FAILED(status))) {
-			LOCK_HTC_TX(target);
-			pEndpoint->ul_outstanding_cnt--;
-			/* remove this packet from the tx completion queue */
-			HTC_PACKET_REMOVE(&pEndpoint->TxLookupQueue, pPacket);
-
-			/*
-			 * Don't bother reclaiming credits - HTC flow control
-			 * is not applicable to tx data.
-			 * In LL systems, there is no download flow control,
-			 * since there's virtually no download delay.
-			 * In HL systems, the txrx SW explicitly performs the
-			 * tx flow control.
-			 */
-			/* pEndpoint->TxCredits += pPacket->PktInfo.AsTx.CreditsUsed; */
-
-			/* put this frame back at the front of the sendQueue */
-			HTC_PACKET_ENQUEUE_TO_HEAD(&sendQueue, pPacket);
-
-			/* put the sendQueue back at the front of pEndpoint->TxQueue */
-			HTC_PACKET_QUEUE_TRANSFER_TO_HEAD(&pEndpoint->TxQueue,
-							  &sendQueue);
-			UNLOCK_HTC_TX(target);
-			break;  /* still need to reset TxProcessCount */
-		}
-	}
-	/* done with this endpoint, we can clear the count */
-	cdf_atomic_init(&pEndpoint->TxProcessCount);
-
-	if (pEndpoint->ul_is_polled) {
-		/*
-		 * Start a cleanup timer to poll for download completion.
-		 * The download completion should be noticed promptly from
-		 * other polling calls, but the timer provides a safety net
-		 * in case other polling calls don't occur as expected.
-		 */
-		htc_send_complete_poll_timer_start(pEndpoint);
-	}
-
-	return status;
-}
-#endif /*ATH_11AC_TXCOMPACT */
-
-/*
- * In the adapted HIF layer, cdf_nbuf_t are passed between HIF and HTC, since upper layers expects
- * HTC_PACKET containers we use the completed netbuf and lookup its corresponding HTC packet buffer
- * from a lookup list.
- * This is extra overhead that can be fixed by re-aligning HIF interfaces with HTC.
- *
- */
-static HTC_PACKET *htc_lookup_tx_packet(HTC_TARGET *target,
-					HTC_ENDPOINT *pEndpoint,
-					cdf_nbuf_t netbuf)
-{
-	HTC_PACKET *pPacket = NULL;
-	HTC_PACKET *pFoundPacket = NULL;
-	HTC_PACKET_QUEUE lookupQueue;
-
-	INIT_HTC_PACKET_QUEUE(&lookupQueue);
-	LOCK_HTC_TX(target);
-
-	/* mark that HIF has indicated the send complete for another packet */
-	pEndpoint->ul_outstanding_cnt--;
-
-	/* Dequeue first packet directly because of in-order completion */
-	pPacket = htc_packet_dequeue(&pEndpoint->TxLookupQueue);
-	if (cdf_unlikely(!pPacket)) {
-		UNLOCK_HTC_TX(target);
-		return NULL;
-	}
-	if (netbuf == (cdf_nbuf_t) GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket)) {
-		UNLOCK_HTC_TX(target);
-		return pPacket;
-	} else {
-		HTC_PACKET_ENQUEUE(&lookupQueue, pPacket);
-	}
-
-	/*
-	 * Move TX lookup queue to temp queue because most of packets that are not index 0
-	 * are not top 10 packets.
-	 */
-	HTC_PACKET_QUEUE_TRANSFER_TO_TAIL(&lookupQueue,
-					  &pEndpoint->TxLookupQueue);
-	UNLOCK_HTC_TX(target);
-
-	ITERATE_OVER_LIST_ALLOW_REMOVE(&lookupQueue.QueueHead, pPacket,
-				       HTC_PACKET, ListLink) {
-
-		if (NULL == pPacket) {
-			pFoundPacket = pPacket;
-			break;
-		}
-		/* check for removal */
-		if (netbuf ==
-		    (cdf_nbuf_t) GET_HTC_PACKET_NET_BUF_CONTEXT(pPacket)) {
-			/* found it */
-			HTC_PACKET_REMOVE(&lookupQueue, pPacket);
-			pFoundPacket = pPacket;
-			break;
-		}
-
-	}
-	ITERATE_END;
-
-	LOCK_HTC_TX(target);
-	HTC_PACKET_QUEUE_TRANSFER_TO_HEAD(&pEndpoint->TxLookupQueue,
-					  &lookupQueue);
-	UNLOCK_HTC_TX(target);
-
-	return pFoundPacket;
-}
-
-CDF_STATUS htc_tx_completion_handler(void *Context,
-				   cdf_nbuf_t netbuf, unsigned int EpID,
-				   uint32_t toeplitz_hash_result)
-{
-	HTC_TARGET *target = (HTC_TARGET *) Context;
-	HTC_ENDPOINT *pEndpoint;
-	HTC_PACKET *pPacket;
-#ifdef USB_HIF_SINGLE_PIPE_DATA_SCHED
-	HTC_ENDPOINT_ID eid[DATA_EP_SIZE] =
-	{ ENDPOINT_5, ENDPOINT_4, ENDPOINT_2, ENDPOINT_3 };
-	int epidIdx;
-	A_UINT16 resourcesThresh[DATA_EP_SIZE]; /* urb resources */
-	A_UINT16 resources;
-	A_UINT16 resourcesMax;
-#endif
-
-	pEndpoint = &target->endpoint[EpID];
-	target->TX_comp_cnt++;
-
-	do {
-		pPacket = htc_lookup_tx_packet(target, pEndpoint, netbuf);
-		if (NULL == pPacket) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					("HTC TX lookup failed!\n"));
-			/* may have already been flushed and freed */
-			netbuf = NULL;
-			break;
-		}
-		if (pPacket->PktInfo.AsTx.Tag != HTC_TX_PACKET_TAG_AUTO_PM)
-			hif_pm_runtime_put(target->hif_dev);
-
-		if (pPacket->PktInfo.AsTx.Tag == HTC_TX_PACKET_TAG_BUNDLED) {
-			HTC_PACKET *pPacketTemp;
-			HTC_PACKET_QUEUE *pQueueSave =
-				(HTC_PACKET_QUEUE *) pPacket->pContext;
-			HTC_PACKET_QUEUE_ITERATE_ALLOW_REMOVE(pQueueSave,
-							      pPacketTemp) {
-				pPacket->Status = A_OK;
-				send_packet_completion(target, pPacketTemp);
-			}
-			HTC_PACKET_QUEUE_ITERATE_END;
-			free_htc_bundle_packet(target, pPacket);
-			return CDF_STATUS_SUCCESS;
-		}
-		/* will be giving this buffer back to upper layers */
-		netbuf = NULL;
-		pPacket->Status = CDF_STATUS_SUCCESS;
-		send_packet_completion(target, pPacket);
-
-	} while (false);
-
-	if (!IS_TX_CREDIT_FLOW_ENABLED(pEndpoint)) {
-		/* note: when using TX credit flow, the re-checking of queues happens
-		* when credits flow back from the target.
-		* in the non-TX credit case, we recheck after the packet completes */
-		htc_try_send(target, pEndpoint, NULL);
-	}
-
-	return CDF_STATUS_SUCCESS;
-}
-
-/* callback when TX resources become available */
-void htc_tx_resource_avail_handler(void *context, A_UINT8 pipeID)
-{
-	int i;
-	HTC_TARGET *target = (HTC_TARGET *) context;
-	HTC_ENDPOINT *pEndpoint = NULL;
-
-	for (i = 0; i < ENDPOINT_MAX; i++) {
-		pEndpoint = &target->endpoint[i];
-		if (pEndpoint->service_id != 0) {
-			if (pEndpoint->UL_PipeID == pipeID) {
-				break;
-			}
-		}
-	}
-
-	if (i >= ENDPOINT_MAX) {
-		AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-				("Invalid pipe indicated for TX resource avail : %d!\n",
-				 pipeID));
-		return;
-	}
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("HIF indicated more resources for pipe:%d \n",
-			 pipeID));
-
-	htc_try_send(target, pEndpoint, NULL);
-}
-
-/**
- * htc_kick_queues(): resumes tx transactions of suspended endpoints
- * @context: pointer to the htc target context
- *
- * Iterates throught the enpoints and provides a context to empty queues
- * int the hif layer when they are stalled due to runtime suspend.
- *
- * Return: none
- */
-void htc_kick_queues(void *context)
-{
-	int i;
-	HTC_TARGET *target = (HTC_TARGET *)context;
-	HTC_ENDPOINT *endpoint = NULL;
-
-	for (i = 0; i < ENDPOINT_MAX; i++) {
-		endpoint = &target->endpoint[i];
-
-		if (endpoint->service_id == 0)
-			continue;
-
-		if (endpoint->EpCallBacks.ep_resume_tx_queue)
-			endpoint->EpCallBacks.ep_resume_tx_queue(
-					endpoint->EpCallBacks.pContext);
-
-		htc_try_send(target, endpoint, NULL);
-	}
-}
-
-/* flush endpoint TX queue */
-void htc_flush_endpoint_tx(HTC_TARGET *target, HTC_ENDPOINT *pEndpoint,
-			   HTC_TX_TAG Tag)
-{
-	HTC_PACKET *pPacket;
-
-	LOCK_HTC_TX(target);
-	while (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)) {
-		pPacket = htc_packet_dequeue(&pEndpoint->TxQueue);
-
-		if (pPacket) {
-			/* let the sender know the packet was not delivered */
-			pPacket->Status = A_ECANCELED;
-			send_packet_completion(target, pPacket);
-		}
-	}
-	UNLOCK_HTC_TX(target);
-}
-
-/* HTC API to flush an endpoint's TX queue*/
-void htc_flush_endpoint(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint,
-			HTC_TX_TAG Tag)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	HTC_ENDPOINT *pEndpoint = &target->endpoint[Endpoint];
-
-	if (pEndpoint->service_id == 0) {
-		AR_DEBUG_ASSERT(false);
-		/* not in use.. */
-		return;
-	}
-
-	htc_flush_endpoint_tx(target, pEndpoint, Tag);
-}
-
-/* HTC API to indicate activity to the credit distribution function */
-void htc_indicate_activity_change(HTC_HANDLE HTCHandle,
-				  HTC_ENDPOINT_ID Endpoint, A_BOOL Active)
-{
-	/*  TODO */
-}
-
-A_BOOL htc_is_endpoint_active(HTC_HANDLE HTCHandle, HTC_ENDPOINT_ID Endpoint)
-{
-	return true;
-}
-
-/* process credit reports and call distribution function */
-void htc_process_credit_rpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt,
-			    int NumEntries, HTC_ENDPOINT_ID FromEndpoint)
-{
-	int i;
-	HTC_ENDPOINT *pEndpoint;
-	int totalCredits = 0;
-	A_UINT8 rpt_credits, rpt_ep_id;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("+htc_process_credit_rpt, Credit Report Entries:%d \n",
-			 NumEntries));
-
-	/* lock out TX while we update credits */
-	LOCK_HTC_TX(target);
-
-	for (i = 0; i < NumEntries; i++, pRpt++) {
-
-		rpt_ep_id = HTC_GET_FIELD(pRpt, HTC_CREDIT_REPORT, ENDPOINTID);
-
-		if (rpt_ep_id >= ENDPOINT_MAX) {
-			AR_DEBUG_ASSERT(false);
-			break;
-		}
-
-		rpt_credits = HTC_GET_FIELD(pRpt, HTC_CREDIT_REPORT, CREDITS);
-
-		pEndpoint = &target->endpoint[rpt_ep_id];
-#if DEBUG_CREDIT
-		if (ep_debug_mask & (1 << pEndpoint->Id)) {
-			AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-					(" <HTC> Increase EP%d %d + %d = %d credits\n",
-					 rpt_ep_id, pEndpoint->TxCredits,
-					 rpt_credits,
-					 pEndpoint->TxCredits + rpt_credits));
-		}
-#endif
-
-#ifdef HTC_EP_STAT_PROFILING
-
-		INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
-		INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, rpt_credits);
-
-		if (FromEndpoint == rpt_ep_id) {
-			/* this credit report arrived on the same endpoint indicating it arrived in an RX
-			 * packet */
-			INC_HTC_EP_STAT(pEndpoint, TxCreditsFromRx,
-					rpt_credits);
-			INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromRx, 1);
-		} else if (FromEndpoint == ENDPOINT_0) {
-			/* this credit arrived on endpoint 0 as a NULL message */
-			INC_HTC_EP_STAT(pEndpoint, TxCreditsFromEp0,
-					rpt_credits);
-			INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromEp0, 1);
-		} else {
-			/* arrived on another endpoint */
-			INC_HTC_EP_STAT(pEndpoint, TxCreditsFromOther,
-					rpt_credits);
-			INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
-		}
-
-#endif
-#if defined(HIF_USB)
-		if (pEndpoint->Id >= ENDPOINT_2 && pEndpoint->Id <= ENDPOINT_5) {
-			HTC_ENDPOINT_ID eid[DATA_EP_SIZE] =
-			{ ENDPOINT_5, ENDPOINT_4, ENDPOINT_2, ENDPOINT_3 };
-			int epid_idx;
-
-			target->avail_tx_credits += rpt_credits;
-
-			for (epid_idx = 0; epid_idx < DATA_EP_SIZE; epid_idx++) {
-				pEndpoint = &target->endpoint[eid[epid_idx]];
-				if (HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)) {
-					break;
-				}
-
-			}
-			UNLOCK_HTC_TX(target);
-			htc_try_send(target, pEndpoint, NULL);
-			LOCK_HTC_TX(target);
-		} else {
-			pEndpoint->TxCredits += rpt_credits;
-
-			if (pEndpoint->TxCredits
-			    && HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)) {
-				UNLOCK_HTC_TX(target);
-				htc_try_send(target, pEndpoint, NULL);
-				LOCK_HTC_TX(target);
-			}
-		}
-#else
-		pEndpoint->TxCredits += rpt_credits;
-
-		if (pEndpoint->service_id == WMI_CONTROL_SVC) {
-			LOCK_HTC_CREDIT(target);
-			htc_credit_record(HTC_PROCESS_CREDIT_REPORT,
-					  pEndpoint->TxCredits,
-					  HTC_PACKET_QUEUE_DEPTH(&pEndpoint->
-								 TxQueue));
-			UNLOCK_HTC_CREDIT(target);
-		}
-
-		if (pEndpoint->TxCredits
-		    && HTC_PACKET_QUEUE_DEPTH(&pEndpoint->TxQueue)) {
-			UNLOCK_HTC_TX(target);
-#ifdef ATH_11AC_TXCOMPACT
-			htc_try_send(target, pEndpoint, NULL);
-#else
-			if (pEndpoint->service_id == HTT_DATA_MSG_SVC) {
-				htc_send_data_pkt(target, NULL, 0);
-			} else {
-				htc_try_send(target, pEndpoint, NULL);
-			}
-#endif
-			LOCK_HTC_TX(target);
-		}
-#endif
-		totalCredits += rpt_credits;
-	}
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
-			("  Report indicated %d credits to distribute \n",
-			 totalCredits));
-
-	UNLOCK_HTC_TX(target);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_SEND, ("-htc_process_credit_rpt \n"));
-}
-
-/* function to fetch stats from htc layer*/
-struct ol_ath_htc_stats *ieee80211_ioctl_get_htc_stats(HTC_HANDLE HTCHandle)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-
-	return (&(target->htc_pkt_stats));
-}

core/htc/htc_services.c

@@ -1,369 +0,0 @@
-/*
- * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
- *
- * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
- *
- *
- * Permission to use, copy, modify, and/or distribute this software for
- * any purpose with or without fee is hereby granted, provided that the
- * above copyright notice and this permission notice appear in all
- * copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
- * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
- * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
- * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
- * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This file was originally distributed by Qualcomm Atheros, Inc.
- * under proprietary terms before Copyright ownership was assigned
- * to the Linux Foundation.
- */
-
-#include "htc_debug.h"
-#include "htc_internal.h"
-#include <cdf_nbuf.h>           /* cdf_nbuf_t */
-#include "hif.h"
-
-/* use credit flow control over HTC */
-unsigned int htc_credit_flow = 1;
-#ifndef DEBUG_CREDIT
-#define DEBUG_CREDIT 0
-#endif
-
-A_STATUS htc_connect_service(HTC_HANDLE HTCHandle,
-			     HTC_SERVICE_CONNECT_REQ *pConnectReq,
-			     HTC_SERVICE_CONNECT_RESP *pConnectResp)
-{
-	HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
-	A_STATUS status = A_OK;
-	HTC_PACKET *pSendPacket = NULL;
-	HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg;
-	HTC_CONNECT_SERVICE_MSG *pConnectMsg;
-	HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX;
-	HTC_ENDPOINT *pEndpoint;
-	unsigned int maxMsgSize = 0;
-	cdf_nbuf_t netbuf;
-	A_UINT8 txAlloc;
-	int length;
-	A_BOOL disableCreditFlowCtrl = false;
-	A_UINT16 conn_flags;
-	A_UINT16 rsp_msg_id, rsp_msg_serv_id, rsp_msg_max_msg_size;
-	A_UINT8 rsp_msg_status, rsp_msg_end_id, rsp_msg_serv_meta_len;
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
-			("+htc_connect_service, target:%p SvcID:0x%X\n", target,
-			 pConnectReq->service_id));
-
-	do {
-
-		AR_DEBUG_ASSERT(pConnectReq->service_id != 0);
-
-		if (HTC_CTRL_RSVD_SVC == pConnectReq->service_id) {
-			/* special case for pseudo control service */
-			assignedEndpoint = ENDPOINT_0;
-			maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
-			txAlloc = 0;
-
-		} else {
-
-			txAlloc = htc_get_credit_allocation(target,
-					pConnectReq->service_id);
-
-			if (!txAlloc) {
-				AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
-						("Service %d does not allocate target credits!\n",
-						 pConnectReq->service_id));
-			}
-
-			/* allocate a packet to send to the target */
-			pSendPacket = htc_alloc_control_tx_packet(target);
-
-			if (NULL == pSendPacket) {
-				AR_DEBUG_ASSERT(false);
-				status = A_NO_MEMORY;
-				break;
-			}
-
-			netbuf =
-				(cdf_nbuf_t)
-				GET_HTC_PACKET_NET_BUF_CONTEXT(pSendPacket);
-			length =
-				sizeof(HTC_CONNECT_SERVICE_MSG) +
-				pConnectReq->MetaDataLength;
-
-			/* assemble connect service message */
-			cdf_nbuf_put_tail(netbuf, length);
-			pConnectMsg =
-				(HTC_CONNECT_SERVICE_MSG *) cdf_nbuf_data(netbuf);
-
-			if (NULL == pConnectMsg) {
-				AR_DEBUG_ASSERT(0);
-				status = A_EFAULT;
-				break;
-			}
-
-			A_MEMZERO(pConnectMsg, sizeof(HTC_CONNECT_SERVICE_MSG));
-
-			conn_flags =
-				(pConnectReq->
-				 ConnectionFlags & ~HTC_SET_RECV_ALLOC_MASK) |
-				HTC_CONNECT_FLAGS_SET_RECV_ALLOCATION(txAlloc);
-			HTC_SET_FIELD(pConnectMsg, HTC_CONNECT_SERVICE_MSG,
-				      MESSAGEID, HTC_MSG_CONNECT_SERVICE_ID);
-			HTC_SET_FIELD(pConnectMsg, HTC_CONNECT_SERVICE_MSG,
-				      SERVICE_ID, pConnectReq->service_id);
-			HTC_SET_FIELD(pConnectMsg, HTC_CONNECT_SERVICE_MSG,
-				      CONNECTIONFLAGS, conn_flags);
-
-			if (pConnectReq->
-			    ConnectionFlags &
-			    HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL) {
-				disableCreditFlowCtrl = true;
-			}
-#if defined(HIF_USB)
-			if (!htc_credit_flow) {
-				disableCreditFlowCtrl = true;
-			}
-#else
-			/* Only enable credit for WMI service */
-			if (!htc_credit_flow
-			    && pConnectReq->service_id != WMI_CONTROL_SVC) {
-				disableCreditFlowCtrl = true;
-			}
-#endif
-			/* check caller if it wants to transfer meta data */
-			if ((pConnectReq->pMetaData != NULL) &&
-			    (pConnectReq->MetaDataLength <=
-			     HTC_SERVICE_META_DATA_MAX_LENGTH)) {
-				/* copy meta data into message buffer (after header ) */
-				A_MEMCPY((A_UINT8 *) pConnectMsg +
-					 sizeof(HTC_CONNECT_SERVICE_MSG),
-					 pConnectReq->pMetaData,
-					 pConnectReq->MetaDataLength);
-
-				HTC_SET_FIELD(pConnectMsg,
-					      HTC_CONNECT_SERVICE_MSG,
-					      SERVICEMETALENGTH,
-					      pConnectReq->MetaDataLength);
-			}
-
-			SET_HTC_PACKET_INFO_TX(pSendPacket,
-					       NULL,
-					       (A_UINT8 *) pConnectMsg,
-					       length,
-					       ENDPOINT_0,
-					       HTC_SERVICE_TX_PACKET_TAG);
-
-			status = htc_send_pkt((HTC_HANDLE) target, pSendPacket);
-			/* we don't own it anymore */
-			pSendPacket = NULL;
-			if (A_FAILED(status)) {
-				break;
-			}
-
-			/* wait for response */
-			status = htc_wait_recv_ctrl_message(target);
-			if (A_FAILED(status)) {
-				break;
-			}
-			/* we controlled the buffer creation so it has to be properly aligned */
-			pResponseMsg =
-				(HTC_CONNECT_SERVICE_RESPONSE_MSG *) target->
-				CtrlResponseBuffer;
-
-			rsp_msg_id = HTC_GET_FIELD(pResponseMsg,
-						   HTC_CONNECT_SERVICE_RESPONSE_MSG,
-						   MESSAGEID);
-			rsp_msg_serv_id =
-				HTC_GET_FIELD(pResponseMsg,
-					      HTC_CONNECT_SERVICE_RESPONSE_MSG,
-					      SERVICEID);
-			rsp_msg_status =
-				HTC_GET_FIELD(pResponseMsg,
-					      HTC_CONNECT_SERVICE_RESPONSE_MSG,
-					      STATUS);
-			rsp_msg_end_id =
-				HTC_GET_FIELD(pResponseMsg,
-					      HTC_CONNECT_SERVICE_RESPONSE_MSG,
-					      ENDPOINTID);
-			rsp_msg_max_msg_size =
-				HTC_GET_FIELD(pResponseMsg,
-					      HTC_CONNECT_SERVICE_RESPONSE_MSG,
-					      MAXMSGSIZE);
-			rsp_msg_serv_meta_len =
-				HTC_GET_FIELD(pResponseMsg,
-					      HTC_CONNECT_SERVICE_RESPONSE_MSG,
-					      SERVICEMETALENGTH);
-
-			if ((rsp_msg_id != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID)
-			    || (target->CtrlResponseLength <
-				sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
-				/* this message is not valid */
-				AR_DEBUG_ASSERT(false);
-				status = A_EPROTO;
-				break;
-			}
-
-			AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
-					("htc_connect_service, service 0x%X connect response from target status:%d, assigned ep: %d\n",
-					 rsp_msg_serv_id, rsp_msg_status,
-					 rsp_msg_end_id));
-
-			pConnectResp->ConnectRespCode = rsp_msg_status;
-
-			/* check response status */
-			if (rsp_msg_status != HTC_SERVICE_SUCCESS) {
-				AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
-						(" Target failed service 0x%X connect request (status:%d)\n",
-						 rsp_msg_serv_id,
-						 rsp_msg_status));
-				status = A_EPROTO;
-#ifdef QCA_TX_HTT2_SUPPORT
-				/* Keep work and not to block the control message. */
-				target->CtrlResponseProcessing = false;
-#endif /* QCA_TX_HTT2_SUPPORT */
-				break;
-			}
-
-			assignedEndpoint = (HTC_ENDPOINT_ID) rsp_msg_end_id;
-			maxMsgSize = rsp_msg_max_msg_size;
-
-			if ((pConnectResp->pMetaData != NULL) &&
-			    (rsp_msg_serv_meta_len > 0) &&
-			    (rsp_msg_serv_meta_len <=
-			     HTC_SERVICE_META_DATA_MAX_LENGTH)) {
-				/* caller supplied a buffer and the target responded with data */
-				int copyLength =
-					min((int)pConnectResp->BufferLength,
-					    (int)rsp_msg_serv_meta_len);
-				/* copy the meta data */
-				A_MEMCPY(pConnectResp->pMetaData,
-					 ((A_UINT8 *) pResponseMsg) +
-					 sizeof
-					 (HTC_CONNECT_SERVICE_RESPONSE_MSG),
-					 copyLength);
-				pConnectResp->ActualLength = copyLength;
-			}
-			/* done processing response buffer */
-			target->CtrlResponseProcessing = false;
-		}
-
-		/* the rest of these are parameter checks so set the error status */
-		status = A_EPROTO;
-
-		if (assignedEndpoint >= ENDPOINT_MAX) {
-			AR_DEBUG_ASSERT(false);
-			break;
-		}
-
-		if (0 == maxMsgSize) {
-			AR_DEBUG_ASSERT(false);
-			break;
-		}
-
-		pEndpoint = &target->endpoint[assignedEndpoint];
-		pEndpoint->Id = assignedEndpoint;
-		if (pEndpoint->service_id != 0) {
-			/* endpoint already in use! */
-			AR_DEBUG_ASSERT(false);
-			break;
-		}
-
-		/* return assigned endpoint to caller */
-		pConnectResp->Endpoint = assignedEndpoint;
-		pConnectResp->MaxMsgLength = maxMsgSize;
-
-		/* setup the endpoint */
-		/* service_id marks the endpoint in use */
-		pEndpoint->service_id = pConnectReq->service_id;
-		pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
-		pEndpoint->MaxMsgLength = maxMsgSize;
-		pEndpoint->TxCredits = txAlloc;
-		pEndpoint->TxCreditSize = target->TargetCreditSize;
-		pEndpoint->TxCreditsPerMaxMsg =
-			maxMsgSize / target->TargetCreditSize;
-		if (maxMsgSize % target->TargetCreditSize) {
-			pEndpoint->TxCreditsPerMaxMsg++;
-		}
-#if DEBUG_CREDIT
-		cdf_print(" Endpoint%d initial credit:%d, size:%d.\n",
-			  pEndpoint->Id, pEndpoint->TxCredits,
-			  pEndpoint->TxCreditSize);
-#endif
-
-		/* copy all the callbacks */
-		pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
-
-		status = hif_map_service_to_pipe(target->hif_dev,
-						 pEndpoint->service_id,
-						 &pEndpoint->UL_PipeID,
-						 &pEndpoint->DL_PipeID,
-						 &pEndpoint->ul_is_polled,
-						 &pEndpoint->dl_is_polled);
-		if (A_FAILED(status)) {
-			break;
-		}
-
-		cdf_assert(!pEndpoint->dl_is_polled);   /* not currently supported */
-
-		if (pEndpoint->ul_is_polled) {
-			cdf_softirq_timer_init(target->osdev,
-				&pEndpoint->ul_poll_timer,
-				htc_send_complete_check_cleanup,
-				pEndpoint,
-				CDF_TIMER_TYPE_SW);
-		}
-
-		AR_DEBUG_PRINTF(ATH_DEBUG_SETUP,
-				("HTC Service:0x%4.4X, ULpipe:%d DLpipe:%d id:%d Ready\n",
-				 pEndpoint->service_id, pEndpoint->UL_PipeID,
-				 pEndpoint->DL_PipeID, pEndpoint->Id));
-
-		if (disableCreditFlowCtrl && pEndpoint->TxCreditFlowEnabled) {
-			pEndpoint->TxCreditFlowEnabled = false;
-			AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
-					("HTC Service:0x%4.4X ep:%d TX flow control disabled\n",
-					 pEndpoint->service_id,
-					 assignedEndpoint));
-		}
-
-	} while (false);
-
-	AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-htc_connect_service \n"));
-
-	return status;
-}
-
-void htc_set_credit_distribution(HTC_HANDLE HTCHandle,
-				 void *pCreditDistContext,
-				 HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
-				 HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
-				 HTC_SERVICE_ID ServicePriorityOrder[],
-				 int ListLength)
-{
-	/* NOT Supported, this transport does not use a credit based flow control mechanism */
-
-}
-
-void htc_fw_event_handler(void *context, CDF_STATUS status)
-{
-	HTC_TARGET *target = (HTC_TARGET *) context;
-	HTC_INIT_INFO *initInfo = &target->HTCInitInfo;
-
-	/* check if target failure handler exists and pass error code to it. */
-	if (target->HTCInitInfo.TargetFailure != NULL) {
-		initInfo->TargetFailure(initInfo->pContext, status);
-	}
-}
-
-/* Disable ASPM : disable PCIe low power */
-void htc_disable_aspm(void)
-{
-	hif_disable_aspm();
-}