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fw-api: Add hw header files for QCA8074

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Adding missing hardware header files required for QCA8074

CRs-Fixed: 2091297
Change-Id: Ia27b9e4ad161c6123ad66de422f7f35cb85b9f44
This commit is contained in:
Chaitanya Kiran Godavarthi
2017-08-11 15:01:23 +05:30
committed by snandini
parent ae85353f94
commit 78db2eafe9
18 changed files with 8733 additions and 0 deletions
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434
hw/qca8074/v1/receive_user_info.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RECEIVE_USER_INFO_H_
#define _RECEIVE_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 phy_ppdu_id[15:0], user_rssi[23:16], pkt_type[27:24], stbc[28], sgi[30:29], reserved_0[31]
// 1 rate_mcs[3:0], reception_type[5:4], receive_bandwidth[7:6], mimo_ss_bitmap[15:8], user_ru_allocation[23:16], nss[26:24], reserved_1b[31:27]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RECEIVE_USER_INFO 2
struct receive_user_info {
uint32_t phy_ppdu_id : 16, //[15:0]
user_rssi : 8, //[23:16]
pkt_type : 4, //[27:24]
stbc : 1, //[28]
sgi : 2, //[30:29]
reserved_0 : 1; //[31]
uint32_t rate_mcs : 4, //[3:0]
reception_type : 2, //[5:4]
receive_bandwidth : 2, //[7:6]
mimo_ss_bitmap : 8, //[15:8]
user_ru_allocation : 8, //[23:16]
nss : 3, //[26:24]
reserved_1b : 5; //[31:27]
};
/*
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
user_rssi
RSSI for this user
Frequency domain RSSI measurement for this user. Based
on the channel estimate.
If PHY implementation runs into difficulties, the backup
is to reuse the previously notified RSSI values.
TODO PHY: request to update the text here based on the
latest design insights
<legal all>
pkt_type
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
stbc
When set, use STBC transmission rates
sgi
Field only valid when pkt type is HT, VHT or HE.
<enum 0 gi_0_8_us > Legacy normal GI. Can also be
used for HE
<enum 1 gi_0_4_us > Legacy short GI. Can also be
used for HE
<enum 2 gi_1_6_us > HE related GI
<enum 3 gi_3_2_us > HE related GI
<legal 0 - 3>
reserved_0
<legal 0>
rate_mcs
For details, refer to MCS_TYPE description
<legal all>
reception_type
Indicates what type of reception this is.
<enum 0 reception_type_SU >
<enum 1 reception_type_MU_MIMO >
<enum 2 reception_type_MU_OFDMA >
<enum 3 reception_type_MU_OFDMA_MIMO >
<legal all>
receive_bandwidth
Full receive Bandwidth
<enum 0 full_rx_bw_20_mhz>
<enum 1 full_rx_bw_40_mhz>
<enum 2 full_rx_bw_80_mhz>
<enum 3 full_rx_bw_160_mhz>
<legal 0-3>
mimo_ss_bitmap
Field only valid in case of MIMO type reception
Bitmap, with each bit indicating if the related spatial
stream is used for this STA
LSB related to SS 0
0: spatial stream not used for this reception
1: spatial stream used for this reception
<legal all>
user_ru_allocation
Field only valid in case of OFDMA uplink type reception
Indicates the RU number for this user
<legal 0-73>
nss
Number of Spatial Streams occupied by the User
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
reserved_1b
<legal 0>
*/
/* Description RECEIVE_USER_INFO_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0
#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff
/* Description RECEIVE_USER_INFO_0_USER_RSSI
RSSI for this user
Frequency domain RSSI measurement for this user. Based
on the channel estimate.
If PHY implementation runs into difficulties, the backup
is to reuse the previously notified RSSI values.
TODO PHY: request to update the text here based on the
latest design insights
<legal all>
*/
#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16
#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000
/* Description RECEIVE_USER_INFO_0_PKT_TYPE
Packet type:
<enum 0 dot11a>802.11a PPDU type
<enum 1 dot11b>802.11b PPDU type
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
<enum 3 dot11ac>802.11ac PPDU type
<enum 4 dot11ax>802.11ax PPDU type
*/
#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24
#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000
/* Description RECEIVE_USER_INFO_0_STBC
When set, use STBC transmission rates
*/
#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_STBC_LSB 28
#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000
/* Description RECEIVE_USER_INFO_0_SGI
Field only valid when pkt type is HT, VHT or HE.
<enum 0 gi_0_8_us > Legacy normal GI. Can also be
used for HE
<enum 1 gi_0_4_us > Legacy short GI. Can also be
used for HE
<enum 2 gi_1_6_us > HE related GI
<enum 3 gi_3_2_us > HE related GI
<legal 0 - 3>
*/
#define RECEIVE_USER_INFO_0_SGI_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_SGI_LSB 29
#define RECEIVE_USER_INFO_0_SGI_MASK 0x60000000
/* Description RECEIVE_USER_INFO_0_RESERVED_0
<legal 0>
*/
#define RECEIVE_USER_INFO_0_RESERVED_0_OFFSET 0x00000000
#define RECEIVE_USER_INFO_0_RESERVED_0_LSB 31
#define RECEIVE_USER_INFO_0_RESERVED_0_MASK 0x80000000
/* Description RECEIVE_USER_INFO_1_RATE_MCS
For details, refer to MCS_TYPE description
<legal all>
*/
#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0
#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f
/* Description RECEIVE_USER_INFO_1_RECEPTION_TYPE
Indicates what type of reception this is.
<enum 0 reception_type_SU >
<enum 1 reception_type_MU_MIMO >
<enum 2 reception_type_MU_OFDMA >
<enum 3 reception_type_MU_OFDMA_MIMO >
<legal all>
*/
#define RECEIVE_USER_INFO_1_RECEPTION_TYPE_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_RECEPTION_TYPE_LSB 4
#define RECEIVE_USER_INFO_1_RECEPTION_TYPE_MASK 0x00000030
/* Description RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH
Full receive Bandwidth
<enum 0 full_rx_bw_20_mhz>
<enum 1 full_rx_bw_40_mhz>
<enum 2 full_rx_bw_80_mhz>
<enum 3 full_rx_bw_160_mhz>
<legal 0-3>
*/
#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6
#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0
/* Description RECEIVE_USER_INFO_1_MIMO_SS_BITMAP
Field only valid in case of MIMO type reception
Bitmap, with each bit indicating if the related spatial
stream is used for this STA
LSB related to SS 0
0: spatial stream not used for this reception
1: spatial stream used for this reception
<legal all>
*/
#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8
#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00
/* Description RECEIVE_USER_INFO_1_USER_RU_ALLOCATION
Field only valid in case of OFDMA uplink type reception
Indicates the RU number for this user
<legal 0-73>
*/
#define RECEIVE_USER_INFO_1_USER_RU_ALLOCATION_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_USER_RU_ALLOCATION_LSB 16
#define RECEIVE_USER_INFO_1_USER_RU_ALLOCATION_MASK 0x00ff0000
/* Description RECEIVE_USER_INFO_1_NSS
Number of Spatial Streams occupied by the User
<enum 0 1_spatial_stream>Single spatial stream
<enum 1 2_spatial_streams>2 spatial streams
<enum 2 3_spatial_streams>3 spatial streams
<enum 3 4_spatial_streams>4 spatial streams
<enum 4 5_spatial_streams>5 spatial streams
<enum 5 6_spatial_streams>6 spatial streams
<enum 6 7_spatial_streams>7 spatial streams
<enum 7 8_spatial_streams>8 spatial streams
*/
#define RECEIVE_USER_INFO_1_NSS_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_NSS_LSB 24
#define RECEIVE_USER_INFO_1_NSS_MASK 0x07000000
/* Description RECEIVE_USER_INFO_1_RESERVED_1B
<legal 0>
*/
#define RECEIVE_USER_INFO_1_RESERVED_1B_OFFSET 0x00000004
#define RECEIVE_USER_INFO_1_RESERVED_1B_LSB 27
#define RECEIVE_USER_INFO_1_RESERVED_1B_MASK 0xf8000000
#endif // _RECEIVE_USER_INFO_H_

558
hw/qca8074/v1/reo_descriptor_threshold_reached_status.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 threshold_index[1:0], reserved_2[31:2]
// 3 link_descriptor_counter0[23:0], reserved_3[31:24]
// 4 link_descriptor_counter1[23:0], reserved_4[31:24]
// 5 link_descriptor_counter2[23:0], reserved_5[31:24]
// 6 link_descriptor_counter_sum[25:0], reserved_6[31:26]
// 7 reserved_7[31:0]
// 8 reserved_8[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
struct reo_descriptor_threshold_reached_status {
struct uniform_reo_status_header status_header;
uint32_t threshold_index : 2, //[1:0]
reserved_2 : 30; //[31:2]
uint32_t link_descriptor_counter0 : 24, //[23:0]
reserved_3 : 8; //[31:24]
uint32_t link_descriptor_counter1 : 24, //[23:0]
reserved_4 : 8; //[31:24]
uint32_t link_descriptor_counter2 : 24, //[23:0]
reserved_5 : 8; //[31:24]
uint32_t link_descriptor_counter_sum : 26, //[25:0]
reserved_6 : 6; //[31:26]
uint32_t reserved_7 : 32; //[31:0]
uint32_t reserved_8 : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
threshold_index
The index of the threshold register whose value got
reached
<enum 0 reo_desc_counter0_threshold>
<enum 1 reo_desc_counter1_threshold>
<enum 2 reo_desc_counter2_threshold>
<enum 3 reo_desc_counter_sum_threshold>
<legal all>
reserved_2
<legal 0>
link_descriptor_counter0
Value of this counter at generation of this message
<legal all>
reserved_3
<legal 0>
link_descriptor_counter1
Value of this counter at generation of this message
<legal all>
reserved_4
<legal 0>
link_descriptor_counter2
Value of this counter at generation of this message
<legal all>
reserved_5
<legal 0>
link_descriptor_counter_sum
Value of this counter at generation of this message
<legal all>
reserved_6
<legal 0>
reserved_7
<legal 0>
reserved_8
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX
The index of the threshold register whose value got
reached
<enum 0 reo_desc_counter0_threshold>
<enum 1 reo_desc_counter1_threshold>
<enum 2 reo_desc_counter2_threshold>
<enum 3 reo_desc_counter_sum_threshold>
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM
Value of this counter at generation of this message
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_

488
hw/qca8074/v1/reo_flush_cache.h Normal file
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@@ -0,0 +1,488 @@
/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_FLUSH_CACHE_H_
#define _REO_FLUSH_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 flush_addr_31_0[31:0]
// 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
struct reo_flush_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_addr_31_0 : 32; //[31:0]
uint32_t flush_addr_39_32 : 8, //[7:0]
forward_all_mpdus_in_queue : 1, //[8]
release_cache_block_index : 1, //[9]
cache_block_resource_index : 2, //[11:10]
flush_without_invalidate : 1, //[12]
block_cache_usage_after_flush : 1, //[13]
flush_entire_cache : 1, //[14]
reserved_2b : 17; //[31:15]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
flush_addr_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
flush_addr_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
forward_all_mpdus_in_queue
Is only allowed to be set when the flush address
corresponds with a REO descriptor.
When set, REO shall first forward all the MPDUs held in
the indicated re-order queue, before flushing the descriptor
from the cache.
<legal all>
release_cache_block_index
Field not valid when Flush_entire_cache is set.
If SW has previously used a blocking resource that it
now wants to re-use for this command, this bit shall be set.
It prevents SW from having to send a separate
REO_UNBLOCK_CACHE command.
When set, HW will first release the blocking resource
(indicated in field 'Cache_block_resouce_index') before this
command gets executed.
If that resource was already unblocked, this will be
considered an error. This command will not be executed, and
an error shall be returned.
<legal all>
cache_block_resource_index
Field not valid when Flush_entire_cache is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this
(descriptor) address
<legal all>
flush_without_invalidate
Field not valid when Flush_entire_cache is set.
When set, REO shall flush the cache line contents from
the cache, but there is NO need to invalidate the cache line
entry... The contents in the cache can be maintained. This
feature can be used by SW (and DV) to get a current snapshot
of the contents in the cache
<legal all>
block_cache_usage_after_flush
Field not valid when Flush_entire_cache is set.
When set, REO shall block any cache accesses to this
address till explicitly unblocked.
Whenever SW sets this bit, SW shall also set bit
'Forward_all_mpdus_in_queue' to ensure all packets are
flushed out in order to make sure this queue desc is not in
one of the aging link lists. In case SW does not want to
flush the MPDUs in the queue, see the recipe description
below this TLV definition.
The 'blocking' index to be used for this is indicated in
field 'cache_block_resource_index'. If SW had previously
used this blocking resource and was not freed up yet, SW
shall first unblock that index (by setting bit
Release_cache_block_index) or use an unblock command.
If the resource indicated here was already blocked (and
did not get unblocked in this command), it is considered an
error scenario...
No flush shall happen. The status for this command shall
indicate error.
<legal all>
flush_entire_cache
When set, the entire cache shall be flushed. The entire
cache will also remain blocked, till the
'REO_UNBLOCK_COMMAND' is received with bit unblock type set
to unblock_cache. All other fields in this command are to be
ignored.
Note that flushing the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
reserved_2b
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0
#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0
#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff
/* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
Is only allowed to be set when the flush address
corresponds with a REO descriptor.
When set, REO shall first forward all the MPDUs held in
the indicated re-order queue, before flushing the descriptor
from the cache.
<legal all>
*/
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100
/* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
Field not valid when Flush_entire_cache is set.
If SW has previously used a blocking resource that it
now wants to re-use for this command, this bit shall be set.
It prevents SW from having to send a separate
REO_UNBLOCK_CACHE command.
When set, HW will first release the blocking resource
(indicated in field 'Cache_block_resouce_index') before this
command gets executed.
If that resource was already unblocked, this will be
considered an error. This command will not be executed, and
an error shall be returned.
<legal all>
*/
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9
#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200
/* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
Field not valid when Flush_entire_cache is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this
(descriptor) address
<legal all>
*/
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00
/* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
Field not valid when Flush_entire_cache is set.
When set, REO shall flush the cache line contents from
the cache, but there is NO need to invalidate the cache line
entry... The contents in the cache can be maintained. This
feature can be used by SW (and DV) to get a current snapshot
of the contents in the cache
<legal all>
*/
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12
#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000
/* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
Field not valid when Flush_entire_cache is set.
When set, REO shall block any cache accesses to this
address till explicitly unblocked.
Whenever SW sets this bit, SW shall also set bit
'Forward_all_mpdus_in_queue' to ensure all packets are
flushed out in order to make sure this queue desc is not in
one of the aging link lists. In case SW does not want to
flush the MPDUs in the queue, see the recipe description
below this TLV definition.
The 'blocking' index to be used for this is indicated in
field 'cache_block_resource_index'. If SW had previously
used this blocking resource and was not freed up yet, SW
shall first unblock that index (by setting bit
Release_cache_block_index) or use an unblock command.
If the resource indicated here was already blocked (and
did not get unblocked in this command), it is considered an
error scenario...
No flush shall happen. The status for this command shall
indicate error.
<legal all>
*/
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000
/* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
When set, the entire cache shall be flushed. The entire
cache will also remain blocked, till the
'REO_UNBLOCK_COMMAND' is received with bit unblock type set
to unblock_cache. All other fields in this command are to be
ignored.
Note that flushing the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
*/
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14
#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000
/* Description REO_FLUSH_CACHE_2_RESERVED_2B
<legal 0>
*/
#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008
#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15
#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000
/* Description REO_FLUSH_CACHE_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0
#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0
#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0
#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_FLUSH_CACHE_H_

697
hw/qca8074/v1/reo_flush_cache_status.h Normal file
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@@ -0,0 +1,697 @@
/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_FLUSH_CACHE_STATUS_H_
#define _REO_FLUSH_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], block_error_details[2:1], reserved_2a[7:3], cache_controller_flush_status_hit[8], cache_controller_flush_status_desc_type[11:9], cache_controller_flush_status_client_id[15:12], cache_controller_flush_status_error[17:16], cache_controller_flush_count[25:18], reserved_2b[31:26]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
struct reo_flush_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
block_error_details : 2, //[2:1]
reserved_2a : 5, //[7:3]
cache_controller_flush_status_hit: 1, //[8]
cache_controller_flush_status_desc_type: 3, //[11:9]
cache_controller_flush_status_client_id: 4, //[15:12]
cache_controller_flush_status_error: 2, //[17:16]
cache_controller_flush_count : 8, //[25:18]
reserved_2b : 6; //[31:26]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
Status for blocking resource handling
0: No error has been detected while executing this
command
1: an error in the blocking resource management was
detected
See field 'Block_error_details'
block_error_details
Field only valid when 'Error_detected' is set.
0: no blocking related error found
1: blocking resource was already in use
2: resource that was asked to be unblocked, was not
blocked
<legal 0-2>
reserved_2a
<legal 0>
cache_controller_flush_status_hit
The status that the cache controller returned for
executing the flush command
descriptor hit
1 = hit
0 = miss
<legal all>
cache_controller_flush_status_desc_type
The status that the cache controller returned for
executing the flush command
Descriptor type
FLOW_QUEUE_DESCRIPTOR                
3'd0
<legal all>
cache_controller_flush_status_client_id
The status that the cache controller returned for
executing the flush command
client ID
Module who made flush the request
In REO, this is always set to 0
<legal 0>
cache_controller_flush_status_error
The status that the cache controller returned for
executing the flush command
Error condition
2'b00: No error found
2'b01: HW IF still busy
2'b10: Line is currently locked. Used for the one line
flush command.
2'b11: At least one line is currently still locked. Used
for the cache flush command.
<legal all>
cache_controller_flush_count
The number of lines that were actually flushed out.
<legal all>
reserved_2b
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED
Status for blocking resource handling
0: No error has been detected while executing this
command
1: an error in the blocking resource management was
detected
See field 'Block_error_details'
*/
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS
Field only valid when 'Error_detected' is set.
0: no blocking related error found
1: blocking resource was already in use
2: resource that was asked to be unblocked, was not
blocked
<legal 0-2>
*/
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1
#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006
/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT
The status that the cache controller returned for
executing the flush command
descriptor hit
1 = hit
0 = miss
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE
The status that the cache controller returned for
executing the flush command
Descriptor type
FLOW_QUEUE_DESCRIPTOR                
3'd0
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID
The status that the cache controller returned for
executing the flush command
client ID
Module who made flush the request
In REO, this is always set to 0
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR
The status that the cache controller returned for
executing the flush command
Error condition
2'b00: No error found
2'b01: HW IF still busy
2'b10: Line is currently locked. Used for the one line
flush command.
2'b11: At least one line is currently still locked. Used
for the cache flush command.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT
The number of lines that were actually flushed out.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000
/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2B
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26
#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000
/* Description REO_FLUSH_CACHE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0
#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0
#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0
#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0
#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0
#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0
#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0
#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0
#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0
#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0
#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0
#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0
#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0
#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0
#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0
#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0
#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0
#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0
#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_FLUSH_CACHE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0
#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_FLUSH_CACHE_STATUS_H_

280
hw/qca8074/v1/reo_flush_queue.h Normal file
View File

@@ -0,0 +1,280 @@
/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_FLUSH_QUEUE_H_
#define _REO_FLUSH_QUEUE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 flush_desc_addr_31_0[31:0]
// 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], reserved_2a[31:11]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
struct reo_flush_queue {
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_desc_addr_31_0 : 32; //[31:0]
uint32_t flush_desc_addr_39_32 : 8, //[7:0]
block_desc_addr_usage_after_flush: 1, //[8]
block_resource_index : 2, //[10:9]
reserved_2a : 21; //[31:11]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
flush_desc_addr_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
flush_desc_addr_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
block_desc_addr_usage_after_flush
When set, REO shall not re-fetch this address till SW
explicitly unblocked this address
If the blocking resource was already used, this command
shall fail and an error is reported
<legal all>
block_resource_index
Field only valid when 'Block_desc_addr_usage_after_flush
' is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this address.
<legal all>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
Consumer: REO
Producer: SW
Address (lower 32 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0
#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
Consumer: REO
Producer: SW
Address (upper 8 bits) of the descriptor to flush
<legal all>
*/
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0
#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff
/* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
When set, REO shall not re-fetch this address till SW
explicitly unblocked this address
If the blocking resource was already used, this command
shall fail and an error is reported
<legal all>
*/
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100
/* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
Field only valid when 'Block_desc_addr_usage_after_flush
' is set.
Indicates which of the four blocking resources in REO
will be assigned for managing the blocking of this address.
<legal all>
*/
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9
#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600
/* Description REO_FLUSH_QUEUE_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 11
#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff800
/* Description REO_FLUSH_QUEUE_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0
#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0
#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0
#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_FLUSH_QUEUE_H_

472
hw/qca8074/v1/reo_flush_queue_status.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_FLUSH_QUEUE_STATUS_H_
#define _REO_FLUSH_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], reserved_2a[31:1]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
struct reo_flush_queue_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
reserved_2a : 31; //[31:1]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
Status of the blocking resource
0: No error has been detected while executing this
command
1: Error detected: The resource to be used for blocking
was already in use.
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED
Status of the blocking resource
0: No error has been detected while executing this
command
1: Error detected: The resource to be used for blocking
was already in use.
*/
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1
#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe
/* Description REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_FLUSH_QUEUE_STATUS_H_

319
hw/qca8074/v1/reo_flush_timeout_list.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
#define _REO_FLUSH_TIMEOUT_LIST_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 ac_timout_list[1:0], reserved_1[31:2]
// 2 minimum_release_desc_count[15:0], minimum_forward_buf_count[31:16]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
struct reo_flush_timeout_list {
struct uniform_reo_cmd_header cmd_header;
uint32_t ac_timout_list : 2, //[1:0]
reserved_1 : 30; //[31:2]
uint32_t minimum_release_desc_count : 16, //[15:0]
minimum_forward_buf_count : 16; //[31:16]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
ac_timout_list
Consumer: REO
Producer: SW
The AC_timeout list to be used for this command
<legal all>
reserved_1
<legal 0>
minimum_release_desc_count
Consumer: REO
Producer: SW
The minimum number of link descriptors requested to be
released. If set to 0, only buffer release counts seems to
be important... When set to very high value, likely the
entire timeout list will be exhausted before this count is
reached or maybe this count will not get reached. REO
however will stop here as it can not do anything else.
When both this field and field Minimum_forward_buf_count
are > 0, REO needs to meet both requirements. When both
entries are 0 (which should be a programming error), REO
does not need to do anything.
Note that this includes counts of MPDU link Desc as well
as MSDU link Desc. Where the count of MSDU link Desc is not
known to REO it's approximated by deriving from MSDU count
<legal all>
minimum_forward_buf_count
Consumer: REO
Producer: SW
The minimum number of buffer descriptors requested to be
passed on to the REO destination rings.
If set to 0, only descriptor release counts seems to be
important...
When set to very high value, likely the entire timeout
list will be exhausted before this count is reached or maybe
this count will not get reached. REO however will stop here
as it can not do anything else.
Note that REO does not know the exact buffer count. This
can be approximated by using the MSDU_COUNT
<legal all>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST
Consumer: REO
Producer: SW
The AC_timeout list to be used for this command
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003
/* Description REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2
#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc
/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT
Consumer: REO
Producer: SW
The minimum number of link descriptors requested to be
released. If set to 0, only buffer release counts seems to
be important... When set to very high value, likely the
entire timeout list will be exhausted before this count is
reached or maybe this count will not get reached. REO
however will stop here as it can not do anything else.
When both this field and field Minimum_forward_buf_count
are > 0, REO needs to meet both requirements. When both
entries are 0 (which should be a programming error), REO
does not need to do anything.
Note that this includes counts of MPDU link Desc as well
as MSDU link Desc. Where the count of MSDU link Desc is not
known to REO it's approximated by deriving from MSDU count
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff
/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT
Consumer: REO
Producer: SW
The minimum number of buffer descriptors requested to be
passed on to the REO destination rings.
If set to 0, only descriptor release counts seems to be
important...
When set to very high value, likely the entire timeout
list will be exhausted before this count is reached or maybe
this count will not get reached. REO however will stop here
as it can not do anything else.
Note that REO does not know the exact buffer count. This
can be approximated by using the MSDU_COUNT
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000
/* Description REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_FLUSH_TIMEOUT_LIST_H_

544
hw/qca8074/v1/reo_flush_timeout_list_status.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], timout_list_empty[1], reserved_2a[31:2]
// 3 release_desc_count[15:0], forward_buf_count[31:16]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
struct reo_flush_timeout_list_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
timout_list_empty : 1, //[1]
reserved_2a : 30; //[31:2]
uint32_t release_desc_count : 16, //[15:0]
forward_buf_count : 16; //[31:16]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
0: No error has been detected while executing this
command
1: command not properly executed and returned with an
error
NOTE: Current no error is defined, but field is put in
place to avoid data structure changes in future...
timout_list_empty
When set, REO has depleted the timeout list and all
entries are gone.
<legal all>
reserved_2a
<legal 0>
release_desc_count
Consumer: REO
Producer: SW
The number of link descriptors released
<legal all>
forward_buf_count
Consumer: REO
Producer: SW
The number of buffers forwarded to the REO destination
rings
<legal all>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED
0: No error has been detected while executing this
command
1: command not properly executed and returned with an
error
NOTE: Current no error is defined, but field is put in
place to avoid data structure changes in future...
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY
When set, REO has depleted the timeout list and all
entries are gone.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2
#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT
Consumer: REO
Producer: SW
The number of link descriptors released
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT
Consumer: REO
Producer: SW
The number of buffers forwarded to the REO destination
rings
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_

267
hw/qca8074/v1/reo_unblock_cache.h Normal file
View File

@@ -0,0 +1,267 @@
/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_UNBLOCK_CACHE_H_
#define _REO_UNBLOCK_CACHE_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_cmd_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct uniform_reo_cmd_header cmd_header;
// 1 unblock_type[0], cache_block_resource_index[2:1], reserved_1a[31:3]
// 2 reserved_2a[31:0]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
struct reo_unblock_cache {
struct uniform_reo_cmd_header cmd_header;
uint32_t unblock_type : 1, //[0]
cache_block_resource_index : 2, //[2:1]
reserved_1a : 29; //[31:3]
uint32_t reserved_2a : 32; //[31:0]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
};
/*
struct uniform_reo_cmd_header cmd_header
Consumer: REO
Producer: SW
Details for command execution tracking purposes.
unblock_type
Unblock type
<enum 0 unblock_resource_index> Unblock a block
resource, whose index is given in field
'cache_block_resource_index'.
If the indicated blocking resource is not in use (=> not
blocking an address at the moment), the command status will
indicate an error.
<enum 1 unblock_cache> The entire cache usage is
unblocked.
If the entire cache is not in a blocked mode at the
moment this command is received, the command status will
indicate an error.
Note that unlocking the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
cache_block_resource_index
Field not valid when field Unblock_type is set to
unblock_cache.
Indicates which of the four blocking resources in REO
should be released from blocking a (descriptor) address.
<legal all>
reserved_1a
<legal 0>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
*/
#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE
Unblock type
<enum 0 unblock_resource_index> Unblock a block
resource, whose index is given in field
'cache_block_resource_index'.
If the indicated blocking resource is not in use (=> not
blocking an address at the moment), the command status will
indicate an error.
<enum 1 unblock_cache> The entire cache usage is
unblocked.
If the entire cache is not in a blocked mode at the
moment this command is received, the command status will
indicate an error.
Note that unlocking the entire cache has no changes to
the current settings of the blocking resource settings
<legal all>
*/
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0
#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001
/* Description REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX
Field not valid when field Unblock_type is set to
unblock_cache.
Indicates which of the four blocking resources in REO
should be released from blocking a (descriptor) address.
<legal all>
*/
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1
#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006
/* Description REO_UNBLOCK_CACHE_1_RESERVED_1A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3
#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8
/* Description REO_UNBLOCK_CACHE_2_RESERVED_2A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0
#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_3_RESERVED_3A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0
#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_4_RESERVED_4A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_5_RESERVED_5A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0
#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_6_RESERVED_6A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_7_RESERVED_7A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0
#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_8_RESERVED_8A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff
#endif // _REO_UNBLOCK_CACHE_H_

517
hw/qca8074/v1/reo_unblock_cache_status.h Normal file
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@@ -0,0 +1,517 @@
/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
#define _REO_UNBLOCK_CACHE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 error_detected[0], unblock_type[1], reserved_2a[31:2]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
struct reo_unblock_cache_status {
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1, //[0]
unblock_type : 1, //[1]
reserved_2a : 30; //[31:2]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
error_detected
Status for blocking resource handling
0: No error has been detected while executing this
command
1: The blocking resource was not in use, and therefor it
could not be 'unblocked'
unblock_type
Reference to the type of Unblock command type...
<enum 0 unblock_resource_index> Unblock a blocking
resource
<enum 1 unblock_cache> The entire cache usage is
unblock.
<legal all>
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED
Status for blocking resource handling
0: No error has been detected while executing this
command
1: The blocking resource was not in use, and therefor it
could not be 'unblocked'
*/
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
/* Description REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE
Reference to the type of Unblock command type...
<enum 0 unblock_resource_index> Unblock a blocking
resource
<enum 1 unblock_cache> The entire cache usage is
unblock.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1
#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002
/* Description REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2
#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc
/* Description REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_UNBLOCK_CACHE_STATUS_H_

1502
hw/qca8074/v1/reo_update_rx_reo_queue.h Normal file
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447
hw/qca8074/v1/reo_update_rx_reo_queue_status.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#if !defined(__ASSEMBLER__)
#endif
#include "uniform_reo_status_header.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct uniform_reo_status_header status_header;
// 2 reserved_2a[31:0]
// 3 reserved_3a[31:0]
// 4 reserved_4a[31:0]
// 5 reserved_5a[31:0]
// 6 reserved_6a[31:0]
// 7 reserved_7a[31:0]
// 8 reserved_8a[31:0]
// 9 reserved_9a[31:0]
// 10 reserved_10a[31:0]
// 11 reserved_11a[31:0]
// 12 reserved_12a[31:0]
// 13 reserved_13a[31:0]
// 14 reserved_14a[31:0]
// 15 reserved_15a[31:0]
// 16 reserved_16a[31:0]
// 17 reserved_17a[31:0]
// 18 reserved_18a[31:0]
// 19 reserved_19a[31:0]
// 20 reserved_20a[31:0]
// 21 reserved_21a[31:0]
// 22 reserved_22a[31:0]
// 23 reserved_23a[31:0]
// 24 reserved_24a[27:0], looping_count[31:28]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
struct reo_update_rx_reo_queue_status {
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 32; //[31:0]
uint32_t reserved_3a : 32; //[31:0]
uint32_t reserved_4a : 32; //[31:0]
uint32_t reserved_5a : 32; //[31:0]
uint32_t reserved_6a : 32; //[31:0]
uint32_t reserved_7a : 32; //[31:0]
uint32_t reserved_8a : 32; //[31:0]
uint32_t reserved_9a : 32; //[31:0]
uint32_t reserved_10a : 32; //[31:0]
uint32_t reserved_11a : 32; //[31:0]
uint32_t reserved_12a : 32; //[31:0]
uint32_t reserved_13a : 32; //[31:0]
uint32_t reserved_14a : 32; //[31:0]
uint32_t reserved_15a : 32; //[31:0]
uint32_t reserved_16a : 32; //[31:0]
uint32_t reserved_17a : 32; //[31:0]
uint32_t reserved_18a : 32; //[31:0]
uint32_t reserved_19a : 32; //[31:0]
uint32_t reserved_20a : 32; //[31:0]
uint32_t reserved_21a : 32; //[31:0]
uint32_t reserved_22a : 32; //[31:0]
uint32_t reserved_23a : 32; //[31:0]
uint32_t reserved_24a : 28, //[27:0]
looping_count : 4; //[31:28]
};
/*
struct uniform_reo_status_header status_header
Consumer: SW
Producer: REO
Details that can link this status with the original
command. It also contains info on how long REO took to
execute this command.
reserved_2a
<legal 0>
reserved_3a
<legal 0>
reserved_4a
<legal 0>
reserved_5a
<legal 0>
reserved_6a
<legal 0>
reserved_7a
<legal 0>
reserved_8a
<legal 0>
reserved_9a
<legal 0>
reserved_10a
<legal 0>
reserved_11a
<legal 0>
reserved_12a
<legal 0>
reserved_13a
<legal 0>
reserved_14a
<legal 0>
reserved_15a
<legal 0>
reserved_16a
<legal 0>
reserved_17a
<legal 0>
reserved_18a
<legal 0>
reserved_19a
<legal 0>
reserved_20a
<legal 0>
reserved_21a
<legal 0>
reserved_22a
<legal 0>
reserved_23a
<legal 0>
reserved_24a
<legal 0>
looping_count
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
<legal 0>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
A count value that indicates the number of times the
producer of entries into this Ring has looped around the
ring.
At initialization time, this value is set to 0. On the
first loop, this value is set to 1. After the max value is
reached allowed by the number of bits for this field, the
count value continues with 0 again.
In case SW is the consumer of the ring entries, it can
use this field to figure out up to where the producer of
entries has created new entries. This eliminates the need to
check where the head pointer' of the ring is located once
the SW starts processing an interrupt indicating that new
entries have been put into this ring...
Also note that SW if it wants only needs to look at the
LSB bit of this count value.
<legal all>
*/
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
#endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_

1578
hw/qca8074/v1/rx_ppdu_end_user_stats.h Normal file
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224
hw/qca8074/v1/rx_ppdu_end_user_stats_ext.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
#define _RX_PPDU_END_USER_STATS_EXT_H_
#if !defined(__ASSEMBLER__)
#endif
#include "rx_rxpcu_classification_overview.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0 struct rx_rxpcu_classification_overview rxpcu_classification_details;
// 1 fcs_ok_bitmap_95_64[31:0]
// 2 fcs_ok_bitmap_127_96[31:0]
// 3 fcs_ok_bitmap_159_128[31:0]
// 4 fcs_ok_bitmap_191_160[31:0]
// 5 fcs_ok_bitmap_223_192[31:0]
// 6 fcs_ok_bitmap_255_224[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7
struct rx_ppdu_end_user_stats_ext {
struct rx_rxpcu_classification_overview rxpcu_classification_details;
uint32_t fcs_ok_bitmap_95_64 : 32; //[31:0]
uint32_t fcs_ok_bitmap_127_96 : 32; //[31:0]
uint32_t fcs_ok_bitmap_159_128 : 32; //[31:0]
uint32_t fcs_ok_bitmap_191_160 : 32; //[31:0]
uint32_t fcs_ok_bitmap_223_192 : 32; //[31:0]
uint32_t fcs_ok_bitmap_255_224 : 32; //[31:0]
};
/*
struct rx_rxpcu_classification_overview rxpcu_classification_details
Details related to what RXPCU classification types of
MPDUs have been received
fcs_ok_bitmap_95_64
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_127_96
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_159_128
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_191_160
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_223_192
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
fcs_ok_bitmap_255_224
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_OFFSET 0x00000000
#define RX_PPDU_END_USER_STATS_EXT_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004
#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008
#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c
#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010
#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014
#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff
/* Description RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224
Bitmap indicates in order of received MPDUs, which MPDUs
had an passing FCS or had an error.
1: FCS OK
0: FCS error
<legal all>
*/
#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018
#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0
#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff
#endif // _RX_PPDU_END_USER_STATS_EXT_H_

136
hw/qca8074/v1/rx_ppdu_start.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_PPDU_START_H_
#define _RX_PPDU_START_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 phy_ppdu_id[15:0], reserved_15[31:16]
// 1 sw_phy_meta_data[31:0]
// 2 ppdu_start_timestamp[31:0]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_PPDU_START 3
struct rx_ppdu_start {
uint32_t phy_ppdu_id : 16, //[15:0]
reserved_15 : 16; //[31:16]
uint32_t sw_phy_meta_data : 32; //[31:0]
uint32_t ppdu_start_timestamp : 32; //[31:0]
};
/*
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
reserved_15
Reserved
<legal 0>
sw_phy_meta_data
SW programmed Meta data provided by the PHY.
Can be used for SW to indicate the channel the device is
on.
ppdu_start_timestamp
Timestamp that indicates when the PPDU that contained
this MPDU started on the medium.
The timestamp is captured by the PHY ????TODO: Is this
comment correct ?
<legal all>
*/
/* Description RX_PPDU_START_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0
#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff
/* Description RX_PPDU_START_0_RESERVED_15
Reserved
<legal 0>
*/
#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000
#define RX_PPDU_START_0_RESERVED_15_LSB 16
#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000
/* Description RX_PPDU_START_1_SW_PHY_META_DATA
SW programmed Meta data provided by the PHY.
Can be used for SW to indicate the channel the device is
on.
*/
#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004
#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0
#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff
/* Description RX_PPDU_START_2_PPDU_START_TIMESTAMP
Timestamp that indicates when the PPDU that contained
this MPDU started on the medium.
The timestamp is captured by the PHY ????TODO: Is this
comment correct ?
<legal all>
*/
#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008
#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0
#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff
#endif // _RX_PPDU_START_H_

59
hw/qca8074/v1/rx_ppdu_start_user_info.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_PPDU_START_USER_INFO_H_
#define _RX_PPDU_START_USER_INFO_H_
#if !defined(__ASSEMBLER__)
#endif
#include "receive_user_info.h"
// ################ START SUMMARY #################
//
// Dword Fields
// 0-1 struct receive_user_info receive_user_info_details;
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 2
struct rx_ppdu_start_user_info {
struct receive_user_info receive_user_info_details;
};
/*
struct receive_user_info receive_user_info_details
Overview of receive parameters that the MAC needs to
prepend to every received MSDU/MPDU.
*/
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_OFFSET 0x00000000
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_LSB 0
#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_MASK 0xffffffff
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_OFFSET 0x00000004
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_LSB 0
#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_MASK 0xffffffff
#endif // _RX_PPDU_START_USER_INFO_H_

192
hw/qca8074/v1/rx_rxpcu_classification_overview.h Normal file
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/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
// DO NOT EDIT! This file is automatically generated
// These definitions are tied to a particular hardware layout
#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
#if !defined(__ASSEMBLER__)
#endif
// ################ START SUMMARY #################
//
// Dword Fields
// 0 filter_pass_mpdus[0], filter_pass_mpdus_fcs_ok[1], monitor_direct_mpdus[2], monitor_direct_mpdus_fcs_ok[3], monitor_other_mpdus[4], monitor_other_mpdus_fcs_ok[5], reserved_0[15:6], phy_ppdu_id[31:16]
//
// ################ END SUMMARY #################
#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
struct rx_rxpcu_classification_overview {
uint32_t filter_pass_mpdus : 1, //[0]
filter_pass_mpdus_fcs_ok : 1, //[1]
monitor_direct_mpdus : 1, //[2]
monitor_direct_mpdus_fcs_ok : 1, //[3]
monitor_other_mpdus : 1, //[4]
monitor_other_mpdus_fcs_ok : 1, //[5]
reserved_0 : 10, //[15:6]
phy_ppdu_id : 16; //[31:16]
};
/*
filter_pass_mpdus
When set, at least one Filter Pass MPDU has been
received. FCS might or might not have been passing
<legal all>
filter_pass_mpdus_fcs_ok
When set, at least one Filter Pass MPDU has been
received that has a correct FCS.
<legal all>
monitor_direct_mpdus
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing
<legal all>
monitor_direct_mpdus_fcs_ok
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
<legal all>
monitor_other_mpdus
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing
<legal all>
monitor_other_mpdus_fcs_ok
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
<legal all>
reserved_0
<legal 0>
phy_ppdu_id
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS
When set, at least one Filter Pass MPDU has been
received. FCS might or might not have been passing
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK
When set, at least one Filter Pass MPDU has been
received that has a correct FCS.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS
When set, at least one Monitor Direct MPDU has been
received. FCS might or might not have been passing
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK
When set, at least one Monitor Direct MPDU has been
received that has a correct FCS.
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0
<legal 0>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 6
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ffc0
/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID
A ppdu counter value that PHY increments for every PPDU
received. The counter value wraps around
<legal all>
*/
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16
#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000
#endif // _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_

19
hw/qca8074/v1/wcss_version.h Normal file
View File

@@ -0,0 +1,19 @@
/*
* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#define WCSS_VERSION 1019