fw-api: Add hw header files for QCA8074

Adding missing hardware header files required for QCA8074

CRs-Fixed: 2091297
Change-Id: Ia27b9e4ad161c6123ad66de422f7f35cb85b9f44

hw/qca8074/v1/receive_user_info.h

@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	phy_ppdu_id[15:0], user_rssi[23:16], pkt_type[27:24], stbc[28], sgi[30:29], reserved_0[31]
+//	1	rate_mcs[3:0], reception_type[5:4], receive_bandwidth[7:6], mimo_ss_bitmap[15:8], user_ru_allocation[23:16], nss[26:24], reserved_1b[31:27]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 2
+
+struct receive_user_info {
+             uint32_t phy_ppdu_id                     : 16, //[15:0]
+                      user_rssi                       :  8, //[23:16]
+                      pkt_type                        :  4, //[27:24]
+                      stbc                            :  1, //[28]
+                      sgi                             :  2, //[30:29]
+                      reserved_0                      :  1; //[31]
+             uint32_t rate_mcs                        :  4, //[3:0]
+                      reception_type                  :  2, //[5:4]
+                      receive_bandwidth               :  2, //[7:6]
+                      mimo_ss_bitmap                  :  8, //[15:8]
+                      user_ru_allocation              :  8, //[23:16]
+                      nss                             :  3, //[26:24]
+                      reserved_1b                     :  5; //[31:27]
+};
+
+/*
+
+phy_ppdu_id
+
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around
+
+			<legal all>
+
+user_rssi
+
+			RSSI for this user
+
+			Frequency domain RSSI measurement for this user. Based
+			on the channel estimate.
+
+
+
+			If PHY implementation runs into difficulties, the backup
+			is to reuse the previously notified RSSI values.
+
+			TODO PHY: request to update the text here based on the
+			latest design insights
+
+
+
+			<legal all>
+
+pkt_type
+
+			Packet type:
+
+
+
+			<enum 0 dot11a>802.11a PPDU type
+
+			<enum 1 dot11b>802.11b PPDU type
+
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+			<enum 3 dot11ac>802.11ac PPDU type
+
+			<enum 4 dot11ax>802.11ax PPDU type
+
+stbc
+
+			When set, use STBC transmission rates
+
+sgi
+
+			Field only valid when pkt type is HT, VHT or HE.
+
+
+
+			<enum 0     gi_0_8_us > Legacy normal GI.  Can also be
+			used for HE
+
+			<enum 1     gi_0_4_us > Legacy short GI.  Can also be
+			used for HE
+
+			<enum 2     gi_1_6_us > HE related GI
+
+			<enum 3     gi_3_2_us > HE related GI
+
+			<legal 0 - 3>
+
+reserved_0
+
+			<legal 0>
+
+rate_mcs
+
+			For details, refer to  MCS_TYPE description
+
+			<legal all>
+
+reception_type
+
+			Indicates what type of reception this is.
+
+			<enum 0     reception_type_SU >
+
+			<enum 1     reception_type_MU_MIMO >
+
+			<enum 2     reception_type_MU_OFDMA >
+
+			<enum 3     reception_type_MU_OFDMA_MIMO >
+
+			<legal all>
+
+receive_bandwidth
+
+			Full receive Bandwidth
+
+
+
+			<enum 0     full_rx_bw_20_mhz>
+
+			<enum 1      full_rx_bw_40_mhz>
+
+			<enum 2      full_rx_bw_80_mhz>
+
+			<enum 3      full_rx_bw_160_mhz>
+
+
+
+			<legal 0-3>
+
+mimo_ss_bitmap
+
+			Field only valid in case of MIMO type reception
+
+
+
+			Bitmap, with each bit indicating if the related spatial
+			stream is used for this STA
+
+			LSB related to SS 0
+
+
+
+			0: spatial stream not used for this reception
+
+			1: spatial stream used for this reception
+
+
+
+			<legal all>
+
+user_ru_allocation
+
+			Field only valid in case of OFDMA uplink type reception
+
+
+
+			Indicates the RU number for this user
+
+			<legal 0-73>
+
+nss
+
+			Number of Spatial Streams occupied by the User
+
+			<enum 0 1_spatial_stream>Single spatial stream
+
+			<enum 1 2_spatial_streams>2 spatial streams
+
+			<enum 2 3_spatial_streams>3 spatial streams
+
+			<enum 3 4_spatial_streams>4 spatial streams
+
+			<enum 4 5_spatial_streams>5 spatial streams
+
+			<enum 5 6_spatial_streams>6 spatial streams
+
+			<enum 6 7_spatial_streams>7 spatial streams
+
+			<enum 7 8_spatial_streams>8 spatial streams
+
+reserved_1b
+
+			<legal 0>
+*/
+
+
+/* Description		RECEIVE_USER_INFO_0_PHY_PPDU_ID
+
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around
+
+			<legal all>
+*/
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET                       0x00000000
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB                          0
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK                         0x0000ffff
+
+/* Description		RECEIVE_USER_INFO_0_USER_RSSI
+
+			RSSI for this user
+
+			Frequency domain RSSI measurement for this user. Based
+			on the channel estimate.
+
+
+
+			If PHY implementation runs into difficulties, the backup
+			is to reuse the previously notified RSSI values.
+
+			TODO PHY: request to update the text here based on the
+			latest design insights
+
+
+
+			<legal all>
+*/
+#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET                         0x00000000
+#define RECEIVE_USER_INFO_0_USER_RSSI_LSB                            16
+#define RECEIVE_USER_INFO_0_USER_RSSI_MASK                           0x00ff0000
+
+/* Description		RECEIVE_USER_INFO_0_PKT_TYPE
+
+			Packet type:
+
+
+
+			<enum 0 dot11a>802.11a PPDU type
+
+			<enum 1 dot11b>802.11b PPDU type
+
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+			<enum 3 dot11ac>802.11ac PPDU type
+
+			<enum 4 dot11ax>802.11ax PPDU type
+*/
+#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET                          0x00000000
+#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB                             24
+#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK                            0x0f000000
+
+/* Description		RECEIVE_USER_INFO_0_STBC
+
+			When set, use STBC transmission rates
+*/
+#define RECEIVE_USER_INFO_0_STBC_OFFSET                              0x00000000
+#define RECEIVE_USER_INFO_0_STBC_LSB                                 28
+#define RECEIVE_USER_INFO_0_STBC_MASK                                0x10000000
+
+/* Description		RECEIVE_USER_INFO_0_SGI
+
+			Field only valid when pkt type is HT, VHT or HE.
+
+
+
+			<enum 0     gi_0_8_us > Legacy normal GI.  Can also be
+			used for HE
+
+			<enum 1     gi_0_4_us > Legacy short GI.  Can also be
+			used for HE
+
+			<enum 2     gi_1_6_us > HE related GI
+
+			<enum 3     gi_3_2_us > HE related GI
+
+			<legal 0 - 3>
+*/
+#define RECEIVE_USER_INFO_0_SGI_OFFSET                               0x00000000
+#define RECEIVE_USER_INFO_0_SGI_LSB                                  29
+#define RECEIVE_USER_INFO_0_SGI_MASK                                 0x60000000
+
+/* Description		RECEIVE_USER_INFO_0_RESERVED_0
+
+			<legal 0>
+*/
+#define RECEIVE_USER_INFO_0_RESERVED_0_OFFSET                        0x00000000
+#define RECEIVE_USER_INFO_0_RESERVED_0_LSB                           31
+#define RECEIVE_USER_INFO_0_RESERVED_0_MASK                          0x80000000
+
+/* Description		RECEIVE_USER_INFO_1_RATE_MCS
+
+			For details, refer to  MCS_TYPE description
+
+			<legal all>
+*/
+#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET                          0x00000004
+#define RECEIVE_USER_INFO_1_RATE_MCS_LSB                             0
+#define RECEIVE_USER_INFO_1_RATE_MCS_MASK                            0x0000000f
+
+/* Description		RECEIVE_USER_INFO_1_RECEPTION_TYPE
+
+			Indicates what type of reception this is.
+
+			<enum 0     reception_type_SU >
+
+			<enum 1     reception_type_MU_MIMO >
+
+			<enum 2     reception_type_MU_OFDMA >
+
+			<enum 3     reception_type_MU_OFDMA_MIMO >
+
+			<legal all>
+*/
+#define RECEIVE_USER_INFO_1_RECEPTION_TYPE_OFFSET                    0x00000004
+#define RECEIVE_USER_INFO_1_RECEPTION_TYPE_LSB                       4
+#define RECEIVE_USER_INFO_1_RECEPTION_TYPE_MASK                      0x00000030
+
+/* Description		RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH
+
+			Full receive Bandwidth
+
+
+
+			<enum 0     full_rx_bw_20_mhz>
+
+			<enum 1      full_rx_bw_40_mhz>
+
+			<enum 2      full_rx_bw_80_mhz>
+
+			<enum 3      full_rx_bw_160_mhz>
+
+
+
+			<legal 0-3>
+*/
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET                 0x00000004
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB                    6
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK                   0x000000c0
+
+/* Description		RECEIVE_USER_INFO_1_MIMO_SS_BITMAP
+
+			Field only valid in case of MIMO type reception
+
+
+
+			Bitmap, with each bit indicating if the related spatial
+			stream is used for this STA
+
+			LSB related to SS 0
+
+
+
+			0: spatial stream not used for this reception
+
+			1: spatial stream used for this reception
+
+
+
+			<legal all>
+*/
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET                    0x00000004
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB                       8
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK                      0x0000ff00
+
+/* Description		RECEIVE_USER_INFO_1_USER_RU_ALLOCATION
+
+			Field only valid in case of OFDMA uplink type reception
+
+
+
+			Indicates the RU number for this user
+
+			<legal 0-73>
+*/
+#define RECEIVE_USER_INFO_1_USER_RU_ALLOCATION_OFFSET                0x00000004
+#define RECEIVE_USER_INFO_1_USER_RU_ALLOCATION_LSB                   16
+#define RECEIVE_USER_INFO_1_USER_RU_ALLOCATION_MASK                  0x00ff0000
+
+/* Description		RECEIVE_USER_INFO_1_NSS
+
+			Number of Spatial Streams occupied by the User
+
+			<enum 0 1_spatial_stream>Single spatial stream
+
+			<enum 1 2_spatial_streams>2 spatial streams
+
+			<enum 2 3_spatial_streams>3 spatial streams
+
+			<enum 3 4_spatial_streams>4 spatial streams
+
+			<enum 4 5_spatial_streams>5 spatial streams
+
+			<enum 5 6_spatial_streams>6 spatial streams
+
+			<enum 6 7_spatial_streams>7 spatial streams
+
+			<enum 7 8_spatial_streams>8 spatial streams
+*/
+#define RECEIVE_USER_INFO_1_NSS_OFFSET                               0x00000004
+#define RECEIVE_USER_INFO_1_NSS_LSB                                  24
+#define RECEIVE_USER_INFO_1_NSS_MASK                                 0x07000000
+
+/* Description		RECEIVE_USER_INFO_1_RESERVED_1B
+
+			<legal 0>
+*/
+#define RECEIVE_USER_INFO_1_RESERVED_1B_OFFSET                       0x00000004
+#define RECEIVE_USER_INFO_1_RESERVED_1B_LSB                          27
+#define RECEIVE_USER_INFO_1_RESERVED_1B_MASK                         0xf8000000
+
+
+#endif // _RECEIVE_USER_INFO_H_

hw/qca8074/v1/reo_descriptor_threshold_reached_status.h

@@ -0,0 +1,558 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	threshold_index[1:0], reserved_2[31:2]
+//	3	link_descriptor_counter0[23:0], reserved_3[31:24]
+//	4	link_descriptor_counter1[23:0], reserved_4[31:24]
+//	5	link_descriptor_counter2[23:0], reserved_5[31:24]
+//	6	link_descriptor_counter_sum[25:0], reserved_6[31:26]
+//	7	reserved_7[31:0]
+//	8	reserved_8[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
+
+struct reo_descriptor_threshold_reached_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t threshold_index                 :  2, //[1:0]
+                      reserved_2                      : 30; //[31:2]
+             uint32_t link_descriptor_counter0        : 24, //[23:0]
+                      reserved_3                      :  8; //[31:24]
+             uint32_t link_descriptor_counter1        : 24, //[23:0]
+                      reserved_4                      :  8; //[31:24]
+             uint32_t link_descriptor_counter2        : 24, //[23:0]
+                      reserved_5                      :  8; //[31:24]
+             uint32_t link_descriptor_counter_sum     : 26, //[25:0]
+                      reserved_6                      :  6; //[31:26]
+             uint32_t reserved_7                      : 32; //[31:0]
+             uint32_t reserved_8                      : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+			Consumer: SW
+
+			Producer: REO
+
+
+
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+threshold_index
+
+			The index of the threshold register whose value got
+			reached
+
+
+
+			<enum 0     reo_desc_counter0_threshold>
+
+			<enum 1     reo_desc_counter1_threshold>
+
+			<enum 2     reo_desc_counter2_threshold>
+
+			<enum 3     reo_desc_counter_sum_threshold>
+
+
+
+			<legal all>
+
+reserved_2
+
+			<legal 0>
+
+link_descriptor_counter0
+
+			Value of this counter at generation of this message
+
+			<legal all>
+
+reserved_3
+
+			<legal 0>
+
+link_descriptor_counter1
+
+			Value of this counter at generation of this message
+
+			<legal all>
+
+reserved_4
+
+			<legal 0>
+
+link_descriptor_counter2
+
+			Value of this counter at generation of this message
+
+			<legal all>
+
+reserved_5
+
+			<legal 0>
+
+link_descriptor_counter_sum
+
+			Value of this counter at generation of this message
+
+			<legal all>
+
+reserved_6
+
+			<legal 0>
+
+reserved_7
+
+			<legal 0>
+
+reserved_8
+
+			<legal 0>
+
+reserved_9a
+
+			<legal 0>
+
+reserved_10a
+
+			<legal 0>
+
+reserved_11a
+
+			<legal 0>
+
+reserved_12a
+
+			<legal 0>
+
+reserved_13a
+
+			<legal 0>
+
+reserved_14a
+
+			<legal 0>
+
+reserved_15a
+
+			<legal 0>
+
+reserved_16a
+
+			<legal 0>
+
+reserved_17a
+
+			<legal 0>
+
+reserved_18a
+
+			<legal 0>
+
+reserved_19a
+
+			<legal 0>
+
+reserved_20a
+
+			<legal 0>
+
+reserved_21a
+
+			<legal 0>
+
+reserved_22a
+
+			<legal 0>
+
+reserved_23a
+
+			<legal 0>
+
+reserved_24a
+
+			<legal 0>
+
+looping_count
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX
+
+			The index of the threshold register whose value got
+			reached
+
+
+
+			<enum 0     reo_desc_counter0_threshold>
+
+			<enum 1     reo_desc_counter1_threshold>
+
+			<enum 2     reo_desc_counter2_threshold>
+
+			<enum 3     reo_desc_counter_sum_threshold>
+
+
+
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET  0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB     2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK    0xfffffffc
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0
+
+			Value of this counter at generation of this message
+
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET  0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK    0xff000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1
+
+			Value of this counter at generation of this message
+
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET  0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK    0xff000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2
+
+			Value of this counter at generation of this message
+
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET  0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK    0xff000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM
+
+			Value of this counter at generation of this message
+
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET  0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB     26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK    0xfc000000
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET  0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK    0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET  0x00000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK    0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK   0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A
+
+			<legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description		REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_

hw/qca8074/v1/reo_flush_cache.h

@@ -0,0 +1,488 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	flush_addr_31_0[31:0]
+//	2	flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
+
+struct reo_flush_cache {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t flush_addr_31_0                 : 32; //[31:0]
+             uint32_t flush_addr_39_32                :  8, //[7:0]
+                      forward_all_mpdus_in_queue      :  1, //[8]
+                      release_cache_block_index       :  1, //[9]
+                      cache_block_resource_index      :  2, //[11:10]
+                      flush_without_invalidate        :  1, //[12]
+                      block_cache_usage_after_flush   :  1, //[13]
+                      flush_entire_cache              :  1, //[14]
+                      reserved_2b                     : 17; //[31:15]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Details for command execution tracking purposes.
+
+flush_addr_31_0
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (lower 32 bits) of the descriptor to flush
+
+			<legal all>
+
+flush_addr_39_32
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (upper 8 bits) of the descriptor to flush
+
+			<legal all>
+
+forward_all_mpdus_in_queue
+
+			Is only allowed to be set when the flush address
+			corresponds with a REO descriptor.
+
+
+
+			When set, REO shall first forward all the MPDUs held in
+			the indicated re-order queue, before flushing the descriptor
+			from the cache.
+
+			<legal all>
+
+release_cache_block_index
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			If SW has previously used a blocking resource that it
+			now wants to re-use for this command, this bit shall be set.
+			It prevents SW from having to send a separate
+			REO_UNBLOCK_CACHE command.
+
+
+
+			When set, HW will first release the blocking resource
+			(indicated in field 'Cache_block_resouce_index') before this
+			command gets executed.
+
+			If that resource was already unblocked, this will be
+			considered an error. This command will not be executed, and
+			an error shall be returned.
+
+			<legal all>
+
+cache_block_resource_index
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this
+			(descriptor) address
+
+			<legal all>
+
+flush_without_invalidate
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			When set, REO shall flush the cache line contents from
+			the cache, but there is NO need to invalidate the cache line
+			entry... The contents in the cache can be maintained. This
+			feature can be used by SW (and DV) to get a current snapshot
+			of the contents in the cache
+
+
+
+			<legal all>
+
+block_cache_usage_after_flush
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			When set, REO shall block any cache accesses to this
+			address till explicitly unblocked.
+
+
+
+			Whenever SW sets this bit, SW shall also set bit
+			'Forward_all_mpdus_in_queue' to ensure all packets are
+			flushed out in order to make sure this queue desc is not in
+			one of the aging link lists. In case SW does not want to
+			flush the MPDUs in the queue, see the recipe description
+			below this TLV definition.
+
+
+
+			The 'blocking' index to be used for this is indicated in
+			field 'cache_block_resource_index'. If SW had previously
+			used this blocking resource and was not freed up yet, SW
+			shall first unblock that index (by setting bit
+			Release_cache_block_index) or use an unblock command.
+
+
+
+			If the resource indicated here was already blocked (and
+			did not get unblocked in this command), it is considered an
+			error scenario...
+
+			No flush shall happen. The status for this command shall
+			indicate error.
+
+
+
+			<legal all>
+
+flush_entire_cache
+
+			When set, the entire cache shall be flushed. The entire
+			cache will also remain blocked, till the
+			'REO_UNBLOCK_COMMAND' is received with bit unblock type set
+			to unblock_cache. All other fields in this command are to be
+			ignored.
+
+
+
+			Note that flushing the entire cache has no changes to
+			the current settings of the blocking resource settings
+
+
+
+			<legal all>
+
+reserved_2b
+
+			<legal 0>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+*/
+
+#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET   0x00000000
+#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB      0
+#define REO_FLUSH_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK     0xffffffff
+
+/* Description		REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (lower 32 bits) of the descriptor to flush
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET                     0x00000004
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB                        0
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK                       0xffffffff
+
+/* Description		REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (upper 8 bits) of the descriptor to flush
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET                    0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB                       0
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK                      0x000000ff
+
+/* Description		REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
+
+			Is only allowed to be set when the flush address
+			corresponds with a REO descriptor.
+
+
+
+			When set, REO shall first forward all the MPDUs held in
+			the indicated re-order queue, before flushing the descriptor
+			from the cache.
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB             8
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK            0x00000100
+
+/* Description		REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			If SW has previously used a blocking resource that it
+			now wants to re-use for this command, this bit shall be set.
+			It prevents SW from having to send a separate
+			REO_UNBLOCK_CACHE command.
+
+
+
+			When set, HW will first release the blocking resource
+			(indicated in field 'Cache_block_resouce_index') before this
+			command gets executed.
+
+			If that resource was already unblocked, this will be
+			considered an error. This command will not be executed, and
+			an error shall be returned.
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET           0x00000008
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB              9
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK             0x00000200
+
+/* Description		REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this
+			(descriptor) address
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB             10
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK            0x00000c00
+
+/* Description		REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			When set, REO shall flush the cache line contents from
+			the cache, but there is NO need to invalidate the cache line
+			entry... The contents in the cache can be maintained. This
+			feature can be used by SW (and DV) to get a current snapshot
+			of the contents in the cache
+
+
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET            0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB               12
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK              0x00001000
+
+/* Description		REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
+
+			Field not valid when Flush_entire_cache is set.
+
+
+
+			When set, REO shall block any cache accesses to this
+			address till explicitly unblocked.
+
+
+
+			Whenever SW sets this bit, SW shall also set bit
+			'Forward_all_mpdus_in_queue' to ensure all packets are
+			flushed out in order to make sure this queue desc is not in
+			one of the aging link lists. In case SW does not want to
+			flush the MPDUs in the queue, see the recipe description
+			below this TLV definition.
+
+
+
+			The 'blocking' index to be used for this is indicated in
+			field 'cache_block_resource_index'. If SW had previously
+			used this blocking resource and was not freed up yet, SW
+			shall first unblock that index (by setting bit
+			Release_cache_block_index) or use an unblock command.
+
+
+
+			If the resource indicated here was already blocked (and
+			did not get unblocked in this command), it is considered an
+			error scenario...
+
+			No flush shall happen. The status for this command shall
+			indicate error.
+
+
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET       0x00000008
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB          13
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK         0x00002000
+
+/* Description		REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
+
+			When set, the entire cache shall be flushed. The entire
+			cache will also remain blocked, till the
+			'REO_UNBLOCK_COMMAND' is received with bit unblock type set
+			to unblock_cache. All other fields in this command are to be
+			ignored.
+
+
+
+			Note that flushing the entire cache has no changes to
+			the current settings of the blocking resource settings
+
+
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB                     14
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK                    0x00004000
+
+/* Description		REO_FLUSH_CACHE_2_RESERVED_2B
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET                         0x00000008
+#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB                            15
+#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK                           0xffff8000
+
+/* Description		REO_FLUSH_CACHE_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET                         0x0000000c
+#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB                            0
+#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET                         0x00000010
+#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB                            0
+#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET                         0x00000014
+#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB                            0
+#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET                         0x00000018
+#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB                            0
+#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET                         0x0000001c
+#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB                            0
+#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_CACHE_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET                         0x00000020
+#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB                            0
+#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK                           0xffffffff
+
+
+#endif // _REO_FLUSH_CACHE_H_

hw/qca8074/v1/reo_flush_cache_status.h

@@ -0,0 +1,697 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], block_error_details[2:1], reserved_2a[7:3], cache_controller_flush_status_hit[8], cache_controller_flush_status_desc_type[11:9], cache_controller_flush_status_client_id[15:12], cache_controller_flush_status_error[17:16], cache_controller_flush_count[25:18], reserved_2b[31:26]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
+
+struct reo_flush_cache_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      block_error_details             :  2, //[2:1]
+                      reserved_2a                     :  5, //[7:3]
+                      cache_controller_flush_status_hit:  1, //[8]
+                      cache_controller_flush_status_desc_type:  3, //[11:9]
+                      cache_controller_flush_status_client_id:  4, //[15:12]
+                      cache_controller_flush_status_error:  2, //[17:16]
+                      cache_controller_flush_count    :  8, //[25:18]
+                      reserved_2b                     :  6; //[31:26]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+			Consumer: SW
+
+			Producer: REO
+
+
+
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+
+			Status for blocking resource handling
+
+
+
+			0: No error has been detected while executing this
+			command
+
+			1: an error in the blocking resource management was
+			detected
+
+			See field 'Block_error_details'
+
+block_error_details
+
+			Field only valid when 'Error_detected' is set.
+
+			0: no blocking related error found
+
+			1: blocking resource was already in use
+
+			2: resource that was asked to be unblocked, was not
+			blocked
+
+			<legal 0-2>
+
+reserved_2a
+
+			<legal 0>
+
+cache_controller_flush_status_hit
+
+			The status that the cache controller returned for
+			executing the flush command
+
+
+
+			descriptor hit
+
+			1 = hit
+
+			0 = miss
+
+			<legal all>
+
+cache_controller_flush_status_desc_type
+
+			The status that the cache controller returned for
+			executing the flush command
+
+			Descriptor type
+
+			FLOW_QUEUE_DESCRIPTOR                
+			3'd0
+
+
+			 <legal all>
+
+cache_controller_flush_status_client_id
+
+			The status that the cache controller returned for
+			executing the flush command
+
+
+
+			client ID
+
+			Module who made flush the request
+
+
+
+			In REO, this is always set to 0
+
+			<legal 0>
+
+cache_controller_flush_status_error
+
+			The status that the cache controller returned for
+			executing the flush command
+
+
+
+			Error condition
+
+			2'b00: No error found
+
+			2'b01: HW IF still busy
+
+			2'b10: Line is currently locked. Used for the one line
+			flush command.
+
+			2'b11: At least one line is currently still locked. Used
+			for the cache flush command.
+
+
+
+			<legal all>
+
+cache_controller_flush_count
+
+			The number of lines that were actually flushed out.
+
+			<legal all>
+
+reserved_2b
+
+			<legal 0>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+
+reserved_9a
+
+			<legal 0>
+
+reserved_10a
+
+			<legal 0>
+
+reserved_11a
+
+			<legal 0>
+
+reserved_12a
+
+			<legal 0>
+
+reserved_13a
+
+			<legal 0>
+
+reserved_14a
+
+			<legal 0>
+
+reserved_15a
+
+			<legal 0>
+
+reserved_16a
+
+			<legal 0>
+
+reserved_17a
+
+			<legal 0>
+
+reserved_18a
+
+			<legal 0>
+
+reserved_19a
+
+			<legal 0>
+
+reserved_20a
+
+			<legal 0>
+
+reserved_21a
+
+			<legal 0>
+
+reserved_22a
+
+			<legal 0>
+
+reserved_23a
+
+			<legal 0>
+
+reserved_24a
+
+			<legal 0>
+
+looping_count
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+
+#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED
+
+			Status for blocking resource handling
+
+
+
+			0: No error has been detected while executing this
+			command
+
+			1: an error in the blocking resource management was
+			detected
+
+			See field 'Block_error_details'
+*/
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET               0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB                  0
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK                 0x00000001
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS
+
+			Field only valid when 'Error_detected' is set.
+
+			0: no blocking related error found
+
+			1: blocking resource was already in use
+
+			2: resource that was asked to be unblocked, was not
+			blocked
+
+			<legal 0-2>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB             1
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK            0x00000006
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB                     3
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK                    0x000000f8
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT
+
+			The status that the cache controller returned for
+			executing the flush command
+
+
+
+			descriptor hit
+
+			1 = hit
+
+			0 = miss
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE
+
+			The status that the cache controller returned for
+			executing the flush command
+
+			Descriptor type
+
+			FLOW_QUEUE_DESCRIPTOR                
+			3'd0
+
+
+			 <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID
+
+			The status that the cache controller returned for
+			executing the flush command
+
+
+
+			client ID
+
+			Module who made flush the request
+
+
+
+			In REO, this is always set to 0
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR
+
+			The status that the cache controller returned for
+			executing the flush command
+
+
+
+			Error condition
+
+			2'b00: No error found
+
+			2'b01: HW IF still busy
+
+			2'b10: Line is currently locked. Used for the one line
+			flush command.
+
+			2'b11: At least one line is currently still locked. Used
+			for the cache flush command.
+
+
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT
+
+			The number of lines that were actually flushed out.
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB    18
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK   0x03fc0000
+
+/* Description		REO_FLUSH_CACHE_STATUS_2_RESERVED_2B
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB                     26
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK                    0xfc000000
+
+/* Description		REO_FLUSH_CACHE_STATUS_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_9_RESERVED_9A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET                  0x00000024
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_10_RESERVED_10A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET                0x00000028
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_11_RESERVED_11A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET                0x0000002c
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_12_RESERVED_12A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET                0x00000030
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_13_RESERVED_13A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET                0x00000034
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_14_RESERVED_14A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET                0x00000038
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_15_RESERVED_15A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET                0x0000003c
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_16_RESERVED_16A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET                0x00000040
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_17_RESERVED_17A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET                0x00000044
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_18_RESERVED_18A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET                0x00000048
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_19_RESERVED_19A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET                0x0000004c
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_20_RESERVED_20A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET                0x00000050
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_21_RESERVED_21A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET                0x00000054
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_22_RESERVED_22A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET                0x00000058
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_23_RESERVED_23A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET                0x0000005c
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_24_RESERVED_24A
+
+			<legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET                0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK                  0x0fffffff
+
+/* Description		REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET               0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB                  28
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK                 0xf0000000
+
+
+#endif // _REO_FLUSH_CACHE_STATUS_H_

hw/qca8074/v1/reo_flush_queue.h

@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	flush_desc_addr_31_0[31:0]
+//	2	flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], reserved_2a[31:11]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
+
+struct reo_flush_queue {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t flush_desc_addr_31_0            : 32; //[31:0]
+             uint32_t flush_desc_addr_39_32           :  8, //[7:0]
+                      block_desc_addr_usage_after_flush:  1, //[8]
+                      block_resource_index            :  2, //[10:9]
+                      reserved_2a                     : 21; //[31:11]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Details for command execution tracking purposes.
+
+flush_desc_addr_31_0
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (lower 32 bits) of the descriptor to flush
+
+			<legal all>
+
+flush_desc_addr_39_32
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (upper 8 bits) of the descriptor to flush
+
+			<legal all>
+
+block_desc_addr_usage_after_flush
+
+			When set, REO shall not re-fetch this address till SW
+			explicitly unblocked this address
+
+
+
+			If the blocking resource was already used, this command
+			shall fail and an error is reported
+
+
+
+			<legal all>
+
+block_resource_index
+
+			Field only valid when 'Block_desc_addr_usage_after_flush
+			' is set.
+
+
+
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this address.
+
+			<legal all>
+
+reserved_2a
+
+			<legal 0>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+*/
+
+#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET   0x00000000
+#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB      0
+#define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK     0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (lower 32 bits) of the descriptor to flush
+
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET                0x00000004
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB                   0
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (upper 8 bits) of the descriptor to flush
+
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET               0x00000008
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB                  0
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK                 0x000000ff
+
+/* Description		REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
+
+			When set, REO shall not re-fetch this address till SW
+			explicitly unblocked this address
+
+
+
+			If the blocking resource was already used, this command
+			shall fail and an error is reported
+
+
+
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET   0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB      8
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK     0x00000100
+
+/* Description		REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
+
+			Field only valid when 'Block_desc_addr_usage_after_flush
+			' is set.
+
+
+
+			Indicates which of the four blocking resources in REO
+			will be assigned for managing the blocking of this address.
+
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET                0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB                   9
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK                  0x00000600
+
+/* Description		REO_FLUSH_QUEUE_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET                         0x00000008
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB                            11
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK                           0xfffff800
+
+/* Description		REO_FLUSH_QUEUE_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET                         0x0000000c
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB                            0
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET                         0x00000010
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB                            0
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET                         0x00000014
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB                            0
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET                         0x00000018
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB                            0
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET                         0x0000001c
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB                            0
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK                           0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET                         0x00000020
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB                            0
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK                           0xffffffff
+
+
+#endif // _REO_FLUSH_QUEUE_H_

hw/qca8074/v1/reo_flush_queue_status.h

@@ -0,0 +1,472 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], reserved_2a[31:1]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
+
+struct reo_flush_queue_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      reserved_2a                     : 31; //[31:1]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+			Consumer: SW
+
+			Producer: REO
+
+
+
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+
+			Status of the blocking resource
+
+			0: No error has been detected while executing this
+			command
+
+			1: Error detected: The resource to be used for blocking
+			was already in use.
+
+reserved_2a
+
+			<legal 0>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+
+reserved_9a
+
+			<legal 0>
+
+reserved_10a
+
+			<legal 0>
+
+reserved_11a
+
+			<legal 0>
+
+reserved_12a
+
+			<legal 0>
+
+reserved_13a
+
+			<legal 0>
+
+reserved_14a
+
+			<legal 0>
+
+reserved_15a
+
+			<legal 0>
+
+reserved_16a
+
+			<legal 0>
+
+reserved_17a
+
+			<legal 0>
+
+reserved_18a
+
+			<legal 0>
+
+reserved_19a
+
+			<legal 0>
+
+reserved_20a
+
+			<legal 0>
+
+reserved_21a
+
+			<legal 0>
+
+reserved_22a
+
+			<legal 0>
+
+reserved_23a
+
+			<legal 0>
+
+reserved_24a
+
+			<legal 0>
+
+looping_count
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+
+#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED
+
+			Status of the blocking resource
+
+			0: No error has been detected while executing this
+			command
+
+			1: Error detected: The resource to be used for blocking
+			was already in use.
+*/
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET               0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB                  0
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK                 0x00000001
+
+/* Description		REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET                  0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB                     1
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK                    0xfffffffe
+
+/* Description		REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET                  0x00000024
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET                0x00000028
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET                0x0000002c
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET                0x00000030
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET                0x00000034
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET                0x00000038
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET                0x0000003c
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET                0x00000040
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET                0x00000044
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET                0x00000048
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET                0x0000004c
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET                0x00000050
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET                0x00000054
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET                0x00000058
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET                0x0000005c
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK                  0xffffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A
+
+			<legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET                0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK                  0x0fffffff
+
+/* Description		REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET               0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB                  28
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK                 0xf0000000
+
+
+#endif // _REO_FLUSH_QUEUE_STATUS_H_

hw/qca8074/v1/reo_flush_timeout_list.h

@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	ac_timout_list[1:0], reserved_1[31:2]
+//	2	minimum_release_desc_count[15:0], minimum_forward_buf_count[31:16]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
+
+struct reo_flush_timeout_list {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t ac_timout_list                  :  2, //[1:0]
+                      reserved_1                      : 30; //[31:2]
+             uint32_t minimum_release_desc_count      : 16, //[15:0]
+                      minimum_forward_buf_count       : 16; //[31:16]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Details for command execution tracking purposes.
+
+ac_timout_list
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The AC_timeout list to be used for this command
+
+			<legal all>
+
+reserved_1
+
+			<legal 0>
+
+minimum_release_desc_count
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The minimum number of link descriptors requested to be
+			released. If set to 0, only buffer release counts seems to
+			be important... When set to very high value, likely the
+			entire timeout list will be exhausted before this count is
+			reached or maybe this count will not get reached. REO
+			however will stop here as it can not do anything else.
+
+
+
+			When both this field and field Minimum_forward_buf_count
+			are > 0, REO needs to meet both requirements. When both
+			entries are 0 (which should be a programming error), REO
+			does not need to do anything.
+
+
+
+			Note that this includes counts of MPDU link Desc as well
+			as MSDU link Desc. Where the count of MSDU link Desc is not
+			known to REO it's approximated by deriving from MSDU count
+
+			<legal all>
+
+minimum_forward_buf_count
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The minimum number of buffer descriptors requested to be
+			passed on to the REO destination rings.
+
+
+
+			If set to 0, only descriptor release counts seems to be
+			important...
+
+
+
+			When set to very high value, likely the entire timeout
+			list will be exhausted before this count is reached or maybe
+			this count will not get reached. REO however will stop here
+			as it can not do anything else.
+
+
+
+			Note that REO does not know the exact buffer count. This
+			can be approximated by using the MSDU_COUNT
+
+			<legal all>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+*/
+
+#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The AC_timeout list to be used for this command
+
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET               0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB                  0
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK                 0x00000003
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET                   0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB                      2
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK                     0xfffffffc
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The minimum number of link descriptors requested to be
+			released. If set to 0, only buffer release counts seems to
+			be important... When set to very high value, likely the
+			entire timeout list will be exhausted before this count is
+			reached or maybe this count will not get reached. REO
+			however will stop here as it can not do anything else.
+
+
+
+			When both this field and field Minimum_forward_buf_count
+			are > 0, REO needs to meet both requirements. When both
+			entries are 0 (which should be a programming error), REO
+			does not need to do anything.
+
+
+
+			Note that this includes counts of MPDU link Desc as well
+			as MSDU link Desc. Where the count of MSDU link Desc is not
+			known to REO it's approximated by deriving from MSDU count
+
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET   0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB      0
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK     0x0000ffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The minimum number of buffer descriptors requested to be
+			passed on to the REO destination rings.
+
+
+
+			If set to 0, only descriptor release counts seems to be
+			important...
+
+
+
+			When set to very high value, likely the entire timeout
+			list will be exhausted before this count is reached or maybe
+			this count will not get reached. REO however will stop here
+			as it can not do anything else.
+
+
+
+			Note that REO does not know the exact buffer count. This
+			can be approximated by using the MSDU_COUNT
+
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET    0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB       16
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK      0xffff0000
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK                    0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK                    0xffffffff
+
+
+#endif // _REO_FLUSH_TIMEOUT_LIST_H_

hw/qca8074/v1/reo_flush_timeout_list_status.h

@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], timout_list_empty[1], reserved_2a[31:2]
+//	3	release_desc_count[15:0], forward_buf_count[31:16]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
+
+struct reo_flush_timeout_list_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      timout_list_empty               :  1, //[1]
+                      reserved_2a                     : 30; //[31:2]
+             uint32_t release_desc_count              : 16, //[15:0]
+                      forward_buf_count               : 16; //[31:16]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+			Consumer: SW
+
+			Producer: REO
+
+
+
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+
+			0: No error has been detected while executing this
+			command
+
+			1: command not properly executed and returned with an
+			error
+
+
+
+			NOTE: Current no error is defined, but field is put in
+			place to avoid data structure changes in future...
+
+timout_list_empty
+
+			When set, REO has depleted the timeout list and all
+			entries are gone.
+
+			<legal all>
+
+reserved_2a
+
+			<legal 0>
+
+release_desc_count
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The number of link descriptors released
+
+			<legal all>
+
+forward_buf_count
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The number of buffers forwarded to the REO destination
+			rings
+
+			<legal all>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+
+reserved_9a
+
+			<legal 0>
+
+reserved_10a
+
+			<legal 0>
+
+reserved_11a
+
+			<legal 0>
+
+reserved_12a
+
+			<legal 0>
+
+reserved_13a
+
+			<legal 0>
+
+reserved_14a
+
+			<legal 0>
+
+reserved_15a
+
+			<legal 0>
+
+reserved_16a
+
+			<legal 0>
+
+reserved_17a
+
+			<legal 0>
+
+reserved_18a
+
+			<legal 0>
+
+reserved_19a
+
+			<legal 0>
+
+reserved_20a
+
+			<legal 0>
+
+reserved_21a
+
+			<legal 0>
+
+reserved_22a
+
+			<legal 0>
+
+reserved_23a
+
+			<legal 0>
+
+reserved_24a
+
+			<legal 0>
+
+looping_count
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED
+
+			0: No error has been detected while executing this
+			command
+
+			1: command not properly executed and returned with an
+			error
+
+
+
+			NOTE: Current no error is defined, but field is put in
+			place to avoid data structure changes in future...
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET        0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB           0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK          0x00000001
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY
+
+			When set, REO has depleted the timeout list and all
+			entries are gone.
+
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET     0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB        1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK       0x00000002
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET           0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB              2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK             0xfffffffc
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The number of link descriptors released
+
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET    0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB       0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK      0x0000ffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			The number of buffers forwarded to the REO destination
+			rings
+
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET     0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB        16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK       0xffff0000
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET           0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET           0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET           0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET           0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET           0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET           0x00000024
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK             0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET         0x00000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET         0x0000002c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET         0x00000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET         0x00000034
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET         0x00000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET         0x0000003c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET         0x00000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET         0x00000044
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET         0x00000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET         0x0000004c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET         0x00000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET         0x00000054
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET         0x00000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET         0x0000005c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK           0xffffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A
+
+			<legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET         0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK           0x0fffffff
+
+/* Description		REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET        0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB           28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK          0xf0000000
+
+
+#endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_

hw/qca8074/v1/reo_unblock_cache.h

@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	unblock_type[0], cache_block_resource_index[2:1], reserved_1a[31:3]
+//	2	reserved_2a[31:0]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
+
+struct reo_unblock_cache {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t unblock_type                    :  1, //[0]
+                      cache_block_resource_index      :  2, //[2:1]
+                      reserved_1a                     : 29; //[31:3]
+             uint32_t reserved_2a                     : 32; //[31:0]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Details for command execution tracking purposes.
+
+unblock_type
+
+			Unblock type
+
+
+
+			<enum 0 unblock_resource_index> Unblock a block
+			resource, whose index is given in field
+			'cache_block_resource_index'.
+
+			If the indicated blocking resource is not in use (=> not
+			blocking an address at the moment), the command status will
+			indicate an error.
+
+
+
+			<enum 1 unblock_cache> The entire cache usage is
+			unblocked.
+
+			If the entire cache is not in a blocked mode at the
+			moment this command is received, the command status will
+			indicate an error.
+
+			Note that unlocking the entire cache has no changes to
+			the current settings of the blocking resource settings
+
+
+
+			<legal all>
+
+cache_block_resource_index
+
+			Field not valid when field Unblock_type is set to
+			unblock_cache.
+
+
+
+			Indicates which of the four blocking resources in REO
+			should be released from blocking a (descriptor) address.
+
+			<legal all>
+
+reserved_1a
+
+			<legal 0>
+
+reserved_2a
+
+			<legal 0>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+*/
+
+#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB    0
+#define REO_UNBLOCK_CACHE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK   0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE
+
+			Unblock type
+
+
+
+			<enum 0 unblock_resource_index> Unblock a block
+			resource, whose index is given in field
+			'cache_block_resource_index'.
+
+			If the indicated blocking resource is not in use (=> not
+			blocking an address at the moment), the command status will
+			indicate an error.
+
+
+
+			<enum 1 unblock_cache> The entire cache usage is
+			unblocked.
+
+			If the entire cache is not in a blocked mode at the
+			moment this command is received, the command status will
+			indicate an error.
+
+			Note that unlocking the entire cache has no changes to
+			the current settings of the blocking resource settings
+
+
+
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET                      0x00000004
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB                         0
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK                        0x00000001
+
+/* Description		REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX
+
+			Field not valid when field Unblock_type is set to
+			unblock_cache.
+
+
+
+			Indicates which of the four blocking resources in REO
+			should be released from blocking a (descriptor) address.
+
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET        0x00000004
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB           1
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK          0x00000006
+
+/* Description		REO_UNBLOCK_CACHE_1_RESERVED_1A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET                       0x00000004
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB                          3
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK                         0xfffffff8
+
+/* Description		REO_UNBLOCK_CACHE_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET                       0x00000008
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB                          0
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET                       0x0000000c
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB                          0
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET                       0x00000010
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB                          0
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET                       0x00000014
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB                          0
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET                       0x00000018
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB                          0
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET                       0x0000001c
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB                          0
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK                         0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET                       0x00000020
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB                          0
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK                         0xffffffff
+
+
+#endif // _REO_UNBLOCK_CACHE_H_

hw/qca8074/v1/reo_unblock_cache_status.h

@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	error_detected[0], unblock_type[1], reserved_2a[31:2]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
+
+struct reo_unblock_cache_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1, //[0]
+                      unblock_type                    :  1, //[1]
+                      reserved_2a                     : 30; //[31:2]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+			Consumer: SW
+
+			Producer: REO
+
+
+
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+error_detected
+
+			Status for blocking resource handling
+
+
+
+			0: No error has been detected while executing this
+			command
+
+			1: The blocking resource was not in use, and therefor it
+			could not be 'unblocked'
+
+unblock_type
+
+			Reference to the type of Unblock command type...
+
+
+
+			<enum 0 unblock_resource_index> Unblock a blocking
+			resource
+
+
+
+			<enum 1 unblock_cache> The entire cache usage is
+			unblock.
+
+
+
+			<legal all>
+
+reserved_2a
+
+			<legal 0>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+
+reserved_9a
+
+			<legal 0>
+
+reserved_10a
+
+			<legal 0>
+
+reserved_11a
+
+			<legal 0>
+
+reserved_12a
+
+			<legal 0>
+
+reserved_13a
+
+			<legal 0>
+
+reserved_14a
+
+			<legal 0>
+
+reserved_15a
+
+			<legal 0>
+
+reserved_16a
+
+			<legal 0>
+
+reserved_17a
+
+			<legal 0>
+
+reserved_18a
+
+			<legal 0>
+
+reserved_19a
+
+			<legal 0>
+
+reserved_20a
+
+			<legal 0>
+
+reserved_21a
+
+			<legal 0>
+
+reserved_22a
+
+			<legal 0>
+
+reserved_23a
+
+			<legal 0>
+
+reserved_24a
+
+			<legal 0>
+
+looping_count
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+
+#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED
+
+			Status for blocking resource handling
+
+
+
+			0: No error has been detected while executing this
+			command
+
+			1: The blocking resource was not in use, and therefor it
+			could not be 'unblocked'
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET             0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB                0
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK               0x00000001
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE
+
+			Reference to the type of Unblock command type...
+
+
+
+			<enum 0 unblock_resource_index> Unblock a blocking
+			resource
+
+
+
+			<enum 1 unblock_cache> The entire cache usage is
+			unblock.
+
+
+
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET               0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB                  1
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK                 0x00000002
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET                0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB                   2
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK                  0xfffffffc
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET                0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET                0x00000010
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET                0x00000014
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET                0x00000018
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET                0x0000001c
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET                0x00000020
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET                0x00000024
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK                  0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET              0x00000028
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET              0x0000002c
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET              0x00000030
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET              0x00000034
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET              0x00000038
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET              0x0000003c
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET              0x00000040
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET              0x00000044
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET              0x00000048
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET              0x0000004c
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET              0x00000050
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET              0x00000054
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET              0x00000058
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET              0x0000005c
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK                0xffffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A
+
+			<legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET              0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK                0x0fffffff
+
+/* Description		REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET             0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB                28
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK               0xf0000000
+
+
+#endif // _REO_UNBLOCK_CACHE_STATUS_H_

hw/qca8074/v1/reo_update_rx_reo_queue.h

@@ -0,0 +1,1502 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	rx_reo_queue_desc_addr_31_0[31:0]
+//	2	rx_reo_queue_desc_addr_39_32[7:0], update_receive_queue_number[8], update_vld[9], update_associated_link_descriptor_counter[10], update_disable_duplicate_detection[11], update_soft_reorder_enable[12], update_ac[13], update_bar[14], update_rty[15], update_chk_2k_mode[16], update_oor_mode[17], update_ba_window_size[18], update_pn_check_needed[19], update_pn_shall_be_even[20], update_pn_shall_be_uneven[21], update_pn_handling_enable[22], update_pn_size[23], update_ignore_ampdu_flag[24], update_svld[25], update_ssn[26], update_seq_2k_error_detected_flag[27], update_pn_error_detected_flag[28], update_pn_valid[29], update_pn[30], reserved_2a[31]
+//	3	receive_queue_number[15:0], vld[16], associated_link_descriptor_counter[18:17], disable_duplicate_detection[19], soft_reorder_enable[20], ac[22:21], bar[23], rty[24], chk_2k_mode[25], oor_mode[26], pn_check_needed[27], pn_shall_be_even[28], pn_shall_be_uneven[29], pn_handling_enable[30], ignore_ampdu_flag[31]
+//	4	ba_window_size[7:0], pn_size[9:8], svld[10], ssn[22:11], seq_2k_error_detected_flag[23], pn_error_detected_flag[24], pn_valid[25], reserved_4a[31:26]
+//	5	pn_31_0[31:0]
+//	6	pn_63_32[31:0]
+//	7	pn_95_64[31:0]
+//	8	pn_127_96[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9
+
+struct reo_update_rx_reo_queue {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      update_receive_queue_number     :  1, //[8]
+                      update_vld                      :  1, //[9]
+                      update_associated_link_descriptor_counter:  1, //[10]
+                      update_disable_duplicate_detection:  1, //[11]
+                      update_soft_reorder_enable      :  1, //[12]
+                      update_ac                       :  1, //[13]
+                      update_bar                      :  1, //[14]
+                      update_rty                      :  1, //[15]
+                      update_chk_2k_mode              :  1, //[16]
+                      update_oor_mode                 :  1, //[17]
+                      update_ba_window_size           :  1, //[18]
+                      update_pn_check_needed          :  1, //[19]
+                      update_pn_shall_be_even         :  1, //[20]
+                      update_pn_shall_be_uneven       :  1, //[21]
+                      update_pn_handling_enable       :  1, //[22]
+                      update_pn_size                  :  1, //[23]
+                      update_ignore_ampdu_flag        :  1, //[24]
+                      update_svld                     :  1, //[25]
+                      update_ssn                      :  1, //[26]
+                      update_seq_2k_error_detected_flag:  1, //[27]
+                      update_pn_error_detected_flag   :  1, //[28]
+                      update_pn_valid                 :  1, //[29]
+                      update_pn                       :  1, //[30]
+                      reserved_2a                     :  1; //[31]
+             uint32_t receive_queue_number            : 16, //[15:0]
+                      vld                             :  1, //[16]
+                      associated_link_descriptor_counter:  2, //[18:17]
+                      disable_duplicate_detection     :  1, //[19]
+                      soft_reorder_enable             :  1, //[20]
+                      ac                              :  2, //[22:21]
+                      bar                             :  1, //[23]
+                      rty                             :  1, //[24]
+                      chk_2k_mode                     :  1, //[25]
+                      oor_mode                        :  1, //[26]
+                      pn_check_needed                 :  1, //[27]
+                      pn_shall_be_even                :  1, //[28]
+                      pn_shall_be_uneven              :  1, //[29]
+                      pn_handling_enable              :  1, //[30]
+                      ignore_ampdu_flag               :  1; //[31]
+             uint32_t ba_window_size                  :  8, //[7:0]
+                      pn_size                         :  2, //[9:8]
+                      svld                            :  1, //[10]
+                      ssn                             : 12, //[22:11]
+                      seq_2k_error_detected_flag      :  1, //[23]
+                      pn_error_detected_flag          :  1, //[24]
+                      pn_valid                        :  1, //[25]
+                      reserved_4a                     :  6; //[31:26]
+             uint32_t pn_31_0                         : 32; //[31:0]
+             uint32_t pn_63_32                        : 32; //[31:0]
+             uint32_t pn_95_64                        : 32; //[31:0]
+             uint32_t pn_127_96                       : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Details for command execution tracking purposes.
+
+rx_reo_queue_desc_addr_31_0
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (lower 32 bits) of the REO queue descriptor
+
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (upper 8 bits) of the REO queue descriptor
+
+			<legal all>
+
+update_receive_queue_number
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, receive_queue_number from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_vld
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, VLD from this command will be updated in the
+			descriptor.
+
+			<legal all>
+
+update_associated_link_descriptor_counter
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Associated_link_descriptor_counter from this
+			command will be updated in the descriptor.
+
+			<legal all>
+
+update_disable_duplicate_detection
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Disable_duplicate_detection from this command
+			will be updated in the descriptor.
+
+			<legal all>
+
+update_soft_reorder_enable
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Soft_reorder_enable from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_ac
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, AC from this command will be updated in the
+			descriptor.
+
+			<legal all>
+
+update_bar
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, BAR from this command will be updated in the
+			descriptor.
+
+			<legal all>
+
+update_rty
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, RTY from this command will be updated in the
+			descriptor.
+
+			<legal all>
+
+update_chk_2k_mode
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Chk_2k_mode from this command will be updated
+			in the descriptor.
+
+			<legal all>
+
+update_oor_mode
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, OOR_Mode from this command will be updated in
+			the descriptor.
+
+			<legal all>
+
+update_ba_window_size
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, BA_window_size from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_pn_check_needed
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_check_needed from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_pn_shall_be_even
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_shall_be_even from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_pn_shall_be_uneven
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_shall_be_uneven from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_pn_handling_enable
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_handling_enable from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_pn_size
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_size from this command will be updated in
+			the descriptor.
+
+			<legal all>
+
+update_ignore_ampdu_flag
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Ignore_ampdu_flag from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+update_svld
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Svld from this command will be updated in the
+			descriptor.
+
+			<legal all>
+
+update_ssn
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, SSN from this command will be updated in the
+			descriptor.
+
+			<legal all>
+
+update_seq_2k_error_detected_flag
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Seq_2k_error_detected_flag from this command
+			will be updated in the descriptor.
+
+			<legal all>
+
+update_pn_error_detected_flag
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, pn_error_detected_flag from this command will
+			be updated in the descriptor.
+
+			<legal all>
+
+update_pn_valid
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, pn_valid from this command will be updated in
+			the descriptor.
+
+			<legal all>
+
+update_pn
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, all pn_... fields from this command will be
+			updated in the descriptor.
+
+			<legal all>
+
+reserved_2a
+
+			<legal 0>
+
+receive_queue_number
+
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+vld
+
+			Field only valid when Update_VLD is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+associated_link_descriptor_counter
+
+			Field only valid when
+			Update_Associated_link_descriptor_counter is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+disable_duplicate_detection
+
+			Field only valid when Update_Disable_duplicate_detection
+			is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+soft_reorder_enable
+
+			Field only valid when Update_Soft_reorder_enable is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+ac
+
+			Field only valid when Update_AC is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+bar
+
+			Field only valid when Update_BAR is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+rty
+
+			Field only valid when Update_RTY is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+chk_2k_mode
+
+			Field only valid when Update_Chk_2k_Mode is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+oor_mode
+
+			Field only valid when Update_OOR_Mode is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_check_needed
+
+			Field only valid when Update_Pn_check_needed is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_shall_be_even
+
+			Field only valid when Update_Pn_shall_be_even is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_shall_be_uneven
+
+			Field only valid when Update_Pn_shall_be_uneven is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_handling_enable
+
+			Field only valid when Update_Pn_handling_enable is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+ignore_ampdu_flag
+
+			Field only valid when Update_Ignore_ampdu_flag is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+ba_window_size
+
+			Field only valid when Update_BA_window_size is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_size
+
+			Field only valid when Update_Pn_size is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+
+
+			<enum 0     pn_size_24>
+
+			<enum 1     pn_size_48>
+
+			<enum 2     pn_size_128>
+
+
+
+			<legal 0-2>
+
+svld
+
+			Field only valid when Update_Svld is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+ssn
+
+			Field only valid when Update_SSN is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+seq_2k_error_detected_flag
+
+			Field only valid when Update_Seq_2k_error_detected_flag
+			is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_error_detected_flag
+
+			Field only valid when Update_pn_error_detected_flag is
+			set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_valid
+
+			Field only valid when Update_pn_valid is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+reserved_4a
+
+			<legal 0>
+
+pn_31_0
+
+			Field only valid when Update_Pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_63_32
+
+			Field only valid when Update_pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_95_64
+
+			Field only valid when Update_pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+
+pn_127_96
+
+			Field only valid when Update_pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+
+#define REO_UPDATE_RX_REO_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (lower 32 bits) of the REO queue descriptor
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB    0
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK   0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32
+
+			Consumer: REO
+
+			Producer: SW
+
+
+
+			Address (upper 8 bits) of the REO queue descriptor
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB   0
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK  0x000000ff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, receive_queue_number from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB    8
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK   0x00000100
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, VLD from this command will be updated in the
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB                     9
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK                    0x00000200
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Associated_link_descriptor_counter from this
+			command will be updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Disable_duplicate_detection from this command
+			will be updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Soft_reorder_enable from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB     12
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK    0x00001000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, AC from this command will be updated in the
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB                      13
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK                     0x00002000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, BAR from this command will be updated in the
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB                     14
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK                    0x00004000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, RTY from this command will be updated in the
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB                     15
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK                    0x00008000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Chk_2k_mode from this command will be updated
+			in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET          0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB             16
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK            0x00010000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, OOR_Mode from this command will be updated in
+			the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET             0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB                17
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK               0x00020000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, BA_window_size from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET       0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB          18
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK         0x00040000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_check_needed from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET      0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB         19
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK        0x00080000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_shall_be_even from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET     0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB        20
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK       0x00100000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_shall_be_uneven from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB      21
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK     0x00200000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_handling_enable from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB      22
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK     0x00400000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Pn_size from this command will be updated in
+			the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET              0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB                 23
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK                0x00800000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Ignore_ampdu_flag from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB       24
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK      0x01000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Svld from this command will be updated in the
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET                 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB                    25
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK                   0x02000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, SSN from this command will be updated in the
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB                     26
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK                    0x04000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, Seq_2k_error_detected_flag from this command
+			will be updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, pn_error_detected_flag from this command will
+			be updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB  28
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, pn_valid from this command will be updated in
+			the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET             0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB                29
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK               0x20000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN
+
+			Consumer: REO
+
+			Producer: SW
+
+			When set, all pn_... fields from this command will be
+			updated in the descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB                      30
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK                     0x40000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A_OFFSET                 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A_LSB                    31
+#define REO_UPDATE_RX_REO_QUEUE_2_RESERVED_2A_MASK                   0x80000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER
+
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET        0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK          0x0000ffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_VLD
+
+			Field only valid when Update_VLD is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB                            16
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK                           0x00010000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+
+			Field only valid when
+			Update_Associated_link_descriptor_counter is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION
+
+			Field only valid when Update_Disable_duplicate_detection
+			is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB    19
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK   0x00080000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE
+
+			Field only valid when Update_Soft_reorder_enable is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB            20
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK           0x00100000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_AC
+
+			Field only valid when Update_AC is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET                          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB                             21
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK                            0x00600000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_BAR
+
+			Field only valid when Update_BAR is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB                            23
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK                           0x00800000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_RTY
+
+			Field only valid when Update_RTY is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB                            24
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK                           0x01000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE
+
+			Field only valid when Update_Chk_2k_Mode is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET                 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB                    25
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK                   0x02000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE
+
+			Field only valid when Update_OOR_Mode is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET                    0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB                       26
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK                      0x04000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED
+
+			Field only valid when Update_Pn_check_needed is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET             0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB                27
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK               0x08000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN
+
+			Field only valid when Update_Pn_shall_be_even is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET            0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB               28
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK              0x10000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN
+
+			Field only valid when Update_Pn_shall_be_uneven is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB             29
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK            0x20000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE
+
+			Field only valid when Update_Pn_handling_enable is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB             30
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK            0x40000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG
+
+			Field only valid when Update_Ignore_ampdu_flag is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB              31
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK             0x80000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE
+
+			Field only valid when Update_BA_window_size is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET              0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB                 0
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK                0x000000ff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE
+
+			Field only valid when Update_Pn_size is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+
+
+			<enum 0     pn_size_24>
+
+			<enum 1     pn_size_48>
+
+			<enum 2     pn_size_128>
+
+
+
+			<legal 0-2>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET                     0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB                        8
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK                       0x00000300
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_SVLD
+
+			Field only valid when Update_Svld is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET                        0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB                           10
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK                          0x00000400
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_SSN
+
+			Field only valid when Update_SSN is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET                         0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB                            11
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK                           0x007ff800
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG
+
+			Field only valid when Update_Seq_2k_error_detected_flag
+			is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET  0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB     23
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK    0x00800000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG
+
+			Field only valid when Update_pn_error_detected_flag is
+			set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET      0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB         24
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK        0x01000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_PN_VALID
+
+			Field only valid when Update_pn_valid is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET                    0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB                       25
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK                      0x02000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET                 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB                    26
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK                   0xfc000000
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_5_PN_31_0
+
+			Field only valid when Update_Pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET                     0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB                        0
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK                       0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_6_PN_63_32
+
+			Field only valid when Update_pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET                    0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK                      0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_7_PN_95_64
+
+			Field only valid when Update_pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET                    0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK                      0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_8_PN_127_96
+
+			Field only valid when Update_pn is set
+
+
+
+			Field value to be copied over into the RX_REO_QUEUE
+			descriptor.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET                   0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB                      0
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK                     0xffffffff
+
+
+#endif // _REO_UPDATE_RX_REO_QUEUE_H_

hw/qca8074/v1/reo_update_rx_reo_queue_status.h

@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	reserved_2a[31:0]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15a[31:0]
+//	16	reserved_16a[31:0]
+//	17	reserved_17a[31:0]
+//	18	reserved_18a[31:0]
+//	19	reserved_19a[31:0]
+//	20	reserved_20a[31:0]
+//	21	reserved_21a[31:0]
+//	22	reserved_22a[31:0]
+//	23	reserved_23a[31:0]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
+
+struct reo_update_rx_reo_queue_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t reserved_2a                     : 32; //[31:0]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15a                    : 32; //[31:0]
+             uint32_t reserved_16a                    : 32; //[31:0]
+             uint32_t reserved_17a                    : 32; //[31:0]
+             uint32_t reserved_18a                    : 32; //[31:0]
+             uint32_t reserved_19a                    : 32; //[31:0]
+             uint32_t reserved_20a                    : 32; //[31:0]
+             uint32_t reserved_21a                    : 32; //[31:0]
+             uint32_t reserved_22a                    : 32; //[31:0]
+             uint32_t reserved_23a                    : 32; //[31:0]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+			Consumer: SW
+
+			Producer: REO
+
+
+
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+reserved_2a
+
+			<legal 0>
+
+reserved_3a
+
+			<legal 0>
+
+reserved_4a
+
+			<legal 0>
+
+reserved_5a
+
+			<legal 0>
+
+reserved_6a
+
+			<legal 0>
+
+reserved_7a
+
+			<legal 0>
+
+reserved_8a
+
+			<legal 0>
+
+reserved_9a
+
+			<legal 0>
+
+reserved_10a
+
+			<legal 0>
+
+reserved_11a
+
+			<legal 0>
+
+reserved_12a
+
+			<legal 0>
+
+reserved_13a
+
+			<legal 0>
+
+reserved_14a
+
+			<legal 0>
+
+reserved_15a
+
+			<legal 0>
+
+reserved_16a
+
+			<legal 0>
+
+reserved_17a
+
+			<legal 0>
+
+reserved_18a
+
+			<legal 0>
+
+reserved_19a
+
+			<legal 0>
+
+reserved_20a
+
+			<legal 0>
+
+reserved_21a
+
+			<legal 0>
+
+reserved_22a
+
+			<legal 0>
+
+reserved_23a
+
+			<legal 0>
+
+reserved_24a
+
+			<legal 0>
+
+looping_count
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET          0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET          0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET          0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET          0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET          0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET          0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET          0x00000024
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK            0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET        0x00000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET        0x0000002c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET        0x00000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET        0x00000034
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET        0x00000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET        0x0000003c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET        0x00000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET        0x00000044
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET        0x00000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET        0x0000004c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET        0x00000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET        0x00000054
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET        0x00000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET        0x0000005c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK          0xffffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
+
+			<legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET        0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK          0x0fffffff
+
+/* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
+
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+
+
+
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+
+
+
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+
+			<legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET       0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB          28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK         0xf0000000
+
+
+#endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_

hw/qca8074/v1/rx_ppdu_end_user_stats.h

@@ -0,0 +1,1578 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct rx_rxpcu_classification_overview rxpcu_classification_details;
+//	1	sta_full_aid[12:0], mcs[16:13], nss[19:17], odma_info_valid[20], ofdma_low_ru_index[27:21], reserved_1a[31:28]
+//	2	ofdma_high_ru_index[6:0], reserved_2a[7], user_receive_quality[15:8], mpdu_cnt_fcs_err[25:16], wbm2rxdma_buf_source_used[26], fw2rxdma_buf_source_used[27], sw2rxdma_buf_source_used[28], reserved_2b[31:29]
+//	3	mpdu_cnt_fcs_ok[8:0], frame_control_info_valid[9], qos_control_info_valid[10], ht_control_info_valid[11], data_sequence_control_info_valid[12], reserved_3a[15:13], rxdma2reo_ring_used[16], rxdma2fw_ring_used[17], rxdma2sw_ring_used[18], rxdma_release_ring_used[19], ht_control_field_pkt_type[23:20], reserved_3b[31:24]
+//	4	ast_index[15:0], frame_control_field[31:16]
+//	5	first_data_seq_ctrl[15:0], qos_control_field[31:16]
+//	6	ht_control_field[31:0]
+//	7	fcs_ok_bitmap_31_0[31:0]
+//	8	fcs_ok_bitmap_63_32[31:0]
+//	9	udp_msdu_count[15:0], tcp_msdu_count[31:16]
+//	10	other_msdu_count[15:0], tcp_ack_msdu_count[31:16]
+//	11	sw_response_reference_ptr[31:0]
+//	12	received_qos_data_tid_bitmap[15:0], received_qos_data_tid_eosp_bitmap[31:16]
+//	13	qosctrl_15_8_tid0[7:0], qosctrl_15_8_tid1[15:8], qosctrl_15_8_tid2[23:16], qosctrl_15_8_tid3[31:24]
+//	14	qosctrl_15_8_tid4[7:0], qosctrl_15_8_tid5[15:8], qosctrl_15_8_tid6[23:16], qosctrl_15_8_tid7[31:24]
+//	15	qosctrl_15_8_tid8[7:0], qosctrl_15_8_tid9[15:8], qosctrl_15_8_tid10[23:16], qosctrl_15_8_tid11[31:24]
+//	16	qosctrl_15_8_tid12[7:0], qosctrl_15_8_tid13[15:8], qosctrl_15_8_tid14[23:16], qosctrl_15_8_tid15[31:24]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 17
+
+struct rx_ppdu_end_user_stats {
+    struct            rx_rxpcu_classification_overview                       rxpcu_classification_details;
+             uint32_t sta_full_aid                    : 13, //[12:0]
+                      mcs                             :  4, //[16:13]
+                      nss                             :  3, //[19:17]
+                      odma_info_valid                 :  1, //[20]
+                      ofdma_low_ru_index              :  7, //[27:21]
+                      reserved_1a                     :  4; //[31:28]
+             uint32_t ofdma_high_ru_index             :  7, //[6:0]
+                      reserved_2a                     :  1, //[7]
+                      user_receive_quality            :  8, //[15:8]
+                      mpdu_cnt_fcs_err                : 10, //[25:16]
+                      wbm2rxdma_buf_source_used       :  1, //[26]
+                      fw2rxdma_buf_source_used        :  1, //[27]
+                      sw2rxdma_buf_source_used        :  1, //[28]
+                      reserved_2b                     :  3; //[31:29]
+             uint32_t mpdu_cnt_fcs_ok                 :  9, //[8:0]
+                      frame_control_info_valid        :  1, //[9]
+                      qos_control_info_valid          :  1, //[10]
+                      ht_control_info_valid           :  1, //[11]
+                      data_sequence_control_info_valid:  1, //[12]
+                      reserved_3a                     :  3, //[15:13]
+                      rxdma2reo_ring_used             :  1, //[16]
+                      rxdma2fw_ring_used              :  1, //[17]
+                      rxdma2sw_ring_used              :  1, //[18]
+                      rxdma_release_ring_used         :  1, //[19]
+                      ht_control_field_pkt_type       :  4, //[23:20]
+                      reserved_3b                     :  8; //[31:24]
+             uint32_t ast_index                       : 16, //[15:0]
+                      frame_control_field             : 16; //[31:16]
+             uint32_t first_data_seq_ctrl             : 16, //[15:0]
+                      qos_control_field               : 16; //[31:16]
+             uint32_t ht_control_field                : 32; //[31:0]
+             uint32_t fcs_ok_bitmap_31_0              : 32; //[31:0]
+             uint32_t fcs_ok_bitmap_63_32             : 32; //[31:0]
+             uint32_t udp_msdu_count                  : 16, //[15:0]
+                      tcp_msdu_count                  : 16; //[31:16]
+             uint32_t other_msdu_count                : 16, //[15:0]
+                      tcp_ack_msdu_count              : 16; //[31:16]
+             uint32_t sw_response_reference_ptr       : 32; //[31:0]
+             uint32_t received_qos_data_tid_bitmap    : 16, //[15:0]
+                      received_qos_data_tid_eosp_bitmap: 16; //[31:16]
+             uint32_t qosctrl_15_8_tid0               :  8, //[7:0]
+                      qosctrl_15_8_tid1               :  8, //[15:8]
+                      qosctrl_15_8_tid2               :  8, //[23:16]
+                      qosctrl_15_8_tid3               :  8; //[31:24]
+             uint32_t qosctrl_15_8_tid4               :  8, //[7:0]
+                      qosctrl_15_8_tid5               :  8, //[15:8]
+                      qosctrl_15_8_tid6               :  8, //[23:16]
+                      qosctrl_15_8_tid7               :  8; //[31:24]
+             uint32_t qosctrl_15_8_tid8               :  8, //[7:0]
+                      qosctrl_15_8_tid9               :  8, //[15:8]
+                      qosctrl_15_8_tid10              :  8, //[23:16]
+                      qosctrl_15_8_tid11              :  8; //[31:24]
+             uint32_t qosctrl_15_8_tid12              :  8, //[7:0]
+                      qosctrl_15_8_tid13              :  8, //[15:8]
+                      qosctrl_15_8_tid14              :  8, //[23:16]
+                      qosctrl_15_8_tid15              :  8; //[31:24]
+};
+
+/*
+
+struct rx_rxpcu_classification_overview rxpcu_classification_details
+
+			Details related to what RXPCU classification types of
+			MPDUs have been received
+
+sta_full_aid
+
+			Consumer: FW
+
+			Producer: RXPCU
+
+
+
+			The full AID of this station.
+
+
+
+			<legal all>
+
+mcs
+
+			MCS of the received frame
+
+
+
+			For details, refer to  MCS_TYPE description
+
+			<legal all>
+
+nss
+
+			Number of spatial streams.
+
+
+
+			<enum 0 1_spatial_stream>Single spatial stream
+
+			<enum 1 2_spatial_streams>2 spatial streams
+
+			<enum 2 3_spatial_streams>3 spatial streams
+
+			<enum 3 4_spatial_streams>4 spatial streams
+
+			<enum 4 5_spatial_streams>5 spatial streams
+
+			<enum 5 6_spatial_streams>6 spatial streams
+
+			<enum 6 7_spatial_streams>7 spatial streams
+
+			<enum 7 8_spatial_streams>8 spatial streams
+
+odma_info_valid
+
+			When set, ofdma RU related info in the following fields
+			is valid
+
+			<legal all>
+
+ofdma_low_ru_index
+
+			The index of the lowerest RU used by this STA.
+
+			<legal all>
+
+reserved_1a
+
+			<legal 0>
+
+ofdma_high_ru_index
+
+			The index of the highest RU used by this STA.
+
+			<legal all>
+
+reserved_2a
+
+			<legal 0>
+
+user_receive_quality
+
+			RSSI / EVM for this user ???
+
+
+
+			Details TBD
+
+			<legal all>
+
+mpdu_cnt_fcs_err
+
+			The number of MPDUs received from this STA in this PPDU
+			with FCS errors
+
+			<legal all>
+
+wbm2rxdma_buf_source_used
+
+			Field filled in by RXDMA
+
+
+
+			When set, RXDMA has used the wbm2rxdma_buf ring as
+			source for at least one of the frames in this PPDU.
+
+fw2rxdma_buf_source_used
+
+			Field filled in by RXDMA
+
+
+
+			When set, RXDMA has used the fw2rxdma_buf ring as source
+			for at least one of the frames in this PPDU.
+
+sw2rxdma_buf_source_used
+
+			Field filled in by RXDMA
+
+
+
+			When set, RXDMA has used the sw2rxdma_buf ring as source
+			for at least one of the frames in this PPDU.
+
+reserved_2b
+
+			<legal 0>
+
+mpdu_cnt_fcs_ok
+
+			The number of MPDUs received from this STA in this PPDU
+			with correct FCS
+
+			<legal all>
+
+frame_control_info_valid
+
+			When set, the frame_control_info field contains valid
+			information
+
+			<legal all>
+
+qos_control_info_valid
+
+			When set, the QoS_control_info field contains valid
+			information
+
+			<legal all>
+
+ht_control_info_valid
+
+			When set, the HT_control_info field contains valid
+			information
+
+			<legal all>
+
+data_sequence_control_info_valid
+
+			When set, the First_data_seq_ctrl field contains valid
+			information
+
+			<legal all>
+
+reserved_3a
+
+			<legal 0>
+
+rxdma2reo_ring_used
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+
+rxdma2fw_ring_used
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+
+rxdma2sw_ring_used
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+
+rxdma_release_ring_used
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+
+ht_control_field_pkt_type
+
+			Field only valid when HT_control_info_valid  is set.
+
+
+
+			Indicates what the PHY receive type was for receiving
+			this frame. Can help determine if the HT_CONTROL field shall
+			be interpreted as HT/VHT or HE.
+
+
+
+			<enum 0 dot11a>802.11a PPDU type
+
+			<enum 1 dot11b>802.11b PPDU type
+
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+			<enum 3 dot11ac>802.11ac PPDU type
+
+			<enum 4 dot11ax>802.11ax PPDU type
+
+reserved_3b
+
+			<legal 0>
+
+ast_index
+
+			This field indicates the index of the AST entry
+			corresponding to this MPDU. It is provided by the GSE module
+			instantiated in RXPCU.
+
+			A value of 0xFFFF indicates an invalid AST index,
+			meaning that No AST entry was found or NO AST search was
+			performed
+
+			<legal all>
+
+frame_control_field
+
+			Field only valid when Frame_control_info_valid is set.
+
+
+
+			Last successfully received Frame_control field of data
+			frame (excluding Data NULL/ QoS Null) for this user
+
+			Mainly used to track the PM state of the transmitted
+			device
+
+
+
+			NOTE: only data frame info is needed, as control and
+			management frames are already routed to the FW.
+
+			<legal all>
+
+first_data_seq_ctrl
+
+			Field only valid when Data_sequence_control_info_valid
+			is set.
+
+
+
+			Sequence control field of the first data frame
+			(excluding Data NULL or QoS Data null) received for this
+			user with correct FCS
+
+
+
+			NOTE: only data frame info is needed, as control and
+			management frames are already routed to the FW.
+
+			<legal all>
+
+qos_control_field
+
+			Field only valid when QoS_control_info_valid is set.
+
+
+
+			Last successfully received QoS_control field of data
+			frame (excluding Data NULL/ QoS Null) for this user
+
+
+
+			Note that in case of multi TID, this field can only
+			reflect the last properly received MPDU, and thus can not
+			indicate all potentially different TIDs that had been
+			received earlier.
+
+
+
+			There are however per TID fields, that will contain
+			among other things all buffer status info: See
+
+			QoSCtrl_15_8_tid???
+
+			<legal all>
+
+ht_control_field
+
+			Field only valid when HT_control_info_valid is set.
+
+
+
+			Last successfully received
+			HT_CONTROL/VHT_CONTROL/HE_CONTROL  field of data frames,
+			excluding Data NULL/ QoS Null, for this user. Data NULL/ QoS
+			Null are excluded here because these frames are always
+			already routed to the FW by RXDMA.
+
+
+
+			See field HT_control_field_pkt_type in case pkt_type
+			influences if this fields interpretation as HT/VHT/HE
+			CONTROL
+
+			<legal all>
+
+fcs_ok_bitmap_31_0
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+
+fcs_ok_bitmap_63_32
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+
+
+			NOTE: for users 0, 1, 2 and 3, additional bitmap info
+			(up to 256 bitmap window) is provided in
+			RX_PPDU_END_USER_STATS_EXT TLV
+
+			<legal all>
+
+udp_msdu_count
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain UDP frames.
+
+			<legal all>
+
+tcp_msdu_count
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain TCP frames.
+
+
+
+			(Note: This does NOT include TCP-ACK)
+
+			<legal all>
+
+other_msdu_count
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain neither UDP or TCP frames.
+
+
+
+			Includes Management and control frames.
+
+
+
+			<legal all>
+
+tcp_ack_msdu_count
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain TCP ack frames.
+
+			<legal all>
+
+sw_response_reference_ptr
+
+			Pointer that SW uses to refer back to an expected
+			response reception. Used for Rate adaptation purposes.
+
+			When a reception occurrs that is not tied to an expected
+			response, this field is set to 0x0
+
+			<legal all>
+
+received_qos_data_tid_bitmap
+
+			Whenever a QoS Data frame is received, the bit in this
+			field that corresponds to the received TID shall be set.
+
+			...Bitmap[0] = TID0
+
+			...Bitmap[1] = TID1
+
+			Etc.
+
+			<legal all>
+
+received_qos_data_tid_eosp_bitmap
+
+			Field initialized to 0
+
+			For every QoS Data frame that is correctly received, the
+			EOSP bit of that frame is copied over into the corresponding
+			TID related field.
+
+			Note that this implies that the bits here represent the
+			EOSP bit status for each TID of the last MPDU received for
+			that TID.
+
+
+
+			received TID shall be set.
+
+			...eosp_bitmap[0] = eosp of TID0
+
+			...eosp_bitmap[1] = eosp of TID1
+
+			Etc.
+
+			<legal all>
+
+qosctrl_15_8_tid0
+
+			Field only valid when Received_qos_data_tid_bitmap[0] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID0
+
+qosctrl_15_8_tid1
+
+			Field only valid when Received_qos_data_tid_bitmap[1] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID1
+
+qosctrl_15_8_tid2
+
+			Field only valid when Received_qos_data_tid_bitmap[2] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID2
+
+qosctrl_15_8_tid3
+
+			Field only valid when Received_qos_data_tid_bitmap[3] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID3
+
+qosctrl_15_8_tid4
+
+			Field only valid when Received_qos_data_tid_bitmap[4] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID4
+
+qosctrl_15_8_tid5
+
+			Field only valid when Received_qos_data_tid_bitmap[5] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID5
+
+qosctrl_15_8_tid6
+
+			Field only valid when Received_qos_data_tid_bitmap[6] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID6
+
+qosctrl_15_8_tid7
+
+			Field only valid when Received_qos_data_tid_bitmap[7] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID7
+
+qosctrl_15_8_tid8
+
+			Field only valid when Received_qos_data_tid_bitmap[8] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID8
+
+qosctrl_15_8_tid9
+
+			Field only valid when Received_qos_data_tid_bitmap[9] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID9
+
+qosctrl_15_8_tid10
+
+			Field only valid when Received_qos_data_tid_bitmap[10]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID10
+
+qosctrl_15_8_tid11
+
+			Field only valid when Received_qos_data_tid_bitmap[11]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID11
+
+qosctrl_15_8_tid12
+
+			Field only valid when Received_qos_data_tid_bitmap[12]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID12
+
+qosctrl_15_8_tid13
+
+			Field only valid when Received_qos_data_tid_bitmap[13]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID13
+
+qosctrl_15_8_tid14
+
+			Field only valid when Received_qos_data_tid_bitmap[14]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID14
+
+qosctrl_15_8_tid15
+
+			Field only valid when Received_qos_data_tid_bitmap[15]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID15
+*/
+
+#define RX_PPDU_END_USER_STATS_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_LSB 24
+#define RX_PPDU_END_USER_STATS_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_MASK 0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_1_STA_FULL_AID
+
+			Consumer: FW
+
+			Producer: RXPCU
+
+
+
+			The full AID of this station.
+
+
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET                 0x00000004
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB                    0
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK                   0x00001fff
+
+/* Description		RX_PPDU_END_USER_STATS_1_MCS
+
+			MCS of the received frame
+
+
+
+			For details, refer to  MCS_TYPE description
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET                          0x00000004
+#define RX_PPDU_END_USER_STATS_1_MCS_LSB                             13
+#define RX_PPDU_END_USER_STATS_1_MCS_MASK                            0x0001e000
+
+/* Description		RX_PPDU_END_USER_STATS_1_NSS
+
+			Number of spatial streams.
+
+
+
+			<enum 0 1_spatial_stream>Single spatial stream
+
+			<enum 1 2_spatial_streams>2 spatial streams
+
+			<enum 2 3_spatial_streams>3 spatial streams
+
+			<enum 3 4_spatial_streams>4 spatial streams
+
+			<enum 4 5_spatial_streams>5 spatial streams
+
+			<enum 5 6_spatial_streams>6 spatial streams
+
+			<enum 6 7_spatial_streams>7 spatial streams
+
+			<enum 7 8_spatial_streams>8 spatial streams
+*/
+#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET                          0x00000004
+#define RX_PPDU_END_USER_STATS_1_NSS_LSB                             17
+#define RX_PPDU_END_USER_STATS_1_NSS_MASK                            0x000e0000
+
+/* Description		RX_PPDU_END_USER_STATS_1_ODMA_INFO_VALID
+
+			When set, ofdma RU related info in the following fields
+			is valid
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_1_ODMA_INFO_VALID_OFFSET              0x00000004
+#define RX_PPDU_END_USER_STATS_1_ODMA_INFO_VALID_LSB                 20
+#define RX_PPDU_END_USER_STATS_1_ODMA_INFO_VALID_MASK                0x00100000
+
+/* Description		RX_PPDU_END_USER_STATS_1_OFDMA_LOW_RU_INDEX
+
+			The index of the lowerest RU used by this STA.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_1_OFDMA_LOW_RU_INDEX_OFFSET           0x00000004
+#define RX_PPDU_END_USER_STATS_1_OFDMA_LOW_RU_INDEX_LSB              21
+#define RX_PPDU_END_USER_STATS_1_OFDMA_LOW_RU_INDEX_MASK             0x0fe00000
+
+/* Description		RX_PPDU_END_USER_STATS_1_RESERVED_1A
+
+			<legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET                  0x00000004
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB                     28
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK                    0xf0000000
+
+/* Description		RX_PPDU_END_USER_STATS_2_OFDMA_HIGH_RU_INDEX
+
+			The index of the highest RU used by this STA.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_2_OFDMA_HIGH_RU_INDEX_OFFSET          0x00000008
+#define RX_PPDU_END_USER_STATS_2_OFDMA_HIGH_RU_INDEX_LSB             0
+#define RX_PPDU_END_USER_STATS_2_OFDMA_HIGH_RU_INDEX_MASK            0x0000007f
+
+/* Description		RX_PPDU_END_USER_STATS_2_RESERVED_2A
+
+			<legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET                  0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB                     7
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK                    0x00000080
+
+/* Description		RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY
+
+			RSSI / EVM for this user ???
+
+
+
+			Details TBD
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET         0x00000008
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB            8
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK           0x0000ff00
+
+/* Description		RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR
+
+			The number of MPDUs received from this STA in this PPDU
+			with FCS errors
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET             0x00000008
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB                16
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK               0x03ff0000
+
+/* Description		RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED
+
+			Field filled in by RXDMA
+
+
+
+			When set, RXDMA has used the wbm2rxdma_buf ring as
+			source for at least one of the frames in this PPDU.
+*/
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET    0x00000008
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB       26
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK      0x04000000
+
+/* Description		RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED
+
+			Field filled in by RXDMA
+
+
+
+			When set, RXDMA has used the fw2rxdma_buf ring as source
+			for at least one of the frames in this PPDU.
+*/
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET     0x00000008
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB        27
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK       0x08000000
+
+/* Description		RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED
+
+			Field filled in by RXDMA
+
+
+
+			When set, RXDMA has used the sw2rxdma_buf ring as source
+			for at least one of the frames in this PPDU.
+*/
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET     0x00000008
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB        28
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK       0x10000000
+
+/* Description		RX_PPDU_END_USER_STATS_2_RESERVED_2B
+
+			<legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET                  0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB                     29
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK                    0xe0000000
+
+/* Description		RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK
+
+			The number of MPDUs received from this STA in this PPDU
+			with correct FCS
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET              0x0000000c
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB                 0
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK                0x000001ff
+
+/* Description		RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID
+
+			When set, the frame_control_info field contains valid
+			information
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET     0x0000000c
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB        9
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK       0x00000200
+
+/* Description		RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID
+
+			When set, the QoS_control_info field contains valid
+			information
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET       0x0000000c
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB          10
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK         0x00000400
+
+/* Description		RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID
+
+			When set, the HT_control_info field contains valid
+			information
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET        0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB           11
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK          0x00000800
+
+/* Description		RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID
+
+			When set, the First_data_seq_ctrl field contains valid
+			information
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000
+
+/* Description		RX_PPDU_END_USER_STATS_3_RESERVED_3A
+
+			<legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB                     13
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK                    0x0000e000
+
+/* Description		RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET          0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB             16
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK            0x00010000
+
+/* Description		RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET           0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB              17
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK             0x00020000
+
+/* Description		RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET           0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB              18
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK             0x00040000
+
+/* Description		RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED
+
+			Field filled in by RXDMA
+
+
+
+			Set when at least one frame during this PPDU got pushed
+			to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET      0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB         19
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK        0x00080000
+
+/* Description		RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE
+
+			Field only valid when HT_control_info_valid  is set.
+
+
+
+			Indicates what the PHY receive type was for receiving
+			this frame. Can help determine if the HT_CONTROL field shall
+			be interpreted as HT/VHT or HE.
+
+
+
+			<enum 0 dot11a>802.11a PPDU type
+
+			<enum 1 dot11b>802.11b PPDU type
+
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+			<enum 3 dot11ac>802.11ac PPDU type
+
+			<enum 4 dot11ax>802.11ax PPDU type
+*/
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET    0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB       20
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK      0x00f00000
+
+/* Description		RX_PPDU_END_USER_STATS_3_RESERVED_3B
+
+			<legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET                  0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB                     24
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK                    0xff000000
+
+/* Description		RX_PPDU_END_USER_STATS_4_AST_INDEX
+
+			This field indicates the index of the AST entry
+			corresponding to this MPDU. It is provided by the GSE module
+			instantiated in RXPCU.
+
+			A value of 0xFFFF indicates an invalid AST index,
+			meaning that No AST entry was found or NO AST search was
+			performed
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET                    0x00000010
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB                       0
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK                      0x0000ffff
+
+/* Description		RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD
+
+			Field only valid when Frame_control_info_valid is set.
+
+
+
+			Last successfully received Frame_control field of data
+			frame (excluding Data NULL/ QoS Null) for this user
+
+			Mainly used to track the PM state of the transmitted
+			device
+
+
+
+			NOTE: only data frame info is needed, as control and
+			management frames are already routed to the FW.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET          0x00000010
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB             16
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK            0xffff0000
+
+/* Description		RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL
+
+			Field only valid when Data_sequence_control_info_valid
+			is set.
+
+
+
+			Sequence control field of the first data frame
+			(excluding Data NULL or QoS Data null) received for this
+			user with correct FCS
+
+
+
+			NOTE: only data frame info is needed, as control and
+			management frames are already routed to the FW.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET          0x00000014
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB             0
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK            0x0000ffff
+
+/* Description		RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD
+
+			Field only valid when QoS_control_info_valid is set.
+
+
+
+			Last successfully received QoS_control field of data
+			frame (excluding Data NULL/ QoS Null) for this user
+
+
+
+			Note that in case of multi TID, this field can only
+			reflect the last properly received MPDU, and thus can not
+			indicate all potentially different TIDs that had been
+			received earlier.
+
+
+
+			There are however per TID fields, that will contain
+			among other things all buffer status info: See
+
+			QoSCtrl_15_8_tid???
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET            0x00000014
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB               16
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK              0xffff0000
+
+/* Description		RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD
+
+			Field only valid when HT_control_info_valid is set.
+
+
+
+			Last successfully received
+			HT_CONTROL/VHT_CONTROL/HE_CONTROL  field of data frames,
+			excluding Data NULL/ QoS Null, for this user. Data NULL/ QoS
+			Null are excluded here because these frames are always
+			already routed to the FW by RXDMA.
+
+
+
+			See field HT_control_field_pkt_type in case pkt_type
+			influences if this fields interpretation as HT/VHT/HE
+			CONTROL
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET             0x00000018
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB                0
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK               0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET           0x0000001c
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB              0
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK             0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+
+
+			NOTE: for users 0, 1, 2 and 3, additional bitmap info
+			(up to 256 bitmap window) is provided in
+			RX_PPDU_END_USER_STATS_EXT TLV
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET          0x00000020
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB             0
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK            0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain UDP frames.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET               0x00000024
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB                  0
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK                 0x0000ffff
+
+/* Description		RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain TCP frames.
+
+
+
+			(Note: This does NOT include TCP-ACK)
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET               0x00000024
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB                  16
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK                 0xffff0000
+
+/* Description		RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain neither UDP or TCP frames.
+
+
+
+			Includes Management and control frames.
+
+
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET            0x00000028
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB               0
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK              0x0000ffff
+
+/* Description		RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT
+
+			Field filled in by RX OLE
+
+			Set to 0 by RXPCU
+
+
+
+			The number of MSDUs that are part of MPDUs without FCS
+			error, that contain TCP ack frames.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET          0x00000028
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB             16
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK            0xffff0000
+
+/* Description		RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR
+
+			Pointer that SW uses to refer back to an expected
+			response reception. Used for Rate adaptation purposes.
+
+			When a reception occurrs that is not tied to an expected
+			response, this field is set to 0x0
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET   0x0000002c
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB      0
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK     0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP
+
+			Whenever a QoS Data frame is received, the bit in this
+			field that corresponds to the received TID shall be set.
+
+			...Bitmap[0] = TID0
+
+			...Bitmap[1] = TID1
+
+			Etc.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB   0
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK  0x0000ffff
+
+/* Description		RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP
+
+			Field initialized to 0
+
+			For every QoS Data frame that is correctly received, the
+			EOSP bit of that frame is copied over into the corresponding
+			TID related field.
+
+			Note that this implies that the bits here represent the
+			EOSP bit status for each TID of the last MPDU received for
+			that TID.
+
+
+
+			received TID shall be set.
+
+			...eosp_bitmap[0] = eosp of TID0
+
+			...eosp_bitmap[1] = eosp of TID1
+
+			Etc.
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000
+
+/* Description		RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0
+
+			Field only valid when Received_qos_data_tid_bitmap[0] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID0
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB              0
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK             0x000000ff
+
+/* Description		RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1
+
+			Field only valid when Received_qos_data_tid_bitmap[1] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID1
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB              8
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK             0x0000ff00
+
+/* Description		RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2
+
+			Field only valid when Received_qos_data_tid_bitmap[2] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID2
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB              16
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK             0x00ff0000
+
+/* Description		RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3
+
+			Field only valid when Received_qos_data_tid_bitmap[3] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID3
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB              24
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK             0xff000000
+
+/* Description		RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4
+
+			Field only valid when Received_qos_data_tid_bitmap[4] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID4
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB              0
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK             0x000000ff
+
+/* Description		RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5
+
+			Field only valid when Received_qos_data_tid_bitmap[5] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID5
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB              8
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK             0x0000ff00
+
+/* Description		RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6
+
+			Field only valid when Received_qos_data_tid_bitmap[6] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID6
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB              16
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK             0x00ff0000
+
+/* Description		RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7
+
+			Field only valid when Received_qos_data_tid_bitmap[7] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID7
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB              24
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK             0xff000000
+
+/* Description		RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8
+
+			Field only valid when Received_qos_data_tid_bitmap[8] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID8
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET           0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB              0
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK             0x000000ff
+
+/* Description		RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9
+
+			Field only valid when Received_qos_data_tid_bitmap[9] is
+			set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID9
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET           0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB              8
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK             0x0000ff00
+
+/* Description		RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10
+
+			Field only valid when Received_qos_data_tid_bitmap[10]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID10
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET          0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB             16
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK            0x00ff0000
+
+/* Description		RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11
+
+			Field only valid when Received_qos_data_tid_bitmap[11]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID11
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET          0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB             24
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK            0xff000000
+
+/* Description		RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12
+
+			Field only valid when Received_qos_data_tid_bitmap[12]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID12
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB             0
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK            0x000000ff
+
+/* Description		RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13
+
+			Field only valid when Received_qos_data_tid_bitmap[13]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID13
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB             8
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK            0x0000ff00
+
+/* Description		RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14
+
+			Field only valid when Received_qos_data_tid_bitmap[14]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID14
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB             16
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK            0x00ff0000
+
+/* Description		RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15
+
+			Field only valid when Received_qos_data_tid_bitmap[15]
+			is set
+
+
+
+			QoS control field bits 15-8 of the last properly
+			received MPDU with TID15
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB             24
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK            0xff000000
+
+
+#endif // _RX_PPDU_END_USER_STATS_H_

hw/qca8074/v1/rx_ppdu_end_user_stats_ext.h

@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct rx_rxpcu_classification_overview rxpcu_classification_details;
+//	1	fcs_ok_bitmap_95_64[31:0]
+//	2	fcs_ok_bitmap_127_96[31:0]
+//	3	fcs_ok_bitmap_159_128[31:0]
+//	4	fcs_ok_bitmap_191_160[31:0]
+//	5	fcs_ok_bitmap_223_192[31:0]
+//	6	fcs_ok_bitmap_255_224[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7
+
+struct rx_ppdu_end_user_stats_ext {
+    struct            rx_rxpcu_classification_overview                       rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64             : 32; //[31:0]
+             uint32_t fcs_ok_bitmap_127_96            : 32; //[31:0]
+             uint32_t fcs_ok_bitmap_159_128           : 32; //[31:0]
+             uint32_t fcs_ok_bitmap_191_160           : 32; //[31:0]
+             uint32_t fcs_ok_bitmap_223_192           : 32; //[31:0]
+             uint32_t fcs_ok_bitmap_255_224           : 32; //[31:0]
+};
+
+/*
+
+struct rx_rxpcu_classification_overview rxpcu_classification_details
+
+			Details related to what RXPCU classification types of
+			MPDUs have been received
+
+fcs_ok_bitmap_95_64
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+
+fcs_ok_bitmap_127_96
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+
+fcs_ok_bitmap_159_128
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+
+fcs_ok_bitmap_191_160
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+
+fcs_ok_bitmap_223_192
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+
+fcs_ok_bitmap_255_224
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_0_RX_RXPCU_CLASSIFICATION_OVERVIEW_RXPCU_CLASSIFICATION_DETAILS_MASK 0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET      0x00000004
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB         0
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK        0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET     0x00000008
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB        0
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK       0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET    0x0000000c
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK      0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET    0x00000010
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK      0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET    0x00000014
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK      0xffffffff
+
+/* Description		RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224
+
+			Bitmap indicates in order of received MPDUs, which MPDUs
+			had an passing FCS or had an error.
+
+			1: FCS OK
+
+			0: FCS error
+
+			<legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET    0x00000018
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK      0xffffffff
+
+
+#endif // _RX_PPDU_END_USER_STATS_EXT_H_

hw/qca8074/v1/rx_ppdu_start.h

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	phy_ppdu_id[15:0], reserved_15[31:16]
+//	1	sw_phy_meta_data[31:0]
+//	2	ppdu_start_timestamp[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_START 3
+
+struct rx_ppdu_start {
+             uint32_t phy_ppdu_id                     : 16, //[15:0]
+                      reserved_15                     : 16; //[31:16]
+             uint32_t sw_phy_meta_data                : 32; //[31:0]
+             uint32_t ppdu_start_timestamp            : 32; //[31:0]
+};
+
+/*
+
+phy_ppdu_id
+
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around
+
+			<legal all>
+
+reserved_15
+
+			Reserved
+
+			<legal 0>
+
+sw_phy_meta_data
+
+			SW programmed Meta data provided by the PHY.
+
+
+
+			Can be used for SW to indicate the channel the device is
+			on.
+
+ppdu_start_timestamp
+
+			Timestamp that indicates when the PPDU that contained
+			this MPDU started on the medium.
+
+
+
+			The timestamp is captured by the PHY ????TODO: Is this
+			comment correct ?
+
+			<legal all>
+*/
+
+
+/* Description		RX_PPDU_START_0_PHY_PPDU_ID
+
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around
+
+			<legal all>
+*/
+#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET                           0x00000000
+#define RX_PPDU_START_0_PHY_PPDU_ID_LSB                              0
+#define RX_PPDU_START_0_PHY_PPDU_ID_MASK                             0x0000ffff
+
+/* Description		RX_PPDU_START_0_RESERVED_15
+
+			Reserved
+
+			<legal 0>
+*/
+#define RX_PPDU_START_0_RESERVED_15_OFFSET                           0x00000000
+#define RX_PPDU_START_0_RESERVED_15_LSB                              16
+#define RX_PPDU_START_0_RESERVED_15_MASK                             0xffff0000
+
+/* Description		RX_PPDU_START_1_SW_PHY_META_DATA
+
+			SW programmed Meta data provided by the PHY.
+
+
+
+			Can be used for SW to indicate the channel the device is
+			on.
+*/
+#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET                      0x00000004
+#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB                         0
+#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK                        0xffffffff
+
+/* Description		RX_PPDU_START_2_PPDU_START_TIMESTAMP
+
+			Timestamp that indicates when the PPDU that contained
+			this MPDU started on the medium.
+
+
+
+			The timestamp is captured by the PHY ????TODO: Is this
+			comment correct ?
+
+			<legal all>
+*/
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET                  0x00000008
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB                     0
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK                    0xffffffff
+
+
+#endif // _RX_PPDU_START_H_

hw/qca8074/v1/rx_ppdu_start_user_info.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_user_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct receive_user_info receive_user_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 2
+
+struct rx_ppdu_start_user_info {
+    struct            receive_user_info                       receive_user_info_details;
+};
+
+/*
+
+struct receive_user_info receive_user_info_details
+
+			Overview of receive parameters that the MAC needs to
+			prepend to every received MSDU/MPDU.
+*/
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_LSB 0
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_MASK 0xffffffff
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_LSB 0
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_RECEIVE_USER_INFO_DETAILS_MASK 0xffffffff
+
+
+#endif // _RX_PPDU_START_USER_INFO_H_

hw/qca8074/v1/rx_rxpcu_classification_overview.h

@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	filter_pass_mpdus[0], filter_pass_mpdus_fcs_ok[1], monitor_direct_mpdus[2], monitor_direct_mpdus_fcs_ok[3], monitor_other_mpdus[4], monitor_other_mpdus_fcs_ok[5], reserved_0[15:6], phy_ppdu_id[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+             uint32_t filter_pass_mpdus               :  1, //[0]
+                      filter_pass_mpdus_fcs_ok        :  1, //[1]
+                      monitor_direct_mpdus            :  1, //[2]
+                      monitor_direct_mpdus_fcs_ok     :  1, //[3]
+                      monitor_other_mpdus             :  1, //[4]
+                      monitor_other_mpdus_fcs_ok      :  1, //[5]
+                      reserved_0                      : 10, //[15:6]
+                      phy_ppdu_id                     : 16; //[31:16]
+};
+
+/*
+
+filter_pass_mpdus
+
+			When set, at least one Filter Pass MPDU has been
+			received. FCS might or might not have been passing
+
+			<legal all>
+
+filter_pass_mpdus_fcs_ok
+
+			When set, at least one Filter Pass MPDU has been
+			received that has a correct FCS.
+
+			<legal all>
+
+monitor_direct_mpdus
+
+			When set, at least one Monitor Direct MPDU has been
+			received. FCS might or might not have been passing
+
+			<legal all>
+
+monitor_direct_mpdus_fcs_ok
+
+			When set, at least one Monitor Direct MPDU has been
+			received that has a correct FCS.
+
+			<legal all>
+
+monitor_other_mpdus
+
+			When set, at least one Monitor Direct MPDU has been
+			received. FCS might or might not have been passing
+
+			<legal all>
+
+monitor_other_mpdus_fcs_ok
+
+			When set, at least one Monitor Direct MPDU has been
+			received that has a correct FCS.
+
+			<legal all>
+
+reserved_0
+
+			<legal 0>
+
+phy_ppdu_id
+
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around
+
+			<legal all>
+*/
+
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS
+
+			When set, at least one Filter Pass MPDU has been
+			received. FCS might or might not have been passing
+
+			<legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET  0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB     0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK    0x00000001
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK
+
+			When set, at least one Filter Pass MPDU has been
+			received that has a correct FCS.
+
+			<legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS
+
+			When set, at least one Monitor Direct MPDU has been
+			received. FCS might or might not have been passing
+
+			<legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB  2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK
+
+			When set, at least one Monitor Direct MPDU has been
+			received that has a correct FCS.
+
+			<legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS
+
+			When set, at least one Monitor Direct MPDU has been
+			received. FCS might or might not have been passing
+
+			<legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB   4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK  0x00000010
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK
+
+			When set, at least one Monitor Direct MPDU has been
+			received that has a correct FCS.
+
+			<legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0
+
+			<legal 0>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB            6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK           0x0000ffc0
+
+/* Description		RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID
+
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around
+
+			<legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET        0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB           16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK          0xffff0000
+
+
+#endif // _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_

hw/qca8074/v1/wcss_version.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define WCSS_VERSION 1019