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video: driver: set QOS registers

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Move Qos register programming to driver. Use reset_control_acquire
api to ensure xo clk is on before programming

Change-Id: I52bf416da42675d206e1124368f75f627b8b2e9f
Signed-off-by: Maheshwar Ajja <quic_majja@quicinc.com>
This commit is contained in:
Maheshwar Ajja
2022-12-23 11:20:26 -08:00
committed by Deepa Guthyappa Madivalara
parent b12f5ec06e
commit 78c90f4173
3 changed files with 45 additions and 3 deletions
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11
driver/platform/pineapple/src/msm_vidc_pineapple.c
View File

@@ -2754,6 +2754,17 @@ static struct freq_table pineapple_freq_table_v2[] = {
/* register, value, mask */ /* register, value, mask */
static const struct reg_preset_table pineapple_reg_preset_table[] = { static const struct reg_preset_table pineapple_reg_preset_table[] = {
{ 0xB0088, 0x0, 0x11 }, { 0xB0088, 0x0, 0x11 },
{ 0x13030, 0x33332222, 0xFFFFFFFF},
{ 0x13034, 0x44444444, 0xFFFFFFFF},
{ 0x13038, 0x1022, 0xFFFFFFFF},
{ 0x13040, 0x0, 0xFFFFFFFF},
{ 0x13048, 0xFFFF, 0xFFFFFFFF},
{ 0x13430, 0x33332222, 0xFFFFFFFF},
{ 0x13434, 0x44444444, 0xFFFFFFFF},
{ 0x13438, 0x1022, 0xFFFFFFFF},
{ 0x13440, 0x0, 0xFFFFFFFF},
{ 0x13448, 0xFFFF, 0xFFFFFFFF},
{ 0xA013C, 0x99, 0xFFFFFFFF},
}; };
/* name, phys_addr, size, device_addr, device region type */ /* name, phys_addr, size, device_addr, device region type */

4
driver/variant/common/src/msm_vidc_variant.c
View File

@@ -176,8 +176,8 @@ int __set_registers(struct msm_vidc_core *core)
return 0; return 0;
for (cnt = 0; cnt < prst_count; cnt++) { for (cnt = 0; cnt < prst_count; cnt++) {
rc = __write_register_masked(core, reg_prst->reg, rc = __write_register_masked(core, reg_prst[cnt].reg,
reg_prst->value, reg_prst->mask); reg_prst[cnt].value, reg_prst[cnt].mask);
if (rc) if (rc)
return rc; return rc;
} }

31
driver/variant/iris33/src/msm_vidc_iris33.c
View File

@@ -677,6 +677,7 @@ static int __power_on_iris33(struct msm_vidc_core *core)
struct frequency_table *freq_tbl; struct frequency_table *freq_tbl;
u32 freq = 0; u32 freq = 0;
int rc = 0; int rc = 0;
int count = 0;
if (is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE)) if (is_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE))
return 0; return 0;
@@ -722,15 +723,45 @@ static int __power_on_iris33(struct msm_vidc_core *core)
/* /*
* Re-program all of the registers that get reset as a result of * Re-program all of the registers that get reset as a result of
* regulator_disable() and _enable() * regulator_disable() and _enable()
* When video module writing to QOS registers EVA module is not
* supposed to do video_xo_reset operations else we will see register
* access failure, so acquire video_xo_reset to ensure EVA module is
* not doing assert or de-assert on video_xo_reset.
*/ */
do {
rc = call_res_op(core, reset_control_acquire, core, "video_xo_reset");
if (!rc) {
break;
} else {
d_vpr_e(
"%s: failed to acquire video_xo_reset control, count %d\n",
__func__, count);
count++;
usleep_range(1000, 1000);
}
} while (count < 100);
if (count >= 100) {
d_vpr_e("%s: timeout acquiring video_xo_reset\n", __func__);
goto fail_assert_xo_reset;
}
__set_registers(core); __set_registers(core);
/* release reset control for other consumers */
rc = call_res_op(core, reset_control_release, core, "video_xo_reset");
if (rc) {
d_vpr_e("%s: failed to release video_xo_reset reset\n", __func__);
goto fail_deassert_xo_reset;
}
__interrupt_init_iris33(core); __interrupt_init_iris33(core);
core->intr_status = 0; core->intr_status = 0;
enable_irq(core->resource->irq); enable_irq(core->resource->irq);
return rc; return rc;
fail_deassert_xo_reset:
fail_assert_xo_reset:
fail_power_on_substate: fail_power_on_substate:
__power_off_iris33_hardware(core); __power_off_iris33_hardware(core);
fail_power_on_hardware: fail_power_on_hardware: