qcacmn: Flush srng tp and hp only for flush event

Currently after runtime resume all SW2TCL data and reo cmd
srng rings hp and tp value are flushed. In case of IPA
offload case SW2TCL3 righ hp value will be updated by IPA
and not by host. In case of runtime pm enable host is
setting the value to zero as part of runtime resume which
results in incorrect hp value of SW2TCL3. As part of this
change set flush event for rings which are accessed by host
during link down state and after runtime resume flush the
rings for which flush event is set.

Change-Id: I5c9afa708277cf3a6e6d5ef99447bc21f88cfdcf
CRs-Fixed: 2514621
This commit is contained in:
Sravan Kumar Kairam
2019-09-16 14:22:55 +05:30
committed by nshrivas
parent 816b503c44
commit 78b01a1e1b
6 changed files with 93 additions and 4 deletions

View File

@@ -686,7 +686,6 @@ inline int hal_reo_cmd_update_rx_queue(hal_ring_handle_t hal_ring_hdl,
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
uint32_t *reo_desc, val;
struct hal_reo_cmd_update_queue_params *p;
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
p = &cmd->u.upd_queue_params;
@@ -888,7 +887,8 @@ inline int hal_reo_cmd_update_rx_queue(hal_ring_handle_t hal_ring_hdl,
hif_pm_runtime_put(hal_soc->hif_handle);
} else {
hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
srng->needs_flush++;
hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
hal_srng_inc_flush_cnt(hal_ring_hdl);
}
val = reo_desc[CMD_HEADER_DW_OFFSET];