asoc: codecs: add support for bt swr clock

Add support for BT Soundwire clock.

Change-Id: I27879c2f04144b81fcaf057db1810fb9b80267b4
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>

asoc/codecs/audio-ext-clk-up.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -38,6 +38,9 @@ enum {
 	AUDIO_EXT_CLK_LPASS11,
 	AUDIO_EXT_CLK_LPASS12,
 	AUDIO_EXT_CLK_LPASS13,
+	AUDIO_EXT_CLK_LPASS14,
+	AUDIO_EXT_CLK_LPASS15,
+	AUDIO_EXT_CLK_LPASS16,
 	AUDIO_EXT_CLK_LPASS_MAX,
 	AUDIO_EXT_CLK_EXTERNAL_PLL = AUDIO_EXT_CLK_LPASS_MAX,
 	AUDIO_EXT_CLK_MAX,
@@ -473,6 +476,39 @@ static struct audio_ext_clk audio_clk_array[] = {
 			},
 		},
 	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk14",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk15",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk16",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
 	{
 		.pnctrl_info = {NULL},
 		.fact = {

include/bindings/qcom,audio-ext-clk.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.*/
- */
+/* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.*/
 
 #ifndef __AUDIO_EXT_CLK_H
 #define __AUDIO_EXT_CLK_H
@@ -23,5 +23,7 @@
 #define AUDIO_LPASS_MCLK_11           14 /* WSA_TX CORE CLK */
 #define AUDIO_LPASS_MCLK_12           15 /* WSA2_TX CORE CLK */
 #define AUDIO_LPASS_MCLK_13           16 /* RX_MCLK2 2X CLK */
-
+#define AUDIO_LPASS_MCLK_14           17 /* HW SEQUNCER MCLK */
+#define AUDIO_LPASS_MCLK_15           18 /* BT_SWR CLK */
+#define AUDIO_LPASS_MCLK_16           19 /* BT_SWR 2X CLK */
 #endif