video: driver: update iris3 power collapse sequence

1. Set Iris CPU NoC to Low power
2. Remove Debug bridge Low power
3. Reset MVP QNS4PDXFIFO
4. Remove Disable GCC_VIDEO_AXI0_CLK clock

Change-Id: I4a88589cacc894dc5717e8ccb5f731f62e82202d
Signed-off-by: Chinmay Sawarkar <quic_chinmays@quicinc.com>

driver/variant/iris3/src/msm_vidc_iris3.c

@@ -108,6 +108,8 @@
 
 #define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS3	(WRAPPER_BASE_OFFS_IRIS3 + 0x54)
 #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS3	(WRAPPER_BASE_OFFS_IRIS3 + 0x58)
+#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL	(WRAPPER_BASE_OFFS_IRIS3 + 0x5C)
+#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS		(WRAPPER_BASE_OFFS_IRIS3 + 0x60)
 #define WRAPPER_CORE_CLOCK_CONFIG_IRIS3		(WRAPPER_BASE_OFFS_IRIS3 + 0x88)
 
 /*
@@ -118,6 +120,8 @@
 #define WRAPPER_TZ_BASE_OFFS	0x000C0000
 #define WRAPPER_TZ_CPU_CLOCK_CONFIG	(WRAPPER_TZ_BASE_OFFS)
 #define WRAPPER_TZ_CPU_STATUS	(WRAPPER_TZ_BASE_OFFS + 0x10)
+#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG	(WRAPPER_TZ_BASE_OFFS + 0x14)
+#define WRAPPER_TZ_QNS4PDXFIFO_RESET	(WRAPPER_TZ_BASE_OFFS + 0x18)
 
 #define CTRL_INIT_IRIS3		CPU_CS_SCIACMD_IRIS3
 
@@ -555,15 +559,16 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core)
 	if (rc)
 		d_vpr_h("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
 
-	/* Set Debug bridge Low power */
-	rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS3, 0x7);
+	/* Set Iris CPU NoC to Low power */
+	rc = __write_register_masked(core, WRAPPER_IRIS_CPU_NOC_LPI_CONTROL,
+			0x1, BIT(0));
 	if (rc)
 		return rc;
 
-	rc = __read_register_with_poll_timeout(core, WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS3,
-			0x7, 0x7, 200, 2000);
+	rc = __read_register_with_poll_timeout(core, WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
+			0x1, 0x1, 200, 2000);
 	if (rc)
-		d_vpr_h("%s: debug bridge low power failed\n", __func__);
+		d_vpr_h("%s: WRAPPER_IRIS_CPU_NOC_LPI_CONTROL failed\n", __func__);
 
 	/* Debug bridge LPI release */
 	rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS3, 0x0);
@@ -575,6 +580,23 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core)
 	if (rc)
 		d_vpr_h("%s: debug bridge release failed\n", __func__);
 
+	/* Reset MVP QNS4PDXFIFO */
+	rc = __write_register(core, WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG, 0x3);
+	if (rc)
+		return rc;
+
+	rc = __write_register(core, WRAPPER_TZ_QNS4PDXFIFO_RESET, 0x1);
+	if (rc)
+		return rc;
+
+	rc = __write_register(core, WRAPPER_TZ_QNS4PDXFIFO_RESET, 0x0);
+	if (rc)
+		return rc;
+
+	rc = __write_register(core, WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG, 0x0);
+	if (rc)
+		return rc;
+
 	/* Turn off MVP MVS0C core clock */
 	rc = __disable_unprepare_clock_iris3(core, "core_clk");
 	if (rc) {
@@ -582,19 +604,6 @@ static int __power_off_iris3_controller(struct msm_vidc_core *core)
 		rc = 0;
 	}
 
-	/* Disable GCC_VIDEO_AXI0_CLK clock */
-	rc = __disable_unprepare_clock_iris3(core, "gcc_video_axi0");
-	if (rc) {
-		d_vpr_e("%s: disable unprepare gcc_video_axi0 failed\n", __func__);
-		rc = 0;
-	}
-
-	rc = call_venus_op(core, reset_ahb2axi_bridge, core);
-	if (rc) {
-		d_vpr_e("%s: reset ahb2axi bridge failed\n", __func__);
-		rc = 0;
-	}
-
 	/* power down process */
 	rc = __disable_regulator_iris3(core, "iris-ctl");
 	if (rc) {