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@@ -25,16 +25,16 @@
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/**
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* 21 bits cookie
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- * 3 bits ring id 0 ~ 7, mask 0x1C0000, offset 18
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- * 8 bits page id 0 ~ 255, mask 0x03C800, offset 10
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- * 10 bits offset id 0 ~ 1023 mask 0x0003FF, offset 0
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+ * 3 bits ring id 0 ~ 7,
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+ * 8 bits page id 0 ~ 512
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+ * 5 bits offset id 0 ~ 31 (Desc size = 128, Num descs per page = 4096/128 = 32)
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*/
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/* ???Ring ID needed??? */
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-#define DP_TX_DESC_ID_POOL_MASK 0x1C0000
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-#define DP_TX_DESC_ID_POOL_OS 18
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-#define DP_TX_DESC_ID_PAGE_MASK 0x03FC00
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-#define DP_TX_DESC_ID_PAGE_OS 10
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-#define DP_TX_DESC_ID_OFFSET_MASK 0x0003FF
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+#define DP_TX_DESC_ID_POOL_MASK 0x01C000
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+#define DP_TX_DESC_ID_POOL_OS 14
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+#define DP_TX_DESC_ID_PAGE_MASK 0x003FE0
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+#define DP_TX_DESC_ID_PAGE_OS 5
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+#define DP_TX_DESC_ID_OFFSET_MASK 0x00001F
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#define DP_TX_DESC_ID_OFFSET_OS 0
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#ifdef QCA_LL_TX_FLOW_CONTROL_V2
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