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@@ -9,6 +9,7 @@
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#include "cam_hw.h"
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#include "cam_hw.h"
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#include "cam_ife_csid_hw_intf.h"
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#include "cam_ife_csid_hw_intf.h"
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#include "cam_ife_csid_soc.h"
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#include "cam_ife_csid_soc.h"
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+#include "cam_ife_csid_core.h"
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#define CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED BIT(0)
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#define CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED BIT(0)
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#define CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED BIT(1)
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#define CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED BIT(1)
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@@ -192,6 +193,59 @@ struct cam_ife_csid_rdi_reg_offset {
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uint32_t overflow_ctrl_en;
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uint32_t overflow_ctrl_en;
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};
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};
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+struct cam_ife_csid_udi_reg_offset {
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+ uint32_t csid_udi_irq_status_addr;
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+ uint32_t csid_udi_irq_mask_addr;
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+ uint32_t csid_udi_irq_clear_addr;
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+ uint32_t csid_udi_irq_set_addr;
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+
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+ /* UDI N register address */
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+ uint32_t csid_udi_cfg0_addr;
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+ uint32_t csid_udi_cfg1_addr;
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+ uint32_t csid_udi_ctrl_addr;
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+ uint32_t csid_udi_frm_drop_pattern_addr;
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+ uint32_t csid_udi_frm_drop_period_addr;
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+ uint32_t csid_udi_irq_subsample_pattern_addr;
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+ uint32_t csid_udi_irq_subsample_period_addr;
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+ uint32_t csid_udi_rpp_hcrop_addr;
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+ uint32_t csid_udi_rpp_vcrop_addr;
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+ uint32_t csid_udi_rpp_pix_drop_pattern_addr;
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+ uint32_t csid_udi_rpp_pix_drop_period_addr;
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+ uint32_t csid_udi_rpp_line_drop_pattern_addr;
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+ uint32_t csid_udi_rpp_line_drop_period_addr;
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+ uint32_t csid_udi_yuv_chroma_conversion_addr;
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+ uint32_t csid_udi_rst_strobes_addr;
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+ uint32_t csid_udi_status_addr;
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+ uint32_t csid_udi_misr_val0_addr;
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+ uint32_t csid_udi_misr_val1_addr;
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+ uint32_t csid_udi_misr_val2_addr;
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+ uint32_t csid_udi_misr_val3_addr;
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+ uint32_t csid_udi_format_measure_cfg0_addr;
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+ uint32_t csid_udi_format_measure_cfg1_addr;
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+ uint32_t csid_udi_format_measure0_addr;
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+ uint32_t csid_udi_format_measure1_addr;
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+ uint32_t csid_udi_format_measure2_addr;
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+ uint32_t csid_udi_timestamp_curr0_sof_addr;
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+ uint32_t csid_udi_timestamp_curr1_sof_addr;
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+ uint32_t csid_udi_timestamp_prev0_sof_addr;
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+ uint32_t csid_udi_timestamp_prev1_sof_addr;
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+ uint32_t csid_udi_timestamp_curr0_eof_addr;
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+ uint32_t csid_udi_timestamp_curr1_eof_addr;
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+ uint32_t csid_udi_timestamp_prev0_eof_addr;
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+ uint32_t csid_udi_timestamp_prev1_eof_addr;
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+ uint32_t csid_udi_err_recovery_cfg0_addr;
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+ uint32_t csid_udi_err_recovery_cfg1_addr;
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+ uint32_t csid_udi_err_recovery_cfg2_addr;
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+ uint32_t csid_udi_multi_vcdt_cfg0_addr;
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+ uint32_t csid_udi_byte_cntr_ping_addr;
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+ uint32_t csid_udi_byte_cntr_pong_addr;
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+
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+ /* configuration */
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+ uint32_t packing_format;
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+ uint32_t ccif_violation_en;
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+ uint32_t overflow_ctrl_en;
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+};
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+
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struct cam_ife_csid_csi2_rx_reg_offset {
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struct cam_ife_csid_csi2_rx_reg_offset {
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uint32_t csid_csi2_rx_irq_status_addr;
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uint32_t csid_csi2_rx_irq_status_addr;
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uint32_t csid_csi2_rx_irq_mask_addr;
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uint32_t csid_csi2_rx_irq_mask_addr;
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@@ -288,6 +342,7 @@ struct cam_ife_csid_common_reg_offset {
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uint32_t major_version;
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uint32_t major_version;
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uint32_t minor_version;
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uint32_t minor_version;
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uint32_t version_incr;
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uint32_t version_incr;
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+ uint32_t num_udis;
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uint32_t num_rdis;
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uint32_t num_rdis;
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uint32_t num_pix;
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uint32_t num_pix;
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uint32_t num_ppp;
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uint32_t num_ppp;
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@@ -310,8 +365,10 @@ struct cam_ife_csid_common_reg_offset {
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uint32_t ipp_irq_mask_all;
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uint32_t ipp_irq_mask_all;
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uint32_t rdi_irq_mask_all;
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uint32_t rdi_irq_mask_all;
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uint32_t ppp_irq_mask_all;
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uint32_t ppp_irq_mask_all;
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+ uint32_t udi_irq_mask_all;
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uint32_t measure_en_hbi_vbi_cnt_mask;
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uint32_t measure_en_hbi_vbi_cnt_mask;
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uint32_t format_measure_en_val;
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uint32_t format_measure_en_val;
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+ uint32_t num_bytes_out_shift_val;
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};
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};
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/**
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/**
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@@ -320,7 +377,9 @@ struct cam_ife_csid_common_reg_offset {
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* @cmn_reg: csid common registers info
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* @cmn_reg: csid common registers info
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* @ipp_reg: ipp register offset information
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* @ipp_reg: ipp register offset information
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* @ppp_reg: ppp register offset information
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* @ppp_reg: ppp register offset information
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- * @rdi_reg: rdi register offser information
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+ * @rdi_reg: rdi register offset information
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+ * @udi_reg: udi register offset information
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+ * @tpg_reg: tpg register offset information
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*
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*
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*/
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*/
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struct cam_ife_csid_reg_offset {
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struct cam_ife_csid_reg_offset {
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@@ -329,6 +388,7 @@ struct cam_ife_csid_reg_offset {
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const struct cam_ife_csid_pxl_reg_offset *ipp_reg;
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const struct cam_ife_csid_pxl_reg_offset *ipp_reg;
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const struct cam_ife_csid_pxl_reg_offset *ppp_reg;
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const struct cam_ife_csid_pxl_reg_offset *ppp_reg;
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const struct cam_ife_csid_rdi_reg_offset *rdi_reg[CAM_IFE_CSID_RDI_MAX];
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const struct cam_ife_csid_rdi_reg_offset *rdi_reg[CAM_IFE_CSID_RDI_MAX];
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+ const struct cam_ife_csid_udi_reg_offset *udi_reg[CAM_IFE_CSID_UDI_MAX];
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const struct cam_ife_csid_csi2_tpg_reg_offset *tpg_reg;
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const struct cam_ife_csid_csi2_tpg_reg_offset *tpg_reg;
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};
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};
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@@ -427,6 +487,7 @@ struct cam_ife_csid_cid_data {
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* @master_idx: For Slave reservation, Give master IFE instance Index.
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* @master_idx: For Slave reservation, Give master IFE instance Index.
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* Slave will synchronize with master Start and stop operations
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* Slave will synchronize with master Start and stop operations
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* @clk_rate Clock rate
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* @clk_rate Clock rate
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+ * @num_bytes_out: Number of output bytes per cycle
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*
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*
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*/
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*/
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struct cam_ife_csid_path_cfg {
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struct cam_ife_csid_path_cfg {
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@@ -451,6 +512,7 @@ struct cam_ife_csid_path_cfg {
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uint64_t clk_rate;
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uint64_t clk_rate;
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uint32_t horizontal_bin;
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uint32_t horizontal_bin;
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uint32_t qcfa_bin;
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uint32_t qcfa_bin;
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+ uint32_t num_bytes_out;
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};
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};
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/**
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/**
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@@ -468,12 +530,14 @@ struct cam_ife_csid_path_cfg {
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* @ipp_res: image pixel path resource
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* @ipp_res: image pixel path resource
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* @ppp_res: phase pxl path resource
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* @ppp_res: phase pxl path resource
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* @rdi_res: raw dump image path resources
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* @rdi_res: raw dump image path resources
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+ * @udi_res: udi path resources
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* @cid_res: cid resources state
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* @cid_res: cid resources state
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* @csid_top_reset_complete: csid top reset completion
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* @csid_top_reset_complete: csid top reset completion
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* @csid_csi2_reset_complete: csi2 reset completion
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* @csid_csi2_reset_complete: csi2 reset completion
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* @csid_ipp_reset_complete: ipp reset completion
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* @csid_ipp_reset_complete: ipp reset completion
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* @csid_ppp_complete: ppp reset completion
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* @csid_ppp_complete: ppp reset completion
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* @csid_rdin_reset_complete: rdi n completion
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* @csid_rdin_reset_complete: rdi n completion
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+ * @csid_udin_reset_complete: udi n completion
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* @csid_debug: csid debug information to enable the SOT, EOT,
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* @csid_debug: csid debug information to enable the SOT, EOT,
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* SOF, EOF, measure etc in the csid hw
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* SOF, EOF, measure etc in the csid hw
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* @clk_rate Clock rate
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* @clk_rate Clock rate
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@@ -499,12 +563,14 @@ struct cam_ife_csid_hw {
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struct cam_isp_resource_node ipp_res;
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struct cam_isp_resource_node ipp_res;
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struct cam_isp_resource_node ppp_res;
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struct cam_isp_resource_node ppp_res;
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struct cam_isp_resource_node rdi_res[CAM_IFE_CSID_RDI_MAX];
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struct cam_isp_resource_node rdi_res[CAM_IFE_CSID_RDI_MAX];
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+ struct cam_isp_resource_node udi_res[CAM_IFE_CSID_UDI_MAX];
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struct cam_isp_resource_node cid_res[CAM_IFE_CSID_CID_MAX];
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struct cam_isp_resource_node cid_res[CAM_IFE_CSID_CID_MAX];
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struct completion csid_top_complete;
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struct completion csid_top_complete;
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struct completion csid_csi2_complete;
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struct completion csid_csi2_complete;
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struct completion csid_ipp_complete;
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struct completion csid_ipp_complete;
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struct completion csid_ppp_complete;
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struct completion csid_ppp_complete;
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struct completion csid_rdin_complete[CAM_IFE_CSID_RDI_MAX];
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struct completion csid_rdin_complete[CAM_IFE_CSID_RDI_MAX];
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+ struct completion csid_udin_complete[CAM_IFE_CSID_UDI_MAX];
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uint64_t csid_debug;
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uint64_t csid_debug;
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uint64_t clk_rate;
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uint64_t clk_rate;
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bool sof_irq_triggered;
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bool sof_irq_triggered;
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@@ -517,8 +583,14 @@ struct cam_ife_csid_hw {
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};
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};
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int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf,
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int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf,
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- uint32_t csid_idx);
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+ uint32_t csid_idx, bool is_custom);
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int cam_ife_csid_hw_deinit(struct cam_ife_csid_hw *ife_csid_hw);
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int cam_ife_csid_hw_deinit(struct cam_ife_csid_hw *ife_csid_hw);
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+int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw,
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+ struct cam_csid_hw_reserve_resource_args *cid_reserv);
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+
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+int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw,
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+ struct cam_csid_hw_reserve_resource_args *reserve);
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+
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#endif /* _CAM_IFE_CSID_HW_H_ */
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#endif /* _CAM_IFE_CSID_HW_H_ */
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