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@@ -1,5 +1,5 @@
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/*
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- * Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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@@ -700,65 +700,65 @@ struct targetdef_s {
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#endif
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struct hostdef_s {
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- A_UINT32 d_INT_STATUS_ENABLE_ERROR_LSB;
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- A_UINT32 d_INT_STATUS_ENABLE_ERROR_MASK;
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- A_UINT32 d_INT_STATUS_ENABLE_CPU_LSB;
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- A_UINT32 d_INT_STATUS_ENABLE_CPU_MASK;
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- A_UINT32 d_INT_STATUS_ENABLE_COUNTER_LSB;
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- A_UINT32 d_INT_STATUS_ENABLE_COUNTER_MASK;
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- A_UINT32 d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
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- A_UINT32 d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
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- A_UINT32 d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
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- A_UINT32 d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
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- A_UINT32 d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
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- A_UINT32 d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
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- A_UINT32 d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
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- A_UINT32 d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
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- A_UINT32 d_INT_STATUS_ENABLE_ADDRESS;
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- A_UINT32 d_CPU_INT_STATUS_ENABLE_BIT_LSB;
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- A_UINT32 d_CPU_INT_STATUS_ENABLE_BIT_MASK;
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- A_UINT32 d_HOST_INT_STATUS_ADDRESS;
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- A_UINT32 d_CPU_INT_STATUS_ADDRESS;
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- A_UINT32 d_ERROR_INT_STATUS_ADDRESS;
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- A_UINT32 d_ERROR_INT_STATUS_WAKEUP_MASK;
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- A_UINT32 d_ERROR_INT_STATUS_WAKEUP_LSB;
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- A_UINT32 d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
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- A_UINT32 d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
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- A_UINT32 d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
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- A_UINT32 d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
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- A_UINT32 d_COUNT_DEC_ADDRESS;
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- A_UINT32 d_HOST_INT_STATUS_CPU_MASK;
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- A_UINT32 d_HOST_INT_STATUS_CPU_LSB;
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- A_UINT32 d_HOST_INT_STATUS_ERROR_MASK;
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- A_UINT32 d_HOST_INT_STATUS_ERROR_LSB;
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- A_UINT32 d_HOST_INT_STATUS_COUNTER_MASK;
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- A_UINT32 d_HOST_INT_STATUS_COUNTER_LSB;
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- A_UINT32 d_RX_LOOKAHEAD_VALID_ADDRESS;
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- A_UINT32 d_WINDOW_DATA_ADDRESS;
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- A_UINT32 d_WINDOW_READ_ADDR_ADDRESS;
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- A_UINT32 d_WINDOW_WRITE_ADDR_ADDRESS;
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- A_UINT32 d_SOC_GLOBAL_RESET_ADDRESS;
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- A_UINT32 d_RTC_STATE_ADDRESS;
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- A_UINT32 d_RTC_STATE_COLD_RESET_MASK;
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- A_UINT32 d_PCIE_LOCAL_BASE_ADDRESS;
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- A_UINT32 d_PCIE_SOC_WAKE_RESET;
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- A_UINT32 d_PCIE_SOC_WAKE_ADDRESS;
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- A_UINT32 d_PCIE_SOC_WAKE_V_MASK;
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- A_UINT32 d_RTC_STATE_V_MASK;
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- A_UINT32 d_RTC_STATE_V_LSB;
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- A_UINT32 d_FW_IND_EVENT_PENDING;
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- A_UINT32 d_FW_IND_INITIALIZED;
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- A_UINT32 d_FW_IND_HELPER;
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- A_UINT32 d_RTC_STATE_V_ON;
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+ uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
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+ uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
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+ uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
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+ uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
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+ uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
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+ uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
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+ uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
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+ uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
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+ uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
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+ uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
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+ uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
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+ uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
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+ uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
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+ uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
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+ uint32_t d_INT_STATUS_ENABLE_ADDRESS;
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+ uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
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+ uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
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+ uint32_t d_HOST_INT_STATUS_ADDRESS;
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+ uint32_t d_CPU_INT_STATUS_ADDRESS;
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+ uint32_t d_ERROR_INT_STATUS_ADDRESS;
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+ uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
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+ uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
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+ uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
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+ uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
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+ uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
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+ uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
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+ uint32_t d_COUNT_DEC_ADDRESS;
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+ uint32_t d_HOST_INT_STATUS_CPU_MASK;
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+ uint32_t d_HOST_INT_STATUS_CPU_LSB;
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+ uint32_t d_HOST_INT_STATUS_ERROR_MASK;
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+ uint32_t d_HOST_INT_STATUS_ERROR_LSB;
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+ uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
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+ uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
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+ uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
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+ uint32_t d_WINDOW_DATA_ADDRESS;
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+ uint32_t d_WINDOW_READ_ADDR_ADDRESS;
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+ uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
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+ uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
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+ uint32_t d_RTC_STATE_ADDRESS;
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+ uint32_t d_RTC_STATE_COLD_RESET_MASK;
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+ uint32_t d_PCIE_LOCAL_BASE_ADDRESS;
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+ uint32_t d_PCIE_SOC_WAKE_RESET;
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+ uint32_t d_PCIE_SOC_WAKE_ADDRESS;
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+ uint32_t d_PCIE_SOC_WAKE_V_MASK;
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+ uint32_t d_RTC_STATE_V_MASK;
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+ uint32_t d_RTC_STATE_V_LSB;
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+ uint32_t d_FW_IND_EVENT_PENDING;
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+ uint32_t d_FW_IND_INITIALIZED;
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+ uint32_t d_FW_IND_HELPER;
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+ uint32_t d_RTC_STATE_V_ON;
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#if defined(SDIO_3_0)
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- A_UINT32 d_HOST_INT_STATUS_MBOX_DATA_MASK;
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- A_UINT32 d_HOST_INT_STATUS_MBOX_DATA_LSB;
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+ uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
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+ uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
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#endif
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- A_UINT32 d_PCIE_SOC_RDY_STATUS_ADDRESS;
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- A_UINT32 d_PCIE_SOC_RDY_STATUS_BAR_MASK;
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- A_UINT32 d_SOC_PCIE_BASE_ADDRESS;
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- A_UINT32 d_MSI_MAGIC_ADR_ADDRESS;
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- A_UINT32 d_MSI_MAGIC_ADDRESS;
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+ uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS;
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+ uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK;
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+ uint32_t d_SOC_PCIE_BASE_ADDRESS;
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+ uint32_t d_MSI_MAGIC_ADR_ADDRESS;
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+ uint32_t d_MSI_MAGIC_ADDRESS;
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uint32_t d_HOST_CE_COUNT;
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uint32_t d_ENABLE_MSI;
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uint32_t d_MUX_ID_MASK;
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