qcacmn: Handle ML destination in Intra-BSS code
When destination peer is an ML peer, get the soc from da_peer. Change-Id: I93d10a7ab9ce805180397bcf0f3b404c27df528b CRs-Fixed: 3177339
This commit is contained in:

committed by
Madan Koyyalamudi

parent
55b630d160
commit
74ede2801b
@@ -1289,7 +1289,6 @@ dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
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struct dp_txrx_peer *da_peer;
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struct dp_txrx_peer *da_peer;
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bool ret = false;
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bool ret = false;
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uint8_t dest_chip_id;
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uint8_t dest_chip_id;
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uint8_t soc_idx;
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dp_txrx_ref_handle txrx_ref_handle = NULL;
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dp_txrx_ref_handle txrx_ref_handle = NULL;
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struct dp_vdev_be *be_vdev =
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struct dp_vdev_be *be_vdev =
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dp_get_be_vdev_from_dp_vdev(ta_peer->vdev);
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dp_get_be_vdev_from_dp_vdev(ta_peer->vdev);
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@@ -1303,21 +1302,39 @@ dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
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qdf_assert_always(dest_chip_id <= (DP_MLO_MAX_DEST_CHIP_ID - 1));
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qdf_assert_always(dest_chip_id <= (DP_MLO_MAX_DEST_CHIP_ID - 1));
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da_peer_id = HAL_RX_PEER_ID_GET(msdu_metadata);
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da_peer_id = HAL_RX_PEER_ID_GET(msdu_metadata);
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/* TA is MLD peer */
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/* use dest chip id when TA is MLD peer and DA is legacy */
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if (be_soc->mlo_enabled && ta_peer->mld_peer) {
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if (be_soc->mlo_enabled &&
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ta_peer->mld_peer &&
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!(da_peer_id & HAL_RX_DA_IDX_ML_PEER_MASK)) {
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/* validate chip_id, get a ref, and re-assign soc */
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/* validate chip_id, get a ref, and re-assign soc */
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params->dest_soc =
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params->dest_soc =
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dp_mlo_get_soc_ref_by_chip_id(be_soc->ml_ctxt,
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dp_mlo_get_soc_ref_by_chip_id(be_soc->ml_ctxt,
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dest_chip_id);
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dest_chip_id);
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if (!params->dest_soc)
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if (!params->dest_soc)
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return false;
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return false;
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}
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da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
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da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc,
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&txrx_ref_handle, DP_MOD_ID_RX);
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da_peer_id,
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&txrx_ref_handle,
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DP_MOD_ID_RX);
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if (!da_peer)
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if (!da_peer)
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return false;
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return false;
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/* soc unref if needed */
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ret = true;
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} else {
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da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc,
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da_peer_id,
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&txrx_ref_handle,
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DP_MOD_ID_RX);
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if (!da_peer)
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return false;
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params->dest_soc = da_peer->vdev->pdev->soc;
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if (!params->dest_soc)
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goto rel_da_peer;
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ret = true;
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}
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params->tx_vdev_id = da_peer->vdev->vdev_id;
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params->tx_vdev_id = da_peer->vdev->vdev_id;
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@@ -1339,21 +1356,16 @@ dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
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/* MLO specific Intra-BSS check */
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/* MLO specific Intra-BSS check */
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if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
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if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
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/* TA is legacy peer */
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/* use dest chip id for legacy dest peer */
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if (!ta_peer->mld_peer) {
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if (!(da_peer_id & HAL_RX_DA_IDX_ML_PEER_MASK)) {
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params->dest_soc = da_peer->vdev->pdev->soc;
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if (!(be_vdev->partner_vdev_list[dest_chip_id][0] ==
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ret = true;
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goto rel_da_peer;
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}
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/* index of soc in the array */
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soc_idx = dest_chip_id << DP_MLO_DEST_CHIP_ID_SHIFT;
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if (!(be_vdev->partner_vdev_list[soc_idx][0] ==
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params->tx_vdev_id) &&
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params->tx_vdev_id) &&
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!(be_vdev->partner_vdev_list[soc_idx][1] ==
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!(be_vdev->partner_vdev_list[dest_chip_id][1] ==
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params->tx_vdev_id)) {
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params->tx_vdev_id)) {
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/*dp_soc_unref_delete(soc);*/
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/*dp_soc_unref_delete(soc);*/
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goto rel_da_peer;
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goto rel_da_peer;
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}
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}
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}
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ret = true;
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ret = true;
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}
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}
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@@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* purpose with or without fee is hereby granted, provided that the above
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@@ -27,8 +27,6 @@
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/* Max number of chips supported */
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/* Max number of chips supported */
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#define DP_MLO_MAX_DEST_CHIP_ID 3
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#define DP_MLO_MAX_DEST_CHIP_ID 3
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/* shift value to index into the array, used instead of mult by 2 */
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#define DP_MLO_DEST_CHIP_ID_SHIFT 1
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/*
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/*
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* dp_mlo_ctxt
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* dp_mlo_ctxt
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@@ -28,6 +28,7 @@
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#define HAL_RX_DA_IDX_CHIP_ID_MASK 0x3
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#define HAL_RX_DA_IDX_CHIP_ID_MASK 0x3
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#define HAL_RX_DA_IDX_PEER_ID_MASK 0x3fff
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#define HAL_RX_DA_IDX_PEER_ID_MASK 0x3fff
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#define HAL_RX_DA_IDX_ML_PEER_MASK 0x2000
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/*
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/*
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* macro to set the cookie into the rxdma ring entry
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* macro to set the cookie into the rxdma ring entry
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