fw-api: CL 18000081 - update fw common interface files
add HTT_T2H_PPDU_ID_FMT_IND msg def Change-Id: I5abf71d10ea3c0a0ba17e74e1579b1868d4f4b1a CRs-Fixed: 2262693
This commit is contained in:
spuligil
282
fw/htt.h
282
fw/htt.h
@@ -230,9 +230,10 @@
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* 3.103 Add HTT_T2H_SAWF_MSDUQ_INFO_IND defs.
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* 3.104 Add mgmt/ctrl/data specs in rx ring cfg.
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* 3.105 Add HTT_H2T STREAMING_STATS_REQ + HTT_T2H STREAMING_STATS_IND defs.
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* 3.106 Add HTT_T2H_PPDU_ID_FMT_IND def.
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 105
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#define HTT_CURRENT_VERSION_MINOR 106
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#define HTT_NUM_TX_FRAG_DESC 1024
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@@ -9663,6 +9664,7 @@ enum htt_t2h_msg_type {
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HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND = 0x2e,
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HTT_T2H_SAWF_MSDUQ_INFO_IND = 0x2e, /* alias */
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HTT_T2H_MSG_TYPE_STREAMING_STATS_IND = 0x2f,
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HTT_T2H_PPDU_ID_FMT_IND = 0x30,
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HTT_T2H_MSG_TYPE_TEST,
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@@ -18414,4 +18416,282 @@ PREPACK struct htt_t2h_sawf_msduq_event {
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} while (0)
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/**
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* @brief target -> PPDU id format indication
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*
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* MSG_TYPE => HTT_T2H_PPDU_ID_FMT_IND
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*
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* @details
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* The following field definitions describe the format of the HTT target
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* to host PPDU ID format indication message.
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* hwsch_cmd_id :- A number per ring, increases by one with each HWSCH command.
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* ring_id :- HWSCH ring id in which this PPDU was enqueued.
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* seq_idx :- Sequence control index of this PPDU.
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* link_id :- HW link ID of the link in which the PPDU was enqueued.
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* seq_cmd_type:- WHAL_TXSEND_FTYPE (SU Data, MU Data, SGEN frames etc.)
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* tqm_cmd:-
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*
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* |31 27|26 22|21 17| 16 |15 11|10 8|7 6|5 1| 0 |
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* |--------------------------------------------------+------------------------|
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* | rsvd0 | msg type |
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* |-----+----------+----------+---------+-----+----------+----------+---------|
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* |rsvd2|ring_id OF|ring_id NB|ring_id V|rsvd1|cmd_id OF |cmd_id NB |cmd_id V |
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* |-----+----------+----------+---------+-----+----------+----------+---------|
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* |rsvd4|link_id OF|link_id NB|link_id V|rsvd3|seq_idx OF|seq_idx NB|seq_idx V|
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* |-----+----------+----------+---------+-----+----------+----------+---------|
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* |rsvd6|tqm_cmd OF|tqm_cmd NB|tqm_cmd V|rsvd5|seq_cmd OF|seq_cmd NB|seq_cmd V|
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* |-----+----------+----------+---------+-----+----------+----------+---------|
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* |rsvd8| crc OF | crc NB | crc V |rsvd7|mac_id OF |mac_id NB |mac_id V |
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* |-----+----------+----------+---------+-----+----------+----------+---------|
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* Where: OF = bit offset, NB = number of bits, V = valid
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* The message is interpreted as follows:
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*
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* dword0 - b'7:0 - msg_type: This will be set to
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* HTT_T2H_PPDU_ID_FMT_IND
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* value: 0x30
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*
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* dword0 - b'31:8 - reserved
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*
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* dword1 - b'0:0 - field to indicate whether hwsch_cmd_id is valid or not
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*
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* dword1 - b'5:1 - number of bits in hwsch_cmd_id
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*
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* dword1 - b'10:6 - offset of hwsch_cmd_id (in number of bits)
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*
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* dword1 - b'15:11 - reserved for future use
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*
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* dword1 - b'16:16 - field to indicate whether ring_id is valid or not
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*
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* dword1 - b'21:17 - number of bits in ring_id
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*
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* dword1 - b'26:22 - offset of ring_id (in number of bits)
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*
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* dword1 - b'31:27 - reserved for future use
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*
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* dword2 - b'0:0 - field to indicate whether sequence index is valid or not
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*
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* dword2 - b'5:1 - number of bits in sequence index
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*
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* dword2 - b'10:6 - offset of sequence index (in number of bits)
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*
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* dword2 - b'15:11 - reserved for future use
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*
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* dword2 - b'16:16 - field to indicate whether link_id is valid or not
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*
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* dword2 - b'21:17 - number of bits in link_id
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*
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* dword2 - b'26:22 - offset of link_id (in number of bits)
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*
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* dword2 - b'31:27 - reserved for future use
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*
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* dword3 - b'0:0 - field to indicate whether seq_cmd_type is valid or not
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*
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* dword3 - b'5:1 - number of bits in seq_cmd_type
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*
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* dword3 - b'10:6 - offset of seq_cmd_type (in number of bits)
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*
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* dword3 - b'15:11 - reserved for future use
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*
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* dword3 - b'16:16 - field to indicate whether tqm_cmd is valid or not
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*
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* dword3 - b'21:17 - number of bits in tqm_cmd
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*
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* dword3 - b'26:22 - offset of tqm_cmd (in number of bits)
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*
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* dword3 - b'31:27 - reserved for future use
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*
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* dword4 - b'0:0 - field to indicate whether mac_id is valid or not
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*
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* dword4 - b'5:1 - number of bits in mac_id
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*
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* dword4 - b'10:6 - offset of mac_id (in number of bits)
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*
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* dword4 - b'15:11 - reserved for future use
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*
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* dword4 - b'16:16 - field to indicate whether crc is valid or not
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*
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* dword4 - b'21:17 - number of bits in crc
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*
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* dword4 - b'26:22 - offset of crc (in number of bits)
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*
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* dword4 - b'31:27 - reserved for future use
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*
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*/
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#define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M 0x00000001
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#define HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S 0
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#define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M 0x0000003E
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#define HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S 1
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#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M 0x000007C0
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#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S 6
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#define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M 0x00010000
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#define HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S 16
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#define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M 0x003E0000
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#define HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S 17
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#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M 0x07C00000
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#define HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S 22
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/* macros for accessing lower 16 bits in dword */
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#define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0(word, value) \
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do { \
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HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS15_0, value); \
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(word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S; \
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} while (0)
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#define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS15_0(word) \
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(((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS15_0_S)
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#define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0(word, value) \
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do { \
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HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS15_0, value); \
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(word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S; \
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} while (0)
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#define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS15_0(word) \
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(((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS15_0_S)
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#define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0(word, value) \
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do { \
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HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0, value); \
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(word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S; \
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} while (0)
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#define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS15_0(word) \
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(((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS15_0_S)
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/* macros for accessing upper 16 bits in dword */
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#define HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16(word, value) \
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do { \
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HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_VALID_BITS31_16, value); \
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(word) |= (value) << HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S; \
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} while (0)
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#define HTT_PPDU_ID_FMT_IND_VALID_GET_BITS31_16(word) \
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(((word) & HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_VALID_BITS31_16_S)
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#define HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16(word, value) \
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do { \
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HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_BITS_BITS31_16, value); \
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(word) |= (value) << HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S; \
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} while (0)
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#define HTT_PPDU_ID_FMT_IND_BITS_GET_BITS31_16(word) \
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(((word) & HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_BITS_BITS31_16_S)
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#define HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16(word, value) \
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do { \
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HTT_CHECK_SET_VAL(HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16, value); \
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(word) |= (value) << HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S; \
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} while (0)
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#define HTT_PPDU_ID_FMT_IND_OFFSET_GET_BITS31_16(word) \
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(((word) & HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_M) >> HTT_PPDU_ID_FMT_IND_OFFSET_BITS31_16_S)
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#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_RING_ID_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_RING_ID_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_LINK_ID_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_LINK_ID_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_TQM_CMD_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_TQM_CMD_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_MAC_ID_TYPE_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS15_0
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#define HTT_PPDU_ID_FMT_IND_CRC_VALID_SET \
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HTT_PPDU_ID_FMT_IND_VALID_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_CRC_BITS_SET \
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HTT_PPDU_ID_FMT_IND_BITS_SET_BITS31_16
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#define HTT_PPDU_ID_FMT_IND_CRC_OFFSET_SET \
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HTT_PPDU_ID_FMT_IND_OFFSET_SET_BITS31_16
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/* offsets in number dwords */
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#define HTT_PPDU_ID_FMT_IND_HWSCH_CMD_ID_OFFSET 1
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#define HTT_PPDU_ID_FMT_IND_RING_ID_OFFSET 1
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#define HTT_PPDU_ID_FMT_IND_SEQ_IDX_OFFSET 2
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#define HTT_PPDU_ID_FMT_IND_LINK_ID_OFFSET 2
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#define HTT_PPDU_ID_FMT_IND_SEQ_CMD_TYPE_OFFSET 3
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#define HTT_PPDU_ID_FMT_IND_TQM_CMD_OFFSET 3
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#define HTT_PPDU_ID_FMT_IND_MAC_ID_OFFSET 4
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#define HTT_PPDU_ID_FMT_IND_CRC_OFFSET 4
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typedef struct {
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A_UINT32 msg_type: 8, /* bits 7:0 */
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rsvd0: 24;/* bits 31:8 */
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A_UINT32 hwsch_cmd_id_valid: 1, /* bits 0:0 */
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hwsch_cmd_id_bits: 5, /* bits 5:1 */
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hwsch_cmd_id_offset: 5, /* bits 10:6 */
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rsvd1: 5, /* bits 15:11 */
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ring_id_valid: 1, /* bits 16:16 */
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ring_id_bits: 5, /* bits 21:17 */
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ring_id_offset: 5, /* bits 26:22 */
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rsvd2: 5; /* bits 31:27 */
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A_UINT32 seq_idx_valid: 1, /* bits 0:0 */
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seq_idx_bits: 5, /* bits 5:1 */
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seq_idx_offset: 5, /* bits 10:6 */
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rsvd3: 5, /* bits 15:11 */
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link_id_valid: 1, /* bits 16:16 */
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link_id_bits: 5, /* bits 21:17 */
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link_id_offset: 5, /* bits 26:22 */
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rsvd4: 5; /* bits 31:27 */
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A_UINT32 seq_cmd_type_valid: 1, /* bits 0:0 */
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seq_cmd_type_bits: 5, /* bits 5:1 */
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seq_cmd_type_offset: 5, /* bits 10:6 */
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rsvd5: 5, /* bits 15:11 */
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tqm_cmd_valid: 1, /* bits 16:16 */
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tqm_cmd_bits: 5, /* bits 21:17 */
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tqm_cmd_offset: 5, /* bits 26:12 */
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rsvd6: 5; /* bits 31:27 */
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A_UINT32 mac_id_valid: 1, /* bits 0:0 */
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mac_id_bits: 5, /* bits 5:1 */
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mac_id_offset: 5, /* bits 10:6 */
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rsvd8: 5, /* bits 15:11 */
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crc_valid: 1, /* bits 16:16 */
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crc_bits: 5, /* bits 21:17 */
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crc_offset: 5, /* bits 26:12 */
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rsvd9: 5; /* bits 31:27 */
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} htt_t2h_ppdu_id_fmt_ind_t;
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#endif
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