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msm: camera: csiphy: Add support for delay in IRQ confiq

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Add support to add a delay while programming the IRQ
settings. Also, correct the irq mask bring up sequence
for csiphy2.1.0.

CRs-Fixed: 2923706
Change-Id: I1ef5b078bd91e915b9e53305edc0034d62132831
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
This commit is contained in:
Jigar Agrawal
2021-04-13 12:19:18 -07:00
committed by Gerrit - the friendly Code Review server
parent f77f1673d3
commit 74135ec470
2 changed files with 13 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c
View File

@@ -493,15 +493,20 @@ reset_settings:
void cam_csiphy_cphy_irq_config(struct csiphy_device *csiphy_dev)
{
int32_t i;
int32_t i;
struct csiphy_reg_t *csiphy_irq_reg;
void __iomem *csiphybase =
csiphy_dev->soc_info.reg_map[0].mem_base;
for (i = 0; i < csiphy_dev->num_irq_registers; i++)
cam_io_w_mb(
csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_data,
csiphybase +
csiphy_dev->ctrl_reg->csiphy_irq_reg[i].reg_addr);
for (i = 0; i < csiphy_dev->num_irq_registers; i++) {
csiphy_irq_reg = &csiphy_dev->ctrl_reg->csiphy_irq_reg[i];
cam_io_w_mb(csiphy_irq_reg->reg_data,
csiphybase + csiphy_irq_reg->reg_addr);
if (csiphy_irq_reg->delay)
usleep_range(csiphy_irq_reg->delay,
csiphy_irq_reg->delay + 5);
}
}
void cam_csiphy_cphy_irq_disable(struct csiphy_device *csiphy_dev)

5
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h
View File

@@ -18,7 +18,7 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
.csiphy_3ph_config_array_size = 44,
.csiphy_2ph_clock_lane = 0x1,
.csiphy_2ph_combo_ck_ln = 0x10,
.csiphy_interrupt_status_size = 12,
.csiphy_interrupt_status_size = 11,
};
struct csiphy_reg_t csiphy_common_reg_2_1_0[] = {
@@ -53,8 +53,7 @@ struct csiphy_reg_t csiphy_irq_reg_2_1_0[] = {
{0x1048, 0xef, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x104c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1050, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1054, 0xff, 0x00, CSIPHY_2PH_REGS},
{0x1054, 0xff, 0x64, CSIPHY_3PH_REGS},
{0x1054, 0xff, 0x64, CSIPHY_DEFAULT_PARAMS},
};
struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {