msm: camera: isp: Add debugfs mask to print SFE Cache info

This commit adds debugfs mask(Bit 30) to print SFE Cache
information. This helps to check the SCID settings on SFE
bus read and write master.

Change-Id: I75355bbc167763a09442114f43b23dd1b82e0960
CRs-Fixed: 3197257
Signed-off-by: Gaurav Jindal <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "cam_sfe_bus.h"
@@ -108,7 +109,7 @@ void cam_sfe_bus_parse_cache_cfg(
 	uint32_t scratch_alloc_shift = 0, buf_alloc_shift = 0;
 	uint32_t scratch_cfg, buf_cfg, alloc_type;
 
-	if (debug_val >= DISABLE_CACHING_FOR_ALL) {
+	if (debug_val == DISABLE_CACHING_FOR_ALL) {
 		dbg_cfg->disable_all = true;
 		goto end;
 	}
@@ -123,6 +124,7 @@ void cam_sfe_bus_parse_cache_cfg(
 
 	scratch_cfg = (debug_val >> CACHE_SCRATCH_DEBUG_SHIFT) & 0xF;
 	buf_cfg = (debug_val >> CACHE_BUF_DEBUG_SHIFT) & 0xF;
+	dbg_cfg->print_cache_cfg = (bool)(debug_val >> CACHE_BUF_PRINT_DBG_SHIFT);
 
 	/* Check for scratch cfg */
 	if (scratch_cfg == 0xF) {

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.c

@@ -1352,6 +1352,7 @@ static int cam_sfe_bus_rd_config_rm(void *priv, void *cmd_args,
 	struct cam_sfe_bus_cache_dbg_cfg       *cache_dbg_cfg = NULL;
 	uint32_t width = 0, height = 0, stride = 0, width_in_bytes = 0;
 	uint32_t i, img_addr = 0, img_offset = 0;
+	uint32_t curr_cache_cfg = 0;
 	dma_addr_t iova;
 
 	bus_priv = (struct cam_sfe_bus_rd_priv  *) priv;
@@ -1403,7 +1404,7 @@ static int cam_sfe_bus_rd_config_rm(void *priv, void *cmd_args,
 			rm_data->unpacker_cfg, &width_in_bytes);
 		rm_data->height = height;
 		rm_data->width = width;
-
+		curr_cache_cfg = rm_data->cache_cfg;
 		rm_data->cache_cfg = 0x20;
 		if ((!cache_dbg_cfg->disable_for_scratch) &&
 			(rm_data->enable_caching)) {
@@ -1414,6 +1415,14 @@ static int cam_sfe_bus_rd_config_rm(void *priv, void *cmd_args,
 				rm_data->cache_cfg |= cache_dbg_cfg->scratch_alloc;
 			else
 				rm_data->cache_cfg |= CACHE_ALLOC_FORGET;
+
+			if (cache_dbg_cfg->print_cache_cfg &&
+				(curr_cache_cfg != rm_data->cache_cfg)) {
+				CAM_INFO(CAM_SFE,
+					"SFE:%d Scratch Buff RM:%d current_scid:%d cache_cfg:0x%x",
+					rm_data->common_data->core_index,
+					rm_data->index, rm_data->current_scid, rm_data->cache_cfg);
+			}
 		}
 
 		cam_io_w_mb(rm_data->cache_cfg,
@@ -1478,6 +1487,7 @@ static int cam_sfe_bus_rd_update_rm(void *priv, void *cmd_args,
 	uint32_t width = 0, height = 0, stride = 0, width_in_bytes = 0;
 	uint32_t i, j, size = 0, img_addr = 0, img_offset = 0;
 	dma_addr_t iova;
+	uint32_t curr_cache_cfg = 0;
 
 	bus_priv = (struct cam_sfe_bus_rd_priv  *) priv;
 	update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args;
@@ -1545,6 +1555,7 @@ static int cam_sfe_bus_rd_update_rm(void *priv, void *cmd_args,
 		rm_data->height = height;
 		rm_data->width = width;
 
+		curr_cache_cfg = rm_data->cache_cfg;
 		rm_data->cache_cfg = 0x20;
 		if (rm_data->enable_caching) {
 			if ((cache_dbg_cfg->disable_for_scratch) &&
@@ -1570,6 +1581,13 @@ static int cam_sfe_bus_rd_update_rm(void *priv, void *cmd_args,
 				else
 					rm_data->cache_cfg |= CACHE_ALLOC_DEALLOC;
 			}
+
+			if (cache_dbg_cfg->print_cache_cfg &&
+				(curr_cache_cfg != rm_data->cache_cfg)) {
+				CAM_INFO(CAM_SFE, "SFE:%d RM:%d current_scid:%d cache_cfg:0x%x",
+					rm_data->common_data->core_index,
+					rm_data->index, rm_data->current_scid, rm_data->cache_cfg);
+			}
 		}
 
 skip_cache_cfg:

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -2489,6 +2489,7 @@ static int cam_sfe_bus_wr_update_wm(void *priv, void *cmd_args,
 	uint32_t frame_inc = 0, val;
 	uint32_t stride = 0, slice_h = 0;
 	dma_addr_t iova;
+	uint32_t curr_cache_cfg = 0;
 
 	bus_priv = (struct cam_sfe_bus_wr_priv *) priv;
 	update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args;
@@ -2537,6 +2538,7 @@ static int cam_sfe_bus_wr_update_wm(void *priv, void *cmd_args,
 			wm_data->index, sfe_out_data->wm_res[i].res_name,
 			reg_val_pair[j-1]);
 
+		curr_cache_cfg = wm_data->cache_cfg;
 		wm_data->cache_cfg = 0;
 		if (wm_data->enable_caching) {
 			if ((cache_dbg_cfg->disable_for_scratch) &&
@@ -2558,6 +2560,13 @@ static int cam_sfe_bus_wr_update_wm(void *priv, void *cmd_args,
 				wm_data->cache_cfg |= cache_dbg_cfg->buf_alloc;
 			else
 				wm_data->cache_cfg |= CACHE_ALLOC_ALLOC;
+
+			if (cache_dbg_cfg->print_cache_cfg &&
+				(curr_cache_cfg != wm_data->cache_cfg)) {
+				CAM_INFO(CAM_SFE, "SFE:%d WM:%d current_scid:%d cache_cfg:0x%x",
+					wm_data->common_data->core_index,
+					wm_data->index, wm_data->current_scid, wm_data->cache_cfg);
+			}
 		}
 
 skip_cache_cfg:
@@ -2696,6 +2705,7 @@ static int cam_sfe_bus_wr_config_wm(void *priv, void *cmd_args,
 	uint32_t frame_inc = 0, val, img_addr = 0, img_offset = 0;
 	uint32_t stride = 0, slice_h = 0;
 	dma_addr_t iova;
+	uint32_t curr_cache_cfg = 0;
 
 	bus_priv = (struct cam_sfe_bus_wr_priv  *) priv;
 	update_buf =  (struct cam_isp_hw_get_cmd_update *) cmd_args;
@@ -2788,6 +2798,7 @@ static int cam_sfe_bus_wr_config_wm(void *priv, void *cmd_args,
 			wm_data->index, frame_inc,
 			CAM_BOOL_TO_YESNO(cam_smmu_is_expanded_memory));
 
+		curr_cache_cfg = wm_data->cache_cfg;
 		wm_data->cache_cfg = 0;
 		if ((!cache_dbg_cfg->disable_for_scratch) &&
 			(wm_data->enable_caching)) {
@@ -2798,6 +2809,14 @@ static int cam_sfe_bus_wr_config_wm(void *priv, void *cmd_args,
 				wm_data->cache_cfg |= cache_dbg_cfg->scratch_alloc;
 			else
 				wm_data->cache_cfg |= CACHE_ALLOC_ALLOC;
+
+			if (cache_dbg_cfg->print_cache_cfg &&
+				(curr_cache_cfg != wm_data->cache_cfg)) {
+				CAM_INFO(CAM_SFE,
+					"SFE:%d Scratch Buff WM:%d current_scid:%d cache_cfg:0x%x",
+					wm_data->common_data->core_index,
+					wm_data->index, wm_data->current_scid, wm_data->cache_cfg);
+			}
 		}
 
 		cam_io_w_mb(wm_data->cache_cfg,

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/include/cam_sfe_bus.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_SFE_BUS_H_
@@ -37,6 +38,7 @@
 #define CACHE_BUF_RD_ALLOC_SHIFT          12
 #define CACHE_BUF_WR_ALLOC_SHIFT          16
 #define CACHE_BUF_DEBUG_SHIFT             20
+#define CACHE_BUF_PRINT_DBG_SHIFT         26
 
 enum cam_sfe_bus_plane_type {
 	PLANE_Y,
@@ -55,24 +57,24 @@ enum cam_sfe_bus_type {
  *
  * @Brief:                   Bus cache debug cfg
  *
+ * @scratch_alloc:           Alloc type for scratch
+ * @buf_alloc:               Alloc type for actual buffer
  * @disable_all:             Disable caching for all [scratch/snapshot]
  * @disable_for_scratch:     Disable caching for scratch
  * @scratch_dbg_cfg:         Scratch alloc configured
- * @scratch_alloc:           Alloc type for scratch
  * @disable_for_buf:         Disable caching for buffer
  * @buf_dbg_cfg:             Buf alloc configured
- * @buf_alloc:               Alloc type for actual buffer
+ * @print_cache_cfg:         Print cache cfg
  */
 struct cam_sfe_bus_cache_dbg_cfg {
+	uint32_t scratch_alloc;
+	uint32_t buf_alloc;
 	bool disable_all;
-
 	bool disable_for_scratch;
 	bool scratch_dbg_cfg;
-	uint32_t scratch_alloc;
-
 	bool disable_for_buf;
 	bool buf_dbg_cfg;
-	uint32_t buf_alloc;
+	bool print_cache_cfg;
 };
 
 /*