fw-api: CL 16708104 - update fw common interface files
Change-Id: I99ba71e5d79f689c45fd9d5ecca22d940dad61d7 HTT: add fp_phy_err specs in htt_rx_ring_selection_cfg_t CRs-Fixed: 2262693
这个提交包含在:
88
fw/htt.h
88
fw/htt.h
@@ -5609,6 +5609,32 @@ enum htt_srng_ring_id {
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* by host. 1 -> subscribed
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* by host. 1 -> subscribed
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* - b`11 - mo_ndp: Flag to indicate MO NDP status tlv is subscribed
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* - b`11 - mo_ndp: Flag to indicate MO NDP status tlv is subscribed
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* by host. 1 -> subscribed
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* by host. 1 -> subscribed
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* - b`12 - fp_phy_err: Flag to indicate FP PHY status tlv is
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* subscribed by host. 1 -> subscribed
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* - b`13:14 - fp_phy_err_buf_src: This indicates the source ring
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* selection for the FP PHY ERR status tlv.
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* 0 - wbm2rxdma_buf_source_ring
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* 1 - fw2rxdma_buf_source_ring
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* 2 - sw2rxdma_buf_source_ring
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* 3 - no_buffer_ring
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* - b`15:16 - fp_phy_err_buf_dest: This indicates the destination ring
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* selection for the FP PHY ERR status tlv.
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* 0 - rxdma_release_ring
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* 1 - rxdma2fw_ring
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* 2 - rxdma2sw_ring
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* 3 - rxdma2reo_ring
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* dword12 - b'0:31 - phy_err_mask: This field is to select the fp phy errors
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* which have to be posted to host from phy.
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* Corresponding to errors defined in
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* phyrx_abort_request_reason enums 0 to 31.
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* Refer to RXPCU register definition header files for the
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* phyrx_abort_request_reason enum definition.
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* dword13 - b'0:31 - phy_err_mask_cont: This field is to select the fp phy
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* errors which have to be posted to host from phy.
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* Corresponding to errors defined in
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* phyrx_abort_request_reason enums 32 to 63.
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* Refer to RXPCU register definition header files for the
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* phyrx_abort_request_reason enum definition.
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*/
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*/
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PREPACK struct htt_rx_ring_selection_cfg_t {
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PREPACK struct htt_rx_ring_selection_cfg_t {
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A_UINT32 msg_type: 8,
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A_UINT32 msg_type: 8,
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@@ -5637,7 +5663,12 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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A_UINT32 rx_drop_threshold: 10,
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A_UINT32 rx_drop_threshold: 10,
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fp_ndp: 1,
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fp_ndp: 1,
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mo_ndp: 1,
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mo_ndp: 1,
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rsvd4: 20;
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fp_phy_err: 1,
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fp_phy_err_buf_src: 2,
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fp_phy_err_buf_dest: 2,
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rsvd4: 15;
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A_UINT32 phy_err_mask;
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A_UINT32 phy_err_mask_cont;
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} POSTPACK;
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} POSTPACK;
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#define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t))
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#define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t))
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@@ -5884,6 +5915,61 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_MO_NDP_S)); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_MO_NDP_S)); \
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} while (0)
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M 0x00001000
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S 12
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_M) >> \
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HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S)
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M 0x00006000
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S 13
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_M) >> \
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HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S)
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_SRC_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M 0x00018000
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S 15
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_M) >> \
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HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S)
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#define HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_PHY_ERR_BUF_DEST_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M 0xffffffff
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S 0
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_M) >> \
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HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S)
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_S)); \
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} while (0)
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M 0xffffffff
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S 0
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_GET(_var) \
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(((_var) & HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_M) >> \
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HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S)
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#define HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT, _val); \
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((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PHY_ERR_MASK_CONT_S)); \
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} while (0)
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/*
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/*
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* Subtype based MGMT frames enable bits.
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* Subtype based MGMT frames enable bits.
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