disp: msm: sde: add multirect error status for ubwc and meta
This change adds support for error checking ubwc and meta error status based off whether REC0 or RECT1 is used. Change-Id: I7c39755da99a9d6c0d02b4ef16fa93b8ec7458a9 Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This commit is contained in:
@@ -2279,7 +2279,7 @@ static void sde_crtc_frame_event_cb(void *data, u32 event)
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struct sde_crtc_frame_event *fevent;
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struct sde_kms_frame_event_cb_data *cb_data;
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struct drm_plane *plane;
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u32 ubwc_error;
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u32 ubwc_error, meta_error;
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unsigned long flags;
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u32 crtc_id;
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@@ -2322,13 +2322,14 @@ static void sde_crtc_frame_event_cb(void *data, u32 event)
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drm_for_each_plane_mask(plane, crtc->dev,
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sde_crtc->plane_mask_old) {
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ubwc_error = sde_plane_get_ubwc_error(plane);
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if (ubwc_error) {
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SDE_EVT32(DRMID(crtc), DRMID(plane),
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ubwc_error, SDE_EVTLOG_ERROR);
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SDE_DEBUG("crtc%d plane %d ubwc_error %d\n",
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DRMID(crtc), DRMID(plane),
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ubwc_error);
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meta_error = sde_plane_get_meta_error(plane);
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if (ubwc_error | meta_error) {
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SDE_EVT32(DRMID(crtc), DRMID(plane), ubwc_error,
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meta_error, SDE_EVTLOG_ERROR);
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SDE_DEBUG("crtc%d plane %d ubwc_error %d meta_error %d\n",
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DRMID(crtc), DRMID(plane), ubwc_error, meta_error);
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sde_plane_clear_ubwc_error(plane);
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sde_plane_clear_meta_error(plane);
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}
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}
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}
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@@ -1744,6 +1744,9 @@ static void sde_sspp_set_features(struct sde_mdss_cfg *sde_cfg,
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if (sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
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set_bit(SDE_PERF_SSPP_SYS_CACHE, &sspp->perf_features);
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if (sde_cfg->sspp_multirect_error)
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set_bit(SDE_SSPP_MULTIRECT_ERROR, &sspp->features);
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if (sde_cfg->has_decimation) {
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sblk->maxhdeciexp = MAX_HORZ_DECIMATION;
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sblk->maxvdeciexp = MAX_VERT_DECIMATION;
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@@ -4827,6 +4830,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
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sde_cfg->dither_luma_mode_support = true;
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sde_cfg->mdss_hw_block_size = 0x158;
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sde_cfg->syscache_supported = true;
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sde_cfg->sspp_multirect_error = true;
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} else {
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SDE_ERROR("unsupported chipset id:%X\n", hw_rev);
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sde_cfg->perf.min_prefill_lines = 0xffff;
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@@ -252,6 +252,7 @@ enum {
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* @SDE_SSPP_BLOCK_SEC_UI Blocks secure-ui layers
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* @SDE_SSPP_SCALER_QSEED3LITE Qseed3lite algorithm support
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* @SDE_SSPP_TRUE_INLINE_ROT Support of SSPP true inline rotation v1
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* @SDE_SSPP_MULTIRECT_ERROR SSPP has error based on RECT0 or RECT1
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* @SDE_SSPP_PREDOWNSCALE Support pre-downscale X-direction by 2 for inline
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* @SDE_SSPP_PREDOWNSCALE_Y Support pre-downscale Y-direction for inline
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* @SDE_SSPP_INLINE_CONST_CLR Inline rotation requires const clr disabled
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@@ -283,6 +284,7 @@ enum {
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SDE_SSPP_BLOCK_SEC_UI,
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SDE_SSPP_SCALER_QSEED3LITE,
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SDE_SSPP_TRUE_INLINE_ROT,
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SDE_SSPP_MULTIRECT_ERROR,
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SDE_SSPP_PREDOWNSCALE,
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SDE_SSPP_PREDOWNSCALE_Y,
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SDE_SSPP_INLINE_CONST_CLR,
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@@ -1416,6 +1418,7 @@ struct sde_perf_cfg {
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* @true_inline_rot_rev inline rotator feature revision
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* @macrotile_mode UBWC parameter for macro tile channel distribution
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* @pipe_order_type indicate if it is required to specify pipe order
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* @sspp_multirect_error flag to indicate whether ubwc and meta error by rect is supported
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* @delay_prg_fetch_start indicates if throttling the fetch start is required
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* @has_qsync Supports qsync feature
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* @has_3d_merge_reset Supports 3D merge reset
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@@ -1489,6 +1492,7 @@ struct sde_mdss_cfg {
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u32 true_inline_rot_rev;
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u32 macrotile_mode;
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u32 pipe_order_type;
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bool sspp_multirect_error;
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bool delay_prg_fetch_start;
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bool has_qsync;
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bool has_3d_merge_reset;
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#include "sde_hwio.h"
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@@ -86,6 +86,7 @@
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#define SSPP_SW_PIX_EXT_C3_LR 0x120
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#define SSPP_SW_PIX_EXT_C3_TB 0x124
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#define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128
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#define SSPP_META_ERROR_STATUS 0X12C
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#define SSPP_TRAFFIC_SHAPER 0x130
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#define SSPP_CDP_CNTL 0x134
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#define SSPP_UBWC_ERROR_STATUS 0x138
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@@ -95,6 +96,8 @@
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#define SSPP_TRAFFIC_SHAPER_REC1 0x158
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#define SSPP_EXCL_REC_SIZE 0x1B4
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#define SSPP_EXCL_REC_XY 0x1B8
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#define SSPP_META_ERROR_STATUS_REC1 0x1C4
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#define SSPP_UBWC_ERROR_STATUS_REC1 0x1C8
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#define SSPP_VIG_OP_MODE 0x0
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#define SSPP_VIG_CSC_10_OP_MODE 0x0
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#define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF
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@@ -417,25 +420,81 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx,
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SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
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}
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static void sde_hw_sspp_clear_ubwc_error(struct sde_hw_pipe *ctx)
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static void sde_hw_sspp_clear_ubwc_error(struct sde_hw_pipe *ctx, uint32_t multirect_index)
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{
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struct sde_hw_blk_reg_map *c;
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c = &ctx->hw;
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SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
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}
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static u32 sde_hw_sspp_get_ubwc_error(struct sde_hw_pipe *ctx)
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static u32 sde_hw_sspp_get_ubwc_error(struct sde_hw_pipe *ctx, uint32_t multirect_index)
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{
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struct sde_hw_blk_reg_map *c;
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u32 reg_code;
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c = &ctx->hw;
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reg_code = SDE_REG_READ(c, SSPP_UBWC_ERROR_STATUS);
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return reg_code;
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}
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static void sde_hw_sspp_clear_ubwc_error_v1(struct sde_hw_pipe *ctx, uint32_t multirect_index)
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{
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struct sde_hw_blk_reg_map *c;
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c = &ctx->hw;
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if (multirect_index == SDE_SSPP_RECT_1)
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SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS_REC1, BIT(31));
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else
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SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
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}
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static u32 sde_hw_sspp_get_ubwc_error_v1(struct sde_hw_pipe *ctx, uint32_t multirect_index)
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{
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struct sde_hw_blk_reg_map *c;
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u32 reg_code;
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c = &ctx->hw;
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if (multirect_index == SDE_SSPP_RECT_1)
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reg_code = SDE_REG_READ(c, SSPP_UBWC_ERROR_STATUS_REC1);
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else
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reg_code = SDE_REG_READ(c, SSPP_UBWC_ERROR_STATUS);
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return reg_code;
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}
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static void sde_hw_sspp_clear_meta_error(struct sde_hw_pipe *ctx, uint32_t multirect_index)
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{
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struct sde_hw_blk_reg_map *c;
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c = &ctx->hw;
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if (multirect_index == SDE_SSPP_RECT_1)
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SDE_REG_WRITE(c, SSPP_META_ERROR_STATUS_REC1, BIT(31));
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else
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SDE_REG_WRITE(c, SSPP_META_ERROR_STATUS, BIT(31));
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}
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static u32 sde_hw_sspp_get_meta_error(struct sde_hw_pipe *ctx, uint32_t multirect_index)
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{
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struct sde_hw_blk_reg_map *c;
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u32 reg_code;
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c = &ctx->hw;
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if (multirect_index == SDE_SSPP_RECT_1)
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reg_code = SDE_REG_READ(c, SSPP_META_ERROR_STATUS_REC1);
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else
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reg_code = SDE_REG_READ(c, SSPP_META_ERROR_STATUS);
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return reg_code;
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}
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static void sde_hw_sspp_setup_secure(struct sde_hw_pipe *ctx,
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enum sde_sspp_multirect_index rect_mode,
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bool enable)
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@@ -1253,6 +1312,17 @@ static void _setup_layer_ops(struct sde_hw_pipe *c,
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c->ops.setup_scaler = reg_dmav1_setup_vig_qseed3;
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}
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if (test_bit(SDE_SSPP_MULTIRECT_ERROR, &features)) {
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c->ops.get_meta_error = sde_hw_sspp_get_meta_error;
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c->ops.clear_meta_error = sde_hw_sspp_clear_meta_error;
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c->ops.get_ubwc_error = sde_hw_sspp_get_ubwc_error_v1;
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c->ops.clear_ubwc_error = sde_hw_sspp_clear_ubwc_error_v1;
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} else {
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c->ops.get_ubwc_error = sde_hw_sspp_get_ubwc_error;
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c->ops.clear_ubwc_error = sde_hw_sspp_clear_ubwc_error;
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}
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if (test_bit(SDE_SSPP_PREDOWNSCALE, &features))
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c->ops.setup_pre_downscale = sde_hw_sspp_setup_pre_downscale;
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@@ -1271,9 +1341,6 @@ static void _setup_layer_ops(struct sde_hw_pipe *c,
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c->ops.setup_inverse_pma = sde_hw_sspp_setup_dgm_inverse_pma;
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else if (test_bit(SDE_SSPP_INVERSE_PMA, &features))
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c->ops.setup_inverse_pma = sde_hw_sspp_setup_inverse_pma;
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c->ops.get_ubwc_error = sde_hw_sspp_get_ubwc_error;
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c->ops.clear_ubwc_error = sde_hw_sspp_clear_ubwc_error;
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}
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static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_SSPP_H
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@@ -591,17 +591,33 @@ struct sde_hw_sspp_ops {
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void (*setup_dgm_csc)(struct sde_hw_pipe *ctx,
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enum sde_sspp_multirect_index index, struct sde_csc_cfg *data);
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/**
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* clear_meta_error - clear the meta error-code registers
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* @ctx: Pointer to pipe context
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* @multirect_index: rec in use
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*/
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void (*clear_meta_error)(struct sde_hw_pipe *ctx, uint32_t multirect_index);
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/**
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* get_meta_error - get the meta error-code
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* @ctx: Pointer to pipe context
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* @multirect_index: rec in use
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*/
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u32 (*get_meta_error)(struct sde_hw_pipe *ctx, uint32_t multirect_index);
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/**
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* clear_ubwc_error - clear the ubwc error-code registers
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* @ctx: Pointer to pipe context
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* @multirect_index: rec in use
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*/
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void (*clear_ubwc_error)(struct sde_hw_pipe *ctx);
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void (*clear_ubwc_error)(struct sde_hw_pipe *ctx, uint32_t multirect_index);
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/**
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* get_ubwc_error - get the ubwc error-code
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* @ctx: Pointer to pipe context
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* @multirect_index: rec in use
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*/
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u32 (*get_ubwc_error)(struct sde_hw_pipe *ctx);
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u32 (*get_ubwc_error)(struct sde_hw_pipe *ctx, uint32_t multirect_index);
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};
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/**
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@@ -4276,15 +4276,18 @@ u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
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{
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u32 ubwc_error = 0;
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struct sde_plane *psde;
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struct sde_plane_state *pstate;
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if (!plane) {
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SDE_ERROR("invalid plane\n");
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return 0;
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}
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psde = to_sde_plane(plane);
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pstate = to_sde_plane_state(plane->state);
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if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
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ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw);
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ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
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pstate->multirect_index);
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return ubwc_error;
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}
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@@ -4292,15 +4295,53 @@ u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
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void sde_plane_clear_ubwc_error(struct drm_plane *plane)
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{
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struct sde_plane *psde;
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struct sde_plane_state *pstate;
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if (!plane) {
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SDE_ERROR("invalid plane\n");
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return;
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}
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psde = to_sde_plane(plane);
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pstate = to_sde_plane_state(plane->state);
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if (psde->pipe_hw->ops.clear_ubwc_error)
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psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw);
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psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
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}
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u32 sde_plane_get_meta_error(struct drm_plane *plane)
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{
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u32 meta_error = 0;
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struct sde_plane *psde;
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struct sde_plane_state *pstate;
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if (!plane) {
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SDE_ERROR("invalid plane\n");
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return 0;
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}
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psde = to_sde_plane(plane);
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pstate = to_sde_plane_state(plane->state);
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if (psde->pipe_hw->ops.get_meta_error)
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meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
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pstate->multirect_index);
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return meta_error;
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}
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void sde_plane_clear_meta_error(struct drm_plane *plane)
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{
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struct sde_plane *psde;
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struct sde_plane_state *pstate;
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if (!plane) {
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SDE_ERROR("invalid plane\n");
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return;
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}
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psde = to_sde_plane(plane);
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pstate = to_sde_plane_state(plane->state);
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if (psde->pipe_hw->ops.clear_meta_error)
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psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
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}
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#ifdef CONFIG_DEBUG_FS
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@@ -317,6 +317,18 @@ u32 sde_plane_get_ubwc_error(struct drm_plane *plane);
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*/
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void sde_plane_clear_ubwc_error(struct drm_plane *plane);
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/*
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* sde_plane_get_meta_error - gets the meta error code
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* @plane: Pointer to DRM plane object
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*/
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u32 sde_plane_get_meta_error(struct drm_plane *plane);
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/*
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* sde_plane_clear_meta_error - clears the meta error code
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* @plane: Pointer to DRM plane object
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*/
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void sde_plane_clear_meta_error(struct drm_plane *plane);
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/*
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* sde_plane_setup_src_split_order - enable/disable pipe's src_split_order
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* @plane: Pointer to DRM plane object
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